Merge changes from topic "ti-k3-checks-and-refactor" into integration
* changes:
fix(ti): fix typo in boot authentication message name
refactor(ti): remove empty validate_ns_entrypoint function
refactor(ti): use console_set_scope() rather than empty function hack
refactor(ti): factor out common board code into common files
feat(ti): add PSCI system_off support
feat(ti): do not handle EAs in EL3
feat(ti): set snoop-delayed exclusive handling on A72 cores
feat(ti): disable L2 dataless UniqueClean evictions
feat(ti): set L2 cache ECC and and parity on A72 cores
feat(ti): set L2 cache data ram latency on A72 cores to 4 cycles
diff --git a/include/lib/cpus/aarch32/cortex_a72.h b/include/lib/cpus/aarch32/cortex_a72.h
index 4b1af61..954f736 100644
--- a/include/lib/cpus/aarch32/cortex_a72.h
+++ b/include/lib/cpus/aarch32/cortex_a72.h
@@ -37,16 +37,21 @@
#define CORTEX_A72_CPUACTLR_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_CPUACTLR_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A72_CPUACTLR_DIS_INSTR_PREFETCH (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
/*******************************************************************************
* L2 Control register specific definitions.
******************************************************************************/
#define CORTEX_A72_L2CTLR p15, 1, c9, c0, 2
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
+
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h
index 1777645..bef9337 100644
--- a/include/lib/cpus/aarch64/cortex_a72.h
+++ b/include/lib/cpus/aarch64/cortex_a72.h
@@ -40,6 +40,7 @@
#define CORTEX_A72_CPUACTLR_EL1_NO_ALLOC_WBWA (ULL(1) << 49)
#define CORTEX_A72_CPUACTLR_EL1_DCC_AS_DCCI (ULL(1) << 44)
#define CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH (ULL(1) << 32)
+#define CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP (ULL(1) << 31)
/*******************************************************************************
* L2 Auxiliary Control register specific definitions.
@@ -60,6 +61,9 @@
******************************************************************************/
#define CORTEX_A72_L2CTLR_EL1 S3_1_C11_C0_2
+#define CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE (ULL(1) << 21)
+#define CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE (ULL(1) << 20)
+
#define CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT U(0)
#define CORTEX_A72_L2CTLR_DATA_RAM_SETUP_SHIFT U(5)
#define CORTEX_A72_L2CTLR_TAG_RAM_LATENCY_SHIFT U(6)
@@ -68,6 +72,7 @@
#define CORTEX_A72_L2_DATA_RAM_LATENCY_MASK U(0x7)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_MASK U(0x7)
#define CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES U(0x2)
+#define CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES U(0x3)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_2_CYCLES U(0x1)
#define CORTEX_A72_L2_TAG_RAM_LATENCY_3_CYCLES U(0x2)
diff --git a/plat/ti/k3/board/generic/board.mk b/plat/ti/k3/board/generic/board.mk
index ef74cd6..58c966a 100644
--- a/plat/ti/k3/board/generic/board.mk
+++ b/plat/ti/k3/board/generic/board.mk
@@ -4,21 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the full prioritized communication scheme
K3_SEC_PROXY_LITE := 0
$(eval $(call add_define,K3_SEC_PROXY_LITE))
# System coherency is managed in hardware
USE_COHERENT_MEM := 1
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/generic/include \
diff --git a/plat/ti/k3/board/generic/include/board_def.h b/plat/ti/k3/board/generic/include/board_def.h
index 4ff687c..edfa73f 100644
--- a/plat/ti/k3/board/generic/include/board_def.h
+++ b/plat/ti/k3/board/generic/include/board_def.h
@@ -15,29 +15,9 @@
#define K3_CLUSTER2_CORE_COUNT U(2)
#define K3_CLUSTER3_CORE_COUNT U(2)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
-
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/j784s4/board.mk b/plat/ti/k3/board/j784s4/board.mk
index 92433ab..21d4151 100644
--- a/plat/ti/k3/board/j784s4/board.mk
+++ b/plat/ti/k3/board/j784s4/board.mk
@@ -4,21 +4,17 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the full prioritized communication scheme
K3_SEC_PROXY_LITE := 0
$(eval $(call add_define,K3_SEC_PROXY_LITE))
+# Use a 4 cycle data RAM latency for J784s4
+K3_DATA_RAM_4_LATENCY := 1
+$(eval $(call add_define,K3_DATA_RAM_4_LATENCY))
+
+# Delay snoop exclusive handling for J784s4
+K3_EXCLUSIVE_SNOOP_DELAY := 1
+$(eval $(call add_define,K3_EXCLUSIVE_SNOOP_DELAY))
+
# System coherency is managed in hardware
USE_COHERENT_MEM := 1
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/j784s4/include \
diff --git a/plat/ti/k3/board/j784s4/include/board_def.h b/plat/ti/k3/board/j784s4/include/board_def.h
index c2debc7..c817999 100644
--- a/plat/ti/k3/board/j784s4/include/board_def.h
+++ b/plat/ti/k3/board/j784s4/include/board_def.h
@@ -14,30 +14,10 @@
#define K3_CLUSTER1_CORE_COUNT U(4)
#define K3_CLUSTER2_CORE_COUNT U(0)
#define K3_CLUSTER3_CORE_COUNT U(0)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
#define PLAT_PROC_START_ID U(32)
-
#define PLAT_PROC_DEVICE_START_ID U(202)
#define PLAT_CLUSTER_DEVICE_START_ID U(198)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/board/lite/board.mk b/plat/ti/k3/board/lite/board.mk
index 76246be..2fa09ad 100644
--- a/plat/ti/k3/board/lite/board.mk
+++ b/plat/ti/k3/board/lite/board.mk
@@ -4,21 +4,9 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-BL32_BASE ?= 0x9e800000
-$(eval $(call add_define,BL32_BASE))
-
-PRELOADED_BL33_BASE ?= 0x80080000
-$(eval $(call add_define,PRELOADED_BL33_BASE))
-
-K3_HW_CONFIG_BASE ?= 0x82000000
-$(eval $(call add_define,K3_HW_CONFIG_BASE))
-
# Define sec_proxy usage as the lite version
K3_SEC_PROXY_LITE := 1
$(eval $(call add_define,K3_SEC_PROXY_LITE))
# We dont have system level coherency capability
USE_COHERENT_MEM := 0
-
-PLAT_INCLUDES += \
- -Iplat/ti/k3/board/lite/include \
diff --git a/plat/ti/k3/board/lite/include/board_def.h b/plat/ti/k3/board/lite/include/board_def.h
index fd4e5b1..f523198 100644
--- a/plat/ti/k3/board/lite/include/board_def.h
+++ b/plat/ti/k3/board/lite/include/board_def.h
@@ -15,31 +15,9 @@
#define K3_CLUSTER2_CORE_COUNT U(0)
#define K3_CLUSTER3_CORE_COUNT U(0)
-/*
- * This RAM will be used for the bootloader including code, bss, and stacks.
- * It may need to be increased if BL31 grows in size.
- * Current computation assumes data structures necessary for GIC and ARM for
- * a single cluster of 4 processor.
- *
- * The link addresses are determined by SEC_SRAM_BASE + offset.
- * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
- * SEC_SRAM_BASE is really arbitrary.
- *
- * When ENABLE_PIE is unset, SEC_SRAM_BASE should be chosen so that
- * it matches to the physical address where BL31 is loaded, that is,
- * SEC_SRAM_BASE should be the base address of the RAM region.
- *
- * Lets make things explicit by mapping SRAM_BASE to 0x0 since ENABLE_PIE is
- * defined as default for our platform.
- */
-#define SEC_SRAM_BASE UL(0x00000000) /* PIE remapped on fly */
-#define SEC_SRAM_SIZE UL(0x00020000) /* 128k */
-
-#define PLAT_MAX_OFF_STATE U(2)
-#define PLAT_MAX_RET_STATE U(1)
-
#define PLAT_PROC_START_ID U(32)
#define PLAT_PROC_DEVICE_START_ID U(135)
#define PLAT_CLUSTER_DEVICE_START_ID U(134)
+#define PLAT_BOARD_DEVICE_ID U(157)
#endif /* BOARD_DEF_H */
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
index 2cbfa3d..569e60c 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci.c
@@ -1432,7 +1432,7 @@
struct ti_sci_xfer xfer;
int ret;
- ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMIAGE, 0,
+ ret = ti_sci_setup_one_xfer(TISCI_MSG_PROC_AUTH_BOOT_IMAGE, 0,
&req, sizeof(req),
&resp, sizeof(resp),
&xfer);
diff --git a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
index d220612..1b1a910 100644
--- a/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
+++ b/plat/ti/k3/common/drivers/ti_sci/ti_sci_protocol.h
@@ -47,7 +47,7 @@
#define TISCI_MSG_PROC_HANDOVER 0xc005
#define TISCI_MSG_SET_PROC_BOOT_CONFIG 0xc100
#define TISCI_MSG_SET_PROC_BOOT_CTRL 0xc101
-#define TISCI_MSG_PROC_AUTH_BOOT_IMIAGE 0xc120
+#define TISCI_MSG_PROC_AUTH_BOOT_IMAGE 0xc120
#define TISCI_MSG_GET_PROC_BOOT_STATUS 0xc400
#define TISCI_MSG_WAIT_PROC_BOOT_STATUS 0xc401
diff --git a/plat/ti/k3/common/k3_bl31_setup.c b/plat/ti/k3/common/k3_bl31_setup.c
index 457c95d..9a1fd94 100644
--- a/plat/ti/k3/common/k3_bl31_setup.c
+++ b/plat/ti/k3/common/k3_bl31_setup.c
@@ -67,7 +67,8 @@
assert(arg0 == 0U);
assert(arg1 == 0U);
- bl31_console_setup();
+ /* Initialize the console to provide early debug support */
+ k3_console_setup();
#ifdef BL32_BASE
/* Populate entry point information for BL32 */
@@ -120,6 +121,10 @@
k3_gic_init();
ti_sci_init();
+
+ if (ti_sci_device_get(PLAT_BOARD_DEVICE_ID)) {
+ WARN("Unable to take system power reference\n");
+ }
}
void platform_mem_init(void)
@@ -164,14 +169,6 @@
return SYS_COUNTER_FREQ_IN_TICKS;
}
-/*
- * Empty function to prevent the console from being uninitialized after BL33 is
- * started and allow us to see messages from BL31.
- */
-void bl31_plat_runtime_setup(void)
-{
-}
-
/*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image
* for the security state specified. BL3-3 corresponds to the non-secure
diff --git a/plat/ti/k3/common/k3_console.c b/plat/ti/k3/common/k3_console.c
index 8c44c17..1b01c9b 100644
--- a/plat/ti/k3/common/k3_console.c
+++ b/plat/ti/k3/common/k3_console.c
@@ -11,11 +11,14 @@
#include <k3_console.h>
-void bl31_console_setup(void)
+void k3_console_setup(void)
{
static console_t console;
- /* Initialize the console to provide early debug support */
console_16550_register(K3_USART_BASE, K3_USART_CLK_SPEED,
K3_USART_BAUD, &console);
+
+ console_set_scope(&console, CONSOLE_FLAG_BOOT |
+ CONSOLE_FLAG_RUNTIME |
+ CONSOLE_FLAG_CRASH);
}
diff --git a/plat/ti/k3/common/k3_helpers.S b/plat/ti/k3/common/k3_helpers.S
index f4f7d18..f997b46 100644
--- a/plat/ti/k3/common/k3_helpers.S
+++ b/plat/ti/k3/common/k3_helpers.S
@@ -105,8 +105,32 @@
/* Cortex-A72 specific settings */
a72:
mrs x0, CORTEX_A72_L2CTLR_EL1
- orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#if K3_DATA_RAM_4_LATENCY
+ /* Set L2 cache data RAM latency to 4 cycles */
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_4_CYCLES << \
+ CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#else
+ /* Set L2 cache data RAM latency to 3 cycles */
+ orr x0, x0, #(CORTEX_A72_L2_DATA_RAM_LATENCY_3_CYCLES << \
+ CORTEX_A72_L2CTLR_DATA_RAM_LATENCY_SHIFT)
+#endif
+ /* Enable L2 ECC and parity with inline data */
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_ECC_AND_PARITY_ENABLE
+ orr x0, x0, #CORTEX_A72_L2CTLR_EL1_DATA_INLINE_ECC_ENABLE
msr CORTEX_A72_L2CTLR_EL1, x0
+
+ mrs x0, CORTEX_A72_L2ACTLR_EL1
+ /* Enable L2 UniqueClean evictions with data */
+ orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN
+ msr CORTEX_A72_L2ACTLR_EL1, x0
+
+#if K3_EXCLUSIVE_SNOOP_DELAY
+ mrs x0, CORTEX_A72_CPUACTLR_EL1
+ /* Set Snoop-delayed exclusive handling */
+ orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DELAY_EXCLUSIVE_SNOOP
+ msr CORTEX_A72_CPUACTLR_EL1, x0
+#endif
+
isb
ret
endfunc plat_reset_handler
diff --git a/plat/ti/k3/common/k3_psci.c b/plat/ti/k3/common/k3_psci.c
index 6febbc6..d846495 100644
--- a/plat/ti/k3/common/k3_psci.c
+++ b/plat/ti/k3/common/k3_psci.c
@@ -205,7 +205,14 @@
static void __dead2 k3_system_off(void)
{
- ERROR("System Off: operation not handled.\n");
+ int ret;
+
+ /* Queue up the system shutdown request */
+ ret = ti_sci_device_put_no_wait(PLAT_BOARD_DEVICE_ID);
+ if (ret != 0) {
+ ERROR("Sending system shutdown message failed (%d)\n", ret);
+ }
+
while (true)
wfi();
}
@@ -227,13 +234,6 @@
return PSCI_E_SUCCESS;
}
-static int k3_validate_ns_entrypoint(uintptr_t entrypoint)
-{
- /* TODO: perform the proper validation */
-
- return PSCI_E_SUCCESS;
-}
-
#if K3_PM_SYSTEM_SUSPEND
static void k3_pwr_domain_suspend(const psci_power_state_t *target_state)
{
@@ -281,7 +281,6 @@
.system_off = k3_system_off,
.system_reset = k3_system_reset,
.validate_power_state = k3_validate_power_state,
- .validate_ns_entrypoint = k3_validate_ns_entrypoint
};
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
diff --git a/plat/ti/k3/common/plat_common.mk b/plat/ti/k3/common/plat_common.mk
index 026d6a3..fb633a8 100644
--- a/plat/ti/k3/common/plat_common.mk
+++ b/plat/ti/k3/common/plat_common.mk
@@ -27,7 +27,6 @@
ERRATA_A72_1319367 := 1
CRASH_REPORTING := 1
-HANDLE_EA_EL3_FIRST_NS := 1
# Split out RO data into a non-executable section
SEPARATE_CODE_AND_RODATA := 1
diff --git a/plat/ti/k3/include/k3_console.h b/plat/ti/k3/include/k3_console.h
index 6376ab3..51b322c 100644
--- a/plat/ti/k3/include/k3_console.h
+++ b/plat/ti/k3/include/k3_console.h
@@ -7,6 +7,6 @@
#ifndef K3_CONSOLE_H
#define K3_CONSOLE_H
-void bl31_console_setup(void);
+void k3_console_setup(void);
#endif /* K3_CONSOLE_H */
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index 81a383a..ae3775a 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -38,21 +38,31 @@
PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
+#define PLAT_MAX_OFF_STATE U(2)
+#define PLAT_MAX_RET_STATE U(1)
/*******************************************************************************
* Memory layout constants
******************************************************************************/
/*
- * ARM-TF lives in SRAM, partition it here
+ * This RAM will be used for the bootloader including code, bss, and stacks.
+ * It may need to be increased if BL31 grows in size.
*
- * BL3-1 specific defines.
+ * The link addresses are determined by BL31_BASE + offset.
+ * When ENABLE_PIE is set, the TF images can be loaded anywhere, so
+ * BL31_BASE is really arbitrary.
*
- * Put BL3-1 at the base of the Trusted SRAM.
+ * When ENABLE_PIE is unset, BL31_BASE should be chosen so that
+ * it matches to the physical address where BL31 is loaded, that is,
+ * BL31_BASE should be the base address of the RAM region.
+ *
+ * Lets make things explicit by mapping BL31_BASE to 0x0 since ENABLE_PIE is
+ * defined as default for our platform.
*/
-#define BL31_BASE SEC_SRAM_BASE
-#define BL31_SIZE SEC_SRAM_SIZE
-#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
+#define BL31_BASE UL(0x00000000) /* PIE remapped on fly */
+#define BL31_SIZE UL(0x00020000) /* 128k */
+#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
/*
* Defines the maximum number of translation tables that are allocated by the
diff --git a/plat/ti/k3/platform.mk b/plat/ti/k3/platform.mk
index 2de21aa..bce9ef1 100644
--- a/plat/ti/k3/platform.mk
+++ b/plat/ti/k3/platform.mk
@@ -10,5 +10,16 @@
include ${PLAT_PATH}/common/plat_common.mk
include ${PLAT_PATH}/board/${TARGET_BOARD}/board.mk
+BL32_BASE ?= 0x9e800000
+$(eval $(call add_define,BL32_BASE))
+
+PRELOADED_BL33_BASE ?= 0x80080000
+$(eval $(call add_define,PRELOADED_BL33_BASE))
+
+K3_HW_CONFIG_BASE ?= 0x82000000
+$(eval $(call add_define,K3_HW_CONFIG_BASE))
+
+PLAT_INCLUDES += -Iplat/ti/k3/board/${TARGET_BOARD}/include
+
# modify BUILD_PLAT to point to board specific build directory
BUILD_PLAT := $(abspath ${BUILD_BASE})/${PLAT}/${TARGET_BOARD}/${BUILD_TYPE}