Merge "AArch64: Fix assertions in processing dynamic relocations" into integration
diff --git a/docs/plat/marvell/armada/build.rst b/docs/plat/marvell/armada/build.rst
index 54182cb..2c2bd68 100644
--- a/docs/plat/marvell/armada/build.rst
+++ b/docs/plat/marvell/armada/build.rst
@@ -86,6 +86,20 @@
There is no reason to enable this feature if OP-TEE OS built with CFG_WITH_PAGER=n.
Only set LLC_SRAM=1 if OP-TEE OS is built with CFG_WITH_PAGER=y.
+- CM3_SYSTEM_RESET
+
+ For Armada37x0 only, when ``CM3_SYSTEM_RESET=1``, the Cortex-M3 secure coprocessor will
+ be used for system reset.
+ TF-A will send command 0x0009 with a magic value via the rWTM mailbox interface to the
+ Cortex-M3 secure coprocessor.
+ The firmware running in the coprocessor must either implement this functionality or
+ ignore the 0x0009 command (which is true for the firmware from A3700-utils-marvell
+ repository). If this option is enabled but the firmware does not support this command,
+ an error message will be printed prior trying to reboot via the usual way.
+
+ This option is needed on Turris MOX as a workaround to a HW bug which causes reset to
+ sometime hang the board.
+
- MARVELL_SECURE_BOOT
Build trusted(=1)/non trusted(=0) image, default is non trusted.
@@ -209,7 +223,8 @@
.. code:: shell
- > make USE_COHERENT_MEM=0 PLAT=a3700 BL33=/path/to/u-boot.bin CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
+ > make USE_COHERENT_MEM=0 PLAT=a3700 CM3_SYSTEM_RESET=1 BL33=/path/to/u-boot.bin \
+ CROSS_COMPILE=aarch64-linux-gnu- mrvl_bootimage
Supported MARVELL_PLATFORM are:
- a3700 (for both A3720 DB and EspressoBin)
diff --git a/drivers/renesas/rcar/emmc/emmc_cmd.c b/drivers/renesas/rcar/emmc/emmc_cmd.c
index a2e25e3..d255bff 100644
--- a/drivers/renesas/rcar/emmc/emmc_cmd.c
+++ b/drivers/renesas/rcar/emmc/emmc_cmd.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
#include "micro_delay.h"
static void emmc_little_to_big(uint8_t *p, uint32_t value)
@@ -22,6 +22,7 @@
p[1] = (uint8_t) (value >> 16);
p[2] = (uint8_t) (value >> 8);
p[3] = (uint8_t) value;
+
}
static void emmc_softreset(void)
@@ -64,7 +65,6 @@
SETR_32(SD_INFO2, SD_INFO2_CLEAR);
SETR_32(SD_INFO1_MASK, 0x00000000U); /* all interrupt disable */
SETR_32(SD_INFO2_MASK, SD_INFO2_CLEAR); /* all interrupt disable */
-
}
static void emmc_read_response(uint32_t *response)
@@ -96,8 +96,7 @@
{
HAL_MEMCARD_RESPONSE_TYPE response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
if (response == NULL)
return EMMC_ERR_PARAM;
@@ -117,7 +116,7 @@
}
return EMMC_ERR_CARD_STATUS_BIT;
}
- return EMMC_SUCCESS;;
+ return EMMC_SUCCESS;
}
if (response_type == HAL_MEMCARD_RESPONSE_R4) {
@@ -223,11 +222,11 @@
state = ESTATE_BEGIN;
response_type =
- (HAL_MEMCARD_RESPONSE_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_RESPONSE_TYPE_MASK);
+ ((HAL_MEMCARD_RESPONSE_TYPE)mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_RESPONSE_TYPE_MASK);
cmd_type =
- (HAL_MEMCARD_COMMAND_TYPE) (mmc_drv_obj.cmd_info.
- cmd & HAL_MEMCARD_COMMAND_TYPE_MASK);
+ ((HAL_MEMCARD_COMMAND_TYPE) mmc_drv_obj.cmd_info.cmd &
+ HAL_MEMCARD_COMMAND_TYPE_MASK);
/* state machine */
while ((mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END)) {
@@ -427,8 +426,9 @@
case ESTATE_ACCESS_END:
/* clear flag */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -448,8 +448,9 @@
case ESTATE_TRANSFER_ERROR:
/* The error occurred in the Data transfer. */
- if (HAL_MEMCARD_DMA == mmc_drv_obj.transfer_mode) {
- SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR); /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ if (mmc_drv_obj.transfer_mode == HAL_MEMCARD_DMA) {
+ /* W (CC_EXT_MODE, H'0000_1010) SD_BUF DMA transfer disabled */
+ SETR_32(CC_EXT_MODE, CC_EXT_MODE_CLEAR);
SETR_32(SD_STOP, 0x00000000U);
mmc_drv_obj.during_dma_transfer = FALSE;
}
@@ -468,8 +469,8 @@
default:
state = ESTATE_END;
break;
- } /* switch (state) */
- } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
+ } /* switch (state) */
+ } /* while ( (mmc_drv_obj.force_terminate != TRUE) && (state != ESTATE_END) ) */
/* force terminate */
if (mmc_drv_obj.force_terminate == TRUE) {
@@ -481,7 +482,7 @@
ERROR("BL2: emmc exec_cmd:EMMC_ERR_FORCE_TERMINATE\n");
emmc_softreset();
- return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
+ return EMMC_ERR_FORCE_TERMINATE; /* error information has already been written. */
}
/* success */
diff --git a/drivers/renesas/rcar/emmc/emmc_config.h b/drivers/renesas/rcar/emmc/emmc_config.h
index 686ccb9..16b6b8a 100644
--- a/drivers/renesas/rcar/emmc/emmc_config.h
+++ b/drivers/renesas/rcar/emmc/emmc_config.h
@@ -1,40 +1,20 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/**
- * @file emmc_config.h
- * @brief Configuration file
- *
- */
-
#ifndef EMMC_CONFIG_H
#define EMMC_CONFIG_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
-/** @brief MMC driver config
- */
-#define EMMC_RCA 1UL /* RCA */
-#define EMMC_RW_DATA_TIMEOUT 0x40UL /* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
-#define EMMC_RETRY_COUNT 0 /* how many times to try after fail. Don't change. */
-#define EMMC_CMD_MAX 60UL /* Don't change. */
-
-/** @brief etc
- */
-#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
-
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
+/* RCA */
+#define EMMC_RCA 1UL
+/* 314ms (freq = 400KHz, timeout Counter = 0x04(SDCLK * 2^17) */
+#define EMMC_RW_DATA_TIMEOUT 0x40UL
+/* how many times to try after fail. Don't change. */
+#define EMMC_RETRY_COUNT 0
+#define EMMC_CMD_MAX 60UL /* Don't change. */
-/* ********************************* CODE ********************************** */
+#define LOADIMAGE_FLAGS_DMA_ENABLE 0x00000001UL
#endif /* EMMC_CONFIG_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_hal.h b/drivers/renesas/rcar/emmc/emmc_hal.h
index f0b7e9d..0a85517 100644
--- a/drivers/renesas/rcar/emmc/emmc_hal.h
+++ b/drivers/renesas/rcar/emmc/emmc_hal.h
@@ -1,100 +1,81 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/**
- * @file emmc_hal.h
- * @brief emmc boot driver is expecting this header file
- *
- */
-
#ifndef EMMC_HAL_H
#define EMMC_HAL_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-#include <stdint.h>
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-/** @brief memory card error/status types
- */
-#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
-#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
-#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
-#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
-#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
-#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
-#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
-#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
-#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
-#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
-#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
-#define HAL_MEMCARD_CC_ERROR 0x00100000L
-#define HAL_MEMCARD_ERROR 0x00080000L
-#define HAL_MEMCARD_UNDERRUN 0x00040000L
-#define HAL_MEMCARD_OVERRUN 0x00020000L
-#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
-#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
-#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
-#define HAL_MEMCARD_ERASE_RESET 0x00002000L
-#define HAL_MEMCARD_CARD_STATE 0x00001E00L
-#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
-#define HAL_MEMCARD_APP_CMD 0x00000020L
-#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
-#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
-#define HAL_MEMCARD_NO_ERRORS 0x00000000L
-
-/** @brief Memory card response types
- */
-#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
+/* memory card error/status types */
+#define HAL_MEMCARD_OUT_OF_RANGE 0x80000000L
+#define HAL_MEMCARD_ADDRESS_ERROR 0x40000000L
+#define HAL_MEMCARD_BLOCK_LEN_ERROR 0x20000000L
+#define HAL_MEMCARD_ERASE_SEQ_ERROR 0x10000000L
+#define HAL_MEMCARD_ERASE_PARAM 0x08000000L
+#define HAL_MEMCARD_WP_VIOLATION 0x04000000L
+#define HAL_MEMCARD_CARD_IS_LOCKED 0x02000000L
+#define HAL_MEMCARD_LOCK_UNLOCK_FAILED 0x01000000L
+#define HAL_MEMCARD_COM_CRC_ERROR 0x00800000L
+#define HAL_MEMCARD_ILEGAL_COMMAND 0x00400000L
+#define HAL_MEMCARD_CARD_ECC_FAILED 0x00200000L
+#define HAL_MEMCARD_CC_ERROR 0x00100000L
+#define HAL_MEMCARD_ERROR 0x00080000L
+#define HAL_MEMCARD_UNDERRUN 0x00040000L
+#define HAL_MEMCARD_OVERRUN 0x00020000L
+#define HAL_MEMCARD_CIDCSD_OVERWRITE 0x00010000L
+#define HAL_MEMCARD_WP_ERASE_SKIP 0x00008000L
+#define HAL_MEMCARD_CARD_ECC_DISABLED 0x00004000L
+#define HAL_MEMCARD_ERASE_RESET 0x00002000L
+#define HAL_MEMCARD_CARD_STATE 0x00001E00L
+#define HAL_MEMCARD_CARD_READY_FOR_DATA 0x00000100L
+#define HAL_MEMCARD_APP_CMD 0x00000020L
+#define HAL_MEMCARD_SWITCH_ERROR 0x00000080L
+#define HAL_MEMCARD_AKE_SEQ_ERROR 0x00000008L
+#define HAL_MEMCARD_NO_ERRORS 0x00000000L
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+/* Memory card response types */
+#define HAL_MEMCARD_COMMAND_INDEX_MASK 0x0003f
-/** @brief Type of the return value.
- */
+/* Type of the return value. */
typedef enum {
HAL_MEMCARD_FAIL = 0U,
HAL_MEMCARD_OK = 1U,
- HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /**< DMA channel allocation failed */
- HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /**< DMA transfer failed */
- HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /**< A non-masked error bit was set in the card status */
- HAL_MEMCARD_CMD_TIMEOUT = 5U, /**< Command timeout occurred */
- HAL_MEMCARD_DATA_TIMEOUT = 6U, /**< Data timeout occurred */
- HAL_MEMCARD_CMD_CRC_ERROR = 7U, /**< Command CRC error occurred */
- HAL_MEMCARD_DATA_CRC_ERROR = 8U /**< Data CRC error occurred */
+ HAL_MEMCARD_DMA_ALLOC_FAIL = 2U, /* DMA channel allocation failed */
+ HAL_MEMCARD_DMA_TRANSFER_FAIL = 3U, /* DMA transfer failed */
+ HAL_MEMCARD_CARD_STATUS_ERROR = 4U, /* card status non-masked error */
+ HAL_MEMCARD_CMD_TIMEOUT = 5U, /* Command timeout occurred */
+ HAL_MEMCARD_DATA_TIMEOUT = 6U, /* Data timeout occurred */
+ HAL_MEMCARD_CMD_CRC_ERROR = 7U, /* Command CRC error occurred */
+ HAL_MEMCARD_DATA_CRC_ERROR = 8U /* Data CRC error occurred */
} HAL_MEMCARD_RETURN;
-/** @brief memory access operation
- */
+/* memory access operation */
typedef enum {
- HAL_MEMCARD_READ = 0U, /**< read */
- HAL_MEMCARD_WRITE = 1U /**< write */
+ HAL_MEMCARD_READ = 0U, /* read */
+ HAL_MEMCARD_WRITE = 1U /* write */
} HAL_MEMCARD_OPERATION;
-/** @brief Type of data width on memorycard bus
- */
+/* Type of data width on memorycard bus */
typedef enum {
HAL_MEMCARD_DATA_WIDTH_1_BIT = 0U,
HAL_MEMCARD_DATA_WIDTH_4_BIT = 1U,
HAL_MEMCARD_DATA_WIDTH_8_BIT = 2U
-} HAL_MEMCARD_DATA_WIDTH; /**< data (bus) width types */
+} HAL_MEMCARD_DATA_WIDTH; /* data (bus) width types */
-/** @brief Presence of the memory card
- */
+/* Presence of the memory card */
typedef enum {
HAL_MEMCARD_CARD_IS_IN = 0U,
HAL_MEMCARD_CARD_IS_OUT = 1U
} HAL_MEMCARD_PRESENCE_STATUS; /* presence status of the memory card */
-/** @brief mode of data transfer
- */
+/* mode of data transfer */
typedef enum {
HAL_MEMCARD_DMA = 0U,
HAL_MEMCARD_NOT_DMA = 1U
} HAL_MEMCARD_DATA_TRANSFER_MODE;
-/** @brief Memory card response types.
- */
+/* Memory card response types. */
typedef enum hal_memcard_response_type {
HAL_MEMCARD_RESPONSE_NONE = 0x00000U,
HAL_MEMCARD_RESPONSE_R1 = 0x00100U,
@@ -108,8 +89,7 @@
HAL_MEMCARD_RESPONSE_TYPE_MASK = 0x00f00U
} HAL_MEMCARD_RESPONSE_TYPE;
-/** @brief Memory card command types.
- */
+/* Memory card command types. */
typedef enum hal_memcard_command_type {
HAL_MEMCARD_COMMAND_TYPE_BC = 0x00000U,
HAL_MEMCARD_COMMAND_TYPE_BCR = 0x01000U,
@@ -119,8 +99,7 @@
HAL_MEMCARD_COMMAND_TYPE_MASK = 0x07000U
} HAL_MEMCARD_COMMAND_TYPE;
-/** @brief Type of memory card
- */
+/* Type of memory card */
typedef enum hal_memcard_command_card_type {
HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON = 0x00000U,
HAL_MEMCARD_COMMAND_CARD_TYPE_MMC = 0x08000U,
@@ -128,191 +107,429 @@
HAL_MEMCARD_COMMAND_CARD_TYPE_MASK = 0x18000U
} HAL_MEMCARD_COMMAND_CARD_TYPE;
-/** @brief Memory card application command.
- */
+/* Memory card application command. */
typedef enum hal_memcard_command_app_norm {
HAL_MEMCARD_COMMAND_NORMAL = 0x00000U,
HAL_MEMCARD_COMMAND_APP = 0x20000U,
HAL_MEMCARD_COMMAND_APP_NORM_MASK = 0x20000U
} HAL_MEMCARD_COMMAND_APP_NORM;
-/** @brief Memory card command codes.
- */
+/* Memory card command codes. */
typedef enum {
/* class 0 and class 1 */
- CMD0_GO_IDLE_STATE = 0 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD0 */
- CMD1_SEND_OP_COND = 1 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD1 */
- CMD2_ALL_SEND_CID_MMC = 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD2 */
+ /* CMD0 */
+ CMD0_GO_IDLE_STATE =
+ 0U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t) HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD1 */
+ CMD1_SEND_OP_COND =
+ 1U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD2 */
+ CMD2_ALL_SEND_CID_MMC =
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
CMD2_ALL_SEND_CID_SD =
- 2 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD3_SET_RELATIVE_ADDR = 3 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD3 */
+ 2U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD3 */
+ CMD3_SET_RELATIVE_ADDR =
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
CMD3_SEND_RELATIVE_ADDR =
- 3 | HAL_MEMCARD_RESPONSE_R6 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD4_SET_DSR = 4 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_BC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD4 */
- CMD5_SLEEP_AWAKE = 5 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD5 */
- CMD6_SWITCH = 6 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD6 */
+ 3U | (uint32_t)HAL_MEMCARD_RESPONSE_R6 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD4 */
+ CMD4_SET_DSR =
+ 4U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD5 */
+ CMD5_SLEEP_AWAKE =
+ 5U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD6 */
+ CMD6_SWITCH =
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
CMD6_SWITCH_FUNC =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
ACMD6_SET_BUS_WIDTH =
- 6 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD7_SELECT_CARD = 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7 */
- CMD7_SELECT_CARD_PROG = 7 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD7(from Disconnected State to Programming State) */
+ 6U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD7 */
+ CMD7_SELECT_CARD =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD7(from Disconnected State to Programming State) */
+ CMD7_SELECT_CARD_PROG =
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
CMD7_DESELECT_CARD =
- 7 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL,
- CMD8_SEND_EXT_CSD = 8 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD8 */
+ 7U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD8 */
+ CMD8_SEND_EXT_CSD =
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
CMD8_SEND_IF_COND =
- 8 | HAL_MEMCARD_RESPONSE_R7 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL,
- CMD9_SEND_CSD = 9 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD9 */
- CMD10_SEND_CID = 10 | HAL_MEMCARD_RESPONSE_R2 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD10 */
- CMD11_READ_DAT_UNTIL_STOP = 11 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD11 */
- CMD12_STOP_TRANSMISSION = 12 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12 */
- CMD12_STOP_TRANSMISSION_WRITE = 12 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD12(R1b : write case) */
- CMD13_SEND_STATUS = 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD13 */
+ 8U | (uint32_t)HAL_MEMCARD_RESPONSE_R7 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD9 */
+ CMD9_SEND_CSD =
+ 9U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD10 */
+ CMD10_SEND_CID =
+ 10U | (uint32_t)HAL_MEMCARD_RESPONSE_R2 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD11 */
+ CMD11_READ_DAT_UNTIL_STOP =
+ 11U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12 */
+ CMD12_STOP_TRANSMISSION =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD12(R1b : write case) */
+ CMD12_STOP_TRANSMISSION_WRITE =
+ 12U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD13 */
+ CMD13_SEND_STATUS =
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
ACMD13_SD_STATUS =
- 13 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD14_BUSTEST_R = 14 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD14 */
- CMD15_GO_INACTIVE_STATE = 15 | HAL_MEMCARD_RESPONSE_NONE | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD15 */
+ 13U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD14 */
+ CMD14_BUSTEST_R =
+ 14U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD15 */
+ CMD15_GO_INACTIVE_STATE =
+ 15U | (uint32_t)HAL_MEMCARD_RESPONSE_NONE |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
/* class 2 */
- CMD16_SET_BLOCKLEN = 16 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD16 */
- CMD17_READ_SINGLE_BLOCK = 17 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD17 */
- CMD18_READ_MULTIPLE_BLOCK = 18 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD18 */
- CMD19_BUS_TEST_W = 19 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD19 */
+ /* CMD16 */
+ CMD16_SET_BLOCKLEN =
+ 16U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD17 */
+ CMD17_READ_SINGLE_BLOCK =
+ 17U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD18 */
+ CMD18_READ_MULTIPLE_BLOCK =
+ 18U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD19 */
+ CMD19_BUS_TEST_W =
+ 19U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
/* class 3 */
- CMD20_WRITE_DAT_UNTIL_STOP = 20 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD20 */
- CMD21 = 21, /* CMD21 */
- CMD22 = 22, /* CMD22 */
+ /* CMD20 */
+ CMD20_WRITE_DAT_UNTIL_STOP =
+ 20U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD21 */
+ CMD21 = 21U,
+ /* CMD22 */
+ CMD22 = 22U,
ACMD22_SEND_NUM_WR_BLOCKS =
- 22 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+ 22U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
/* class 4 */
- CMD23_SET_BLOCK_COUNT = 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD23 */
+ /* CMD23 */
+ CMD23_SET_BLOCK_COUNT =
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
ACMD23_SET_WR_BLK_ERASE_COUNT =
- 23 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD24_WRITE_BLOCK = 24 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD24 */
- CMD25_WRITE_MULTIPLE_BLOCK = 25 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD25 */
- CMD26_PROGRAM_CID = 26 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD26 */
- CMD27_PROGRAM_CSD = 27 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD27 */
+ 23U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ /* CMD24 */
+ CMD24_WRITE_BLOCK =
+ 24U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD25 */
+ CMD25_WRITE_MULTIPLE_BLOCK =
+ 25U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD26 */
+ CMD26_PROGRAM_CID =
+ 26U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD27 */
+ CMD27_PROGRAM_CSD =
+ 27U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
/* class 6 */
- CMD28_SET_WRITE_PROT = 28 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD28 */
- CMD29_CLR_WRITE_PROT = 29 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD29 */
- CMD30_SEND_WRITE_PROT = 30 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD30 */
- CMD30_SEND_WRITE_PROT_TYPE = 31 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD31 */
+ /* CMD28 */
+ CMD28_SET_WRITE_PROT =
+ 28U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD29 */
+ CMD29_CLR_WRITE_PROT =
+ 29U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD30 */
+ CMD30_SEND_WRITE_PROT =
+ 30U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD31 */
+ CMD30_SEND_WRITE_PROT_TYPE =
+ 31U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
/* class 5 */
- CMD32_ERASE_WR_BLK_START = 32 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD32 */
- CMD33_ERASE_WR_BLK_END = 33 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_NORMAL, /* CMD33 */
- CMD34 = 34, /* CMD34 */
- CMD35_ERASE_GROUP_START = 35 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD35 */
- CMD36_ERASE_GROUP_END = 36 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD36 */
- CMD37 = 37, /* CMD37 */
- CMD38_ERASE = 38 | HAL_MEMCARD_RESPONSE_R1b | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD38 */
+ /* CMD32 */
+ CMD32_ERASE_WR_BLK_START =
+ 32U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD33 */
+ CMD33_ERASE_WR_BLK_END =
+ 33U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD34 */
+ CMD34 = 34U,
+ /* CMD35 */
+ CMD35_ERASE_GROUP_START =
+ 35U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD36 */
+ CMD36_ERASE_GROUP_END =
+ 36U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD37 */
+ CMD37 = 37U,
+ /* CMD38 */
+ CMD38_ERASE =
+ 38U | (uint32_t)HAL_MEMCARD_RESPONSE_R1b |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
/* class 9 */
- CMD39_FASTIO = 39 | HAL_MEMCARD_RESPONSE_R4 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD39 */
- CMD40_GO_IRQSTATE = 40 | HAL_MEMCARD_RESPONSE_R5 | HAL_MEMCARD_COMMAND_TYPE_BCR | HAL_MEMCARD_COMMAND_CARD_TYPE_MMC | HAL_MEMCARD_COMMAND_NORMAL, /* CMD40 */
- CMD41 = 41, /* CMD41 */
+ /* CMD39 */
+ CMD39_FASTIO =
+ 39U | (uint32_t)HAL_MEMCARD_RESPONSE_R4 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD40 */
+ CMD40_GO_IRQSTATE =
+ 40U | (uint32_t)HAL_MEMCARD_RESPONSE_R5 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_MMC |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD41 */
+ CMD41 = 41,
ACMD41_SD_SEND_OP_COND =
- 41 | HAL_MEMCARD_RESPONSE_R3 | HAL_MEMCARD_COMMAND_TYPE_BCR |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
+ 41U | (uint32_t)HAL_MEMCARD_RESPONSE_R3 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_BCR |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
/* class 7 */
- CMD42_LOCK_UNLOCK = 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD42 */
+ /* CMD42 */
+ CMD42_LOCK_UNLOCK =
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
ACMD42_SET_CLR_CARD_DETECT =
- 42 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD43 = 43, /* CMD43 */
- CMD44 = 44, /* CMD44 */
- CMD45 = 45, /* CMD45 */
- CMD46 = 46, /* CMD46 */
- CMD47 = 47, /* CMD47 */
- CMD48 = 48, /* CMD48 */
- CMD49 = 49, /* CMD49 */
- CMD50 = 50, /* CMD50 */
- CMD51 = 51, /* CMD51 */
+ 42U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD43 = 43U, /* CMD43 */
+ CMD44 = 44U, /* CMD44 */
+ CMD45 = 45U, /* CMD45 */
+ CMD46 = 46U, /* CMD46 */
+ CMD47 = 47U, /* CMD47 */
+ CMD48 = 48U, /* CMD48 */
+ CMD49 = 49U, /* CMD49 */
+ CMD50 = 50U, /* CMD50 */
+ CMD51 = 51U, /* CMD51 */
ACMD51_SEND_SCR =
- 51 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
- HAL_MEMCARD_COMMAND_CARD_TYPE_SD | HAL_MEMCARD_COMMAND_APP,
- CMD52 = 52, /* CMD52 */
- CMD53 = 53, /* CMD53 */
- CMD54 = 54, /* CMD54 */
+ 51U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_READ |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_SD |
+ (uint32_t)HAL_MEMCARD_COMMAND_APP,
+ CMD52 = 52U, /* CMD52 */
+ CMD53 = 53U, /* CMD53 */
+ CMD54 = 54U, /* CMD54 */
/* class 8 */
- CMD55_APP_CMD = 55 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_AC | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD55 */
- CMD56_GEN_CMD = 56 | HAL_MEMCARD_RESPONSE_R1 | HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE | HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON | HAL_MEMCARD_COMMAND_NORMAL, /* CMD56 */
- CMD57 = 57, /* CMD57 */
- CMD58 = 58, /* CMD58 */
- CMD59 = 59, /* CMD59 */
- CMD60 = 60, /* CMD60 */
- CMD61 = 61, /* CMD61 */
- CMD62 = 62, /* CMD62 */
- CMD63 = 63 /* CMD63 */
+ /* CMD55 */
+ CMD55_APP_CMD =
+ 55U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_AC |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ /* CMD56 */
+ CMD56_GEN_CMD =
+ 56U | (uint32_t)HAL_MEMCARD_RESPONSE_R1 |
+ (uint32_t)HAL_MEMCARD_COMMAND_TYPE_ADTC_WRITE |
+ (uint32_t)HAL_MEMCARD_COMMAND_CARD_TYPE_COMMON |
+ (uint32_t)HAL_MEMCARD_COMMAND_NORMAL,
+ CMD57 = 57U, /* CMD57 */
+ CMD58 = 58U, /* CMD58 */
+ CMD59 = 59U, /* CMD59 */
+ CMD60 = 60U, /* CMD60 */
+ CMD61 = 61U, /* CMD61 */
+ CMD62 = 62U, /* CMD62 */
+ CMD63 = 63U /* CMD63 */
} HAL_MEMCARD_COMMAND;
-/** @brief Configuration structure from HAL layer.
+/*
+ * Configuration structure from HAL layer.
*
* If some field is not available it should be filled with 0xFF.
- * The API version is 32-bit unsigned integer telling the version of the API. The integer is divided to four sections which each can be treated as a 8-bit unsigned number:
- * Bits 31-24 make the most significant part of the version number. This number starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This number changes only, if the API itself changes so much that it is not compatible anymore with older releases.
- * Bits 23-16 API minor version number. For example API version 2.1 would be 0x0201xxxx.
- * Bits 15-8 are the number of the year when release is done. The 0 is year 2000, 1 is year 2001 and so on
- * Bits 7- are the week number when release is done. First full week of the year is 1
+ * The API version is 32-bit unsigned integer telling the version of the API.
+ * The integer is divided to four sections which each can be treated as a 8-bit
+ * unsigned number:
+ * Bits 31-24 make the most significant part of the version number. This number
+ * starts from 1 i.e. the second version of the API will be 0x02xxxxxx. This
+ * number changes only, if the API itself changes so much that it is not
+ * compatible anymore with older releases.
+ * Bits 23-16 API minor version number. For example API version 2.1 would be
+ * 0x0201xxxx.
+ * Bits 15-8 are the number of the year when release is done. The 0 is year
+ * 2000, 1 is year 2001 and so on
+ * Bits 7- are the week number when release is done. First full week of the
+ * year is 1
*
- * @note Example: let's assume that release 2.1 is done on week 10 year 2008 the version will get the value 0x0201080A
+ * Example: let's assume that release 2.1 is done on week 10 year 2008
+ * the version will get the value 0x0201080A
*/
typedef struct {
- /**
- * Version of the chipset API implementation
- *
- * bits [31:24] API specification major version number.<br>
- * bits [23:16] API specification minor version number.<br>
- * bits [15:8] API implemention year. (2000 = 0, 2001 = 1, ...)<br>
- * bits [7:0] API implemention week.<br>
- * Example: API specification version 4.0, implementation w46 2008 => 0x0400082E
- */
+ /*
+ * Version of the chipset API implementation
+ *
+ * bits [31:24] API specification major version number.<br>
+ * bits [23:16] API specification minor version number.<br>
+ * bits [15:8] API implementation year. (2000 = 0, 2001 = 1, ...)
+ * bits [7:0] API implementation week.
+ * Example: API spec version 4.0, implementation w46 2008 => 0x0400082E
+ */
uint32_t api_version;
- /** maximum block count which can be transferred at once */
+ /* maximum block count which can be transferred at once */
uint32_t max_block_count;
- /** maximum clock frequence in Hz supported by HW */
+ /* maximum clock frequence in Hz supported by HW */
uint32_t max_clock_freq;
- /** maximum data bus width supported by HW */
+ /* maximum data bus width supported by HW */
uint16_t max_data_width;
- /** Is high-speed mode supported by HW (yes=1, no=0) */
+ /* Is high-speed mode supported by HW (yes=1, no=0) */
uint8_t hs_mode_supported;
- /** Is memory card removable (yes=1, no=0) */
+ /* Is memory card removable (yes=1, no=0) */
uint8_t card_removable;
} HAL_MEMCARD_HW_CONF;
-/** @brief Configuration structure to HAL layer.
- */
+/* Configuration structure to HAL layer. */
typedef struct {
- /** how many times to try after fail, for instance sending command */
+ /* how many times to try after fail, for instance sending command */
uint32_t retries_after_fail;
} HAL_MEMCARD_INIT_CONF;
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
#endif /* EMMC_HAL_H */
-
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_init.c b/drivers/renesas/rcar/emmc/emmc_init.c
index b27e165..354aa3c 100644
--- a/drivers/renesas/rcar/emmc/emmc_init.c
+++ b/drivers/renesas/rcar/emmc/emmc_init.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -32,12 +32,12 @@
return EMMC_SUCCESS;
}
-static __inline void emmc_set_retry_count(uint32_t retry)
+static inline void emmc_set_retry_count(uint32_t retry)
{
mmc_drv_obj.retries_after_fail = retry;
}
-static __inline void emmc_set_data_timeout(uint32_t data_timeout)
+static inline void emmc_set_data_timeout(uint32_t data_timeout)
{
mmc_drv_obj.data_timeout = data_timeout;
}
@@ -73,7 +73,8 @@
EMMC_ERROR_CODE result;
uint32_t dataL;
- /* MMC power off
+ /*
+ * MMC power off
* the power supply of eMMC device is always turning on.
* RST_n : Hi --> Low level.
*/
@@ -115,27 +116,25 @@
SETR_32(HOST_MODE, 0x00000000U); /* SD_BUF access width = 64-bit */
SETR_32(SD_OPTION, 0x0000C0EEU); /* Bus width = 1bit, timeout=MAX */
- SETR_32(SD_CLK_CTRL, 0x00000000U); /* Automatic Control=Disable, Clock Output=Disable */
+ SETR_32(SD_CLK_CTRL, 0x00000000U); /* Disable Automatic Control & Clock Output */
return EMMC_SUCCESS;
}
static EMMC_ERROR_CODE emmc_reset_controller(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
/* initialize mmc driver */
emmc_drv_init();
/* initialize H/W */
- retult = emmc_dev_init();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_dev_init();
+ if (result == EMMC_SUCCESS) {
+ mmc_drv_obj.initialize = TRUE;
}
- mmc_drv_obj.initialize = TRUE;
-
- return retult;
+ return result;
}
@@ -152,14 +151,12 @@
EMMC_ERROR_CODE rcar_emmc_init(void)
{
- EMMC_ERROR_CODE retult;
+ EMMC_ERROR_CODE result;
- retult = emmc_reset_controller();
- if (EMMC_SUCCESS != retult) {
- return retult;
+ result = emmc_reset_controller();
+ if (result == EMMC_SUCCESS) {
+ emmc_driver_config();
}
- emmc_driver_config();
-
- return EMMC_SUCCESS;
+ return result;
}
diff --git a/drivers/renesas/rcar/emmc/emmc_interrupt.c b/drivers/renesas/rcar/emmc/emmc_interrupt.c
index 2557280..092fdfb 100644
--- a/drivers/renesas/rcar/emmc/emmc_interrupt.c
+++ b/drivers/renesas/rcar/emmc/emmc_interrupt.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -118,7 +118,7 @@
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BWE));
- /* DM_CM_INFO2: DMA-ch0 error occured */
+ /* DM_CM_INFO2: DMA-ch0 error occurred */
if ((BIT16 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
@@ -128,13 +128,13 @@
/* wait next interrupt */
mmc_drv_obj.state_machine_blocking = FALSE;
}
- /* DM_CM_INFO1: DMA-ch1 transfer complete or error occured */
+ /* DM_CM_INFO1: DMA-ch1 transfer complete or error occurred */
else if ((end_bit & mmc_drv_obj.dm_event1) != 0U) {
SETR_32(DM_CM_INFO1, 0x00000000U);
SETR_32(DM_CM_INFO2, 0x00000000U);
/* interrupt clear */
SETR_32(SD_INFO2, (GETR_32(SD_INFO2) & ~SD_INFO2_BRE));
- /* DM_CM_INFO2: DMA-ch1 error occured */
+ /* DM_CM_INFO2: DMA-ch1 error occurred */
if ((BIT17 & mmc_drv_obj.dm_event2) != 0) {
mmc_drv_obj.dma_error_flag = TRUE;
} else {
diff --git a/drivers/renesas/rcar/emmc/emmc_mount.c b/drivers/renesas/rcar/emmc/emmc_mount.c
index df8203e..e04afd4 100644
--- a/drivers/renesas/rcar/emmc/emmc_mount.c
+++ b/drivers/renesas/rcar/emmc/emmc_mount.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -8,10 +8,10 @@
#include <lib/mmio.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
#include "micro_delay.h"
#include "rcar_def.h"
@@ -53,7 +53,7 @@
int32_t retry;
uint32_t freq = MMC_400KHZ; /* 390KHz */
EMMC_ERROR_CODE result;
- uint32_t resultCalc;
+ uint32_t result_calc;
/* state check */
if ((mmc_drv_obj.initialize != TRUE)
@@ -161,9 +161,12 @@
mmc_drv_obj.selected = TRUE;
- /* card speed check */
- resultCalc = emmc_calc_tran_speed(&freq); /* Card spec is calculated from TRAN_SPEED(CSD). */
- if (resultCalc == 0) {
+ /*
+ * card speed check
+ * Card spec is calculated from TRAN_SPEED(CSD)
+ */
+ result_calc = emmc_calc_tran_speed(&freq);
+ if (result_calc == 0) {
emmc_write_error_info(EMMC_FUNCNO_CARD_INIT,
EMMC_ERR_ILLEGAL_CARD);
return EMMC_ERR_ILLEGAL_CARD;
@@ -201,7 +204,8 @@
HAL_MEMCARD_NOT_DMA);
result = emmc_exec_cmd(EMMC_R1_ERROR_MASK, mmc_drv_obj.response);
if (result != EMMC_SUCCESS) {
- /* CMD12 is not send.
+ /*
+ * CMD12 is not send.
* If BUS initialization is failed, user must be execute Bus initialization again.
* Bus initialization is start CMD0(soft reset command).
*/
@@ -217,7 +221,7 @@
static EMMC_ERROR_CODE emmc_high_speed(void)
{
- uint32_t freq; /**< High speed mode clock frequency */
+ uint32_t freq; /* High speed mode clock frequency */
EMMC_ERROR_CODE result;
uint8_t cardType;
@@ -236,8 +240,8 @@
else
freq = MMC_20MHZ;
- /* Hi-Speed-mode selction */
- if ((MMC_52MHZ == freq) || (MMC_26MHZ == freq)) {
+ /* Hi-Speed-mode selection */
+ if ((freq == MMC_52MHZ) || (freq == MMC_26MHZ)) {
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH, EMMC_SWITCH_HS_TIMING);
result =
@@ -322,7 +326,8 @@
return EMMC_ERR_STATE;
}
- mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2); /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ /* 2 = 8bit, 1 = 4bit, 0 =1bit */
+ mmc_drv_obj.bus_width = (HAL_MEMCARD_DATA_WIDTH) (width >> 2);
/* CMD6 */
emmc_make_nontrans_cmd(CMD6_SWITCH,
@@ -371,7 +376,6 @@
return EMMC_SUCCESS;
EXIT:
-
emmc_write_error_info(EMMC_FUNCNO_BUS_WIDTH, result);
ERROR("BL2: emmc bus_width error end\n");
return result;
@@ -489,82 +493,83 @@
static uint32_t emmc_calc_tran_speed(uint32_t *freq)
{
- const uint32_t unit[8] = { 10000, 100000, 1000000, 10000000,
- 0, 0, 0, 0 }; /**< frequency unit (1/10) */
- const uint32_t mult[16] = { 0, 10, 12, 13, 15, 20, 26, 30, 35, 40, 45,
- 52, 55, 60, 70, 80 };
-
- uint32_t maxFreq;
- uint32_t result;
+ const uint32_t unit[8] = { 10000U, 100000U, 1000000U, 10000000U,
+ 0U, 0U, 0U, 0U }; /* frequency unit (1/10) */
+ const uint32_t mult[16] = { 0U, 10U, 12U, 13U, 15U, 20U, 26U, 30U, 35U,
+ 40U, 45U, 52U, 55U, 60U, 70U, 80U };
uint32_t tran_speed = EMMC_CSD_TRAN_SPEED();
+ uint32_t max_freq;
+ uint32_t result;
- /* tran_speed = 0x32
+ /*
+ * tran_speed = 0x32
* unit[tran_speed&0x7] = uint[0x2] = 1000000
* mult[(tran_speed&0x78)>>3] = mult[0x30>>3] = mult[6] = 26
* 1000000 * 26 = 26000000 (26MHz)
*/
result = 1;
- maxFreq =
+ max_freq =
unit[tran_speed & EMMC_TRANSPEED_FREQ_UNIT_MASK] *
mult[(tran_speed & EMMC_TRANSPEED_MULT_MASK) >>
EMMC_TRANSPEED_MULT_SHIFT];
- if (maxFreq == 0) {
+ if (max_freq == 0) {
result = 0;
- } else if (MMC_FREQ_52MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_52MHZ) {
*freq = MMC_52MHZ;
- else if (MMC_FREQ_26MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_26MHZ) {
*freq = MMC_26MHZ;
- else if (MMC_FREQ_20MHZ <= maxFreq)
+ } else if (max_freq >= MMC_FREQ_20MHZ) {
*freq = MMC_20MHZ;
- else
+ } else {
*freq = MMC_400KHZ;
+ }
return result;
}
static uint32_t emmc_set_timeout_register_value(uint32_t freq)
{
- uint32_t timeoutCnt; /* SD_OPTION - Timeout Counter */
+ uint32_t timeout_cnt; /* SD_OPTION - Timeout Counter */
switch (freq) {
case 1U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 2U:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
case 4U:
- timeoutCnt = 0xD0U;
+ timeout_cnt = 0xD0U;
break; /* SDCLK * 2^26 */
case 8U:
- timeoutCnt = 0xC0U;
+ timeout_cnt = 0xC0U;
break; /* SDCLK * 2^25 */
case 16U:
- timeoutCnt = 0xB0U;
+ timeout_cnt = 0xB0U;
break; /* SDCLK * 2^24 */
case 32U:
- timeoutCnt = 0xA0U;
+ timeout_cnt = 0xA0U;
break; /* SDCLK * 2^23 */
case 64U:
- timeoutCnt = 0x90U;
+ timeout_cnt = 0x90U;
break; /* SDCLK * 2^22 */
case 128U:
- timeoutCnt = 0x80U;
+ timeout_cnt = 0x80U;
break; /* SDCLK * 2^21 */
case 256U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
case 512U:
- timeoutCnt = 0x70U;
+ timeout_cnt = 0x70U;
break; /* SDCLK * 2^20 */
default:
- timeoutCnt = 0xE0U;
+ timeout_cnt = 0xE0U;
break; /* SDCLK * 2^27 */
}
- return timeoutCnt;
+ return timeout_cnt;
}
EMMC_ERROR_CODE emmc_set_ext_csd(uint32_t arg)
diff --git a/drivers/renesas/rcar/emmc/emmc_read.c b/drivers/renesas/rcar/emmc/emmc_read.c
index 390d0ca..96e73ca 100644
--- a/drivers/renesas/rcar/emmc/emmc_read.c
+++ b/drivers/renesas/rcar/emmc/emmc_read.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,15 +7,15 @@
#include <arch_helpers.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
-#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
-#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
+#define MIN_EMMC(a, b) (((a) < (b)) ? (a) : (b))
+#define EMMC_RW_SECTOR_COUNT_MAX 0x0000ffffU
-static EMMC_ERROR_CODE emmc_multiple_block_read (uint32_t *buff_address_virtual,
+static EMMC_ERROR_CODE emmc_multiple_block_read(uint32_t *buff_address_virtual,
uint32_t sector_number, uint32_t count,
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode)
{
@@ -39,7 +39,8 @@
}
SETR_32(SD_SECCNT, count);
SETR_32(SD_STOP, 0x00000100);
- SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE)); /* SD_BUF Read/Write DMA Transfer enable */
+ /* SD_BUF Read/Write DMA Transfer enable */
+ SETR_32(CC_EXT_MODE, (CC_EXT_MODE_CLEAR | CC_EXT_MODE_DMASDRW_ENABLE));
/* CMD18 */
emmc_make_trans_cmd(CMD18_READ_MULTIPLE_BLOCK, sector_number,
diff --git a/drivers/renesas/rcar/emmc/emmc_registers.h b/drivers/renesas/rcar/emmc/emmc_registers.h
index 55ff33d..ae689ca 100644
--- a/drivers/renesas/rcar/emmc/emmc_registers.h
+++ b/drivers/renesas/rcar/emmc/emmc_registers.h
@@ -1,22 +1,12 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/**
- * @file emmc_registers.h
- * @brief emmc boot driver is expecting this header file. HS-MMC module header file.
- *
- */
-
#ifndef EMMC_REGISTERS_H
#define EMMC_REGISTERS_H
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
-
/* MMC channel select */
#define MMC_CH0 (0U) /* SDHI2/MMC0 */
#define MMC_CH1 (1U) /* SDHI3/MMC1 */
@@ -27,73 +17,71 @@
#define USE_MMC_CH (MMC_CH0) /* R-Car H3/M3/M3N */
#endif /* RCAR_LSI == RCAR_E3 */
-#define BIT0 (0x00000001U)
-#define BIT1 (0x00000002U)
-#define BIT2 (0x00000004U)
-#define BIT3 (0x00000008U)
-#define BIT4 (0x00000010U)
-#define BIT5 (0x00000020U)
-#define BIT6 (0x00000040U)
-#define BIT7 (0x00000080U)
-#define BIT8 (0x00000100U)
-#define BIT9 (0x00000200U)
-#define BIT10 (0x00000400U)
-#define BIT11 (0x00000800U)
-#define BIT12 (0x00001000U)
-#define BIT13 (0x00002000U)
-#define BIT14 (0x00004000U)
-#define BIT15 (0x00008000U)
-#define BIT16 (0x00010000U)
-#define BIT17 (0x00020000U)
-#define BIT18 (0x00040000U)
-#define BIT19 (0x00080000U)
-#define BIT20 (0x00100000U)
-#define BIT21 (0x00200000U)
-#define BIT22 (0x00400000U)
-#define BIT23 (0x00800000U)
-#define BIT24 (0x01000000U)
-#define BIT25 (0x02000000U)
-#define BIT26 (0x04000000U)
-#define BIT27 (0x08000000U)
-#define BIT28 (0x10000000U)
-#define BIT29 (0x20000000U)
-#define BIT30 (0x40000000U)
-#define BIT31 (0x80000000U)
-
-/** @brief Clock Pulse Generator (CPG) registers
- */
-#define CPG_BASE (0xE6150000U)
-
-#define CPG_MSTPSR3 (CPG_BASE+0x0048U) /* Module stop status register 3 */
-
-#define CPG_SMSTPCR3 (CPG_BASE+0x013CU) /* System module stop control register 3 */
+#define BIT0 (0x00000001U)
+#define BIT1 (0x00000002U)
+#define BIT2 (0x00000004U)
+#define BIT3 (0x00000008U)
+#define BIT4 (0x00000010U)
+#define BIT5 (0x00000020U)
+#define BIT6 (0x00000040U)
+#define BIT7 (0x00000080U)
+#define BIT8 (0x00000100U)
+#define BIT9 (0x00000200U)
+#define BIT10 (0x00000400U)
+#define BIT11 (0x00000800U)
+#define BIT12 (0x00001000U)
+#define BIT13 (0x00002000U)
+#define BIT14 (0x00004000U)
+#define BIT15 (0x00008000U)
+#define BIT16 (0x00010000U)
+#define BIT17 (0x00020000U)
+#define BIT18 (0x00040000U)
+#define BIT19 (0x00080000U)
+#define BIT20 (0x00100000U)
+#define BIT21 (0x00200000U)
+#define BIT22 (0x00400000U)
+#define BIT23 (0x00800000U)
+#define BIT24 (0x01000000U)
+#define BIT25 (0x02000000U)
+#define BIT26 (0x04000000U)
+#define BIT27 (0x08000000U)
+#define BIT28 (0x10000000U)
+#define BIT29 (0x20000000U)
+#define BIT30 (0x40000000U)
+#define BIT31 (0x80000000U)
-#define CPG_SD2CKCR (CPG_BASE+0x0268U) /* SDHI2 clock frequency control register */
-#define CPG_SD3CKCR (CPG_BASE+0x026CU) /* SDHI3 clock frequency control register */
-
-#define CPG_CPGWPR (CPG_BASE+0x0900U) /* CPG Write Protect Register */
+/* Clock Pulse Generator (CPG) registers */
+#define CPG_BASE (0xE6150000U)
+/* Module stop status register 3 */
+#define CPG_MSTPSR3 (CPG_BASE + 0x0048U)
+/* System module stop control register 3 */
+#define CPG_SMSTPCR3 (CPG_BASE + 0x013CU)
+/* SDHI2 clock frequency control register */
+#define CPG_SD2CKCR (CPG_BASE + 0x0268U)
+/* SDHI3 clock frequency control register */
+#define CPG_SD3CKCR (CPG_BASE + 0x026CU)
+/* CPG Write Protect Register */
+#define CPG_CPGWPR (CPG_BASE + 0x0900U)
#if USE_MMC_CH == MMC_CH0
-#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
+#define CPG_SDxCKCR (CPG_SD2CKCR) /* SDHI2/MMC0 */
#else /* USE_MMC_CH == MMC_CH0 */
-#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
+#define CPG_SDxCKCR (CPG_SD3CKCR) /* SDHI3/MMC1 */
#endif /* USE_MMC_CH == MMC_CH0 */
-/** Boot Status register
- */
+/* Boot Status register */
#define MFISBTSTSR (0xE6260604U)
#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
-/** brief eMMC registers
- */
-#define MMC0_SD_BASE (0xEE140000U)
+/* eMMC registers */
+#define MMC0_SD_BASE (0xEE140000U)
#define MMC1_SD_BASE (0xEE160000U)
#if USE_MMC_CH == MMC_CH0
-#define MMC_SD_BASE (MMC0_SD_BASE)
+#define MMC_SD_BASE (MMC0_SD_BASE)
#else /* USE_MMC_CH == MMC_CH0 */
-#define MMC_SD_BASE (MMC1_SD_BASE)
+#define MMC_SD_BASE (MMC1_SD_BASE)
#endif /* USE_MMC_CH == MMC_CH0 */
#define SD_CMD (MMC_SD_BASE + 0x0000U)
@@ -136,125 +124,105 @@
#define DM_CM_INFO2_MASK (MMC_SD_BASE + 0x0858U)
#define DM_DTRAN_ADDR (MMC_SD_BASE + 0x0880U)
-/** @brief SD_INFO1 Registers
- */
-#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
-#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
-#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
-#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
-#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
-#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
-#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
-#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
-#define SD_INFO1_INFO2 0x00000004UL /* Access end */
-#define SD_INFO1_INFO0 0x00000001UL /* Response end */
+/* SD_INFO1 Registers */
+#define SD_INFO1_HPIRES 0x00010000UL /* Response Reception Completion */
+#define SD_INFO1_INFO10 0x00000400UL /* Indicates the SDDAT3 state */
+#define SD_INFO1_INFO9 0x00000200UL /* SDDAT3 Card Insertion */
+#define SD_INFO1_INFO8 0x00000100UL /* SDDAT3 Card Removal */
+#define SD_INFO1_INFO7 0x00000080UL /* Write Protect */
+#define SD_INFO1_INFO5 0x00000020UL /* Indicates the ISDCD state */
+#define SD_INFO1_INFO4 0x00000010UL /* ISDCD Card Insertion */
+#define SD_INFO1_INFO3 0x00000008UL /* ISDCD Card Removal */
+#define SD_INFO1_INFO2 0x00000004UL /* Access end */
+#define SD_INFO1_INFO0 0x00000001UL /* Response end */
-/** @brief SD_INFO2 Registers
- */
-#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
-#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
-#define SD_INFO2_SCLKDIVEN 0x00002000UL
-#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
-#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
-#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
-#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
-#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
-#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
-#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
-#define SD_INFO2_ERR2 0x00000004UL /* END Error */
-#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
-#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
-#define SD_INFO2_ALL_ERR 0x0000807FUL
-#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 The write value should always be 1. HWM_0003 */
+/* SD_INFO2 Registers */
+#define SD_INFO2_ILA 0x00008000UL /* Illegal Access Error */
+#define SD_INFO2_CBSY 0x00004000UL /* Command Type Register Busy */
+#define SD_INFO2_SCLKDIVEN 0x00002000UL
+#define SD_INFO2_BWE 0x00000200UL /* SD_BUF Write Enable */
+#define SD_INFO2_BRE 0x00000100UL /* SD_BUF Read Enable */
+#define SD_INFO2_DAT0 0x00000080UL /* SDDAT0 */
+#define SD_INFO2_ERR6 0x00000040UL /* Response Timeout */
+#define SD_INFO2_ERR5 0x00000020UL /* SD_BUF Illegal Read Access */
+#define SD_INFO2_ERR4 0x00000010UL /* SD_BUF Illegal Write Access */
+#define SD_INFO2_ERR3 0x00000008UL /* Data Timeout */
+#define SD_INFO2_ERR2 0x00000004UL /* END Error */
+#define SD_INFO2_ERR1 0x00000002UL /* CRC Error */
+#define SD_INFO2_ERR0 0x00000001UL /* CMD Error */
+#define SD_INFO2_ALL_ERR 0x0000807FUL
+#define SD_INFO2_CLEAR 0x00000800UL /* BIT11 write value should always be 1. HWM_0003 */
-/** @brief SOFT_RST
- */
-#define SOFT_RST_SDRST 0x00000001UL
+/* SOFT_RST */
+#define SOFT_RST_SDRST 0x00000001UL
-/** @brief SD_CLK_CTRL
- */
+/* SD_CLK_CTRL */
#define SD_CLK_CTRL_SDCLKOFFEN 0x00000200UL
-#define SD_CLK_CTRL_SCLKEN 0x00000100UL
-#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
-#define SD_CLOCK_ENABLE 0x00000100UL
-#define SD_CLOCK_DISABLE 0x00000000UL
-#define SD_CLK_WRITE_MASK 0x000003FFUL
-#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
+#define SD_CLK_CTRL_SCLKEN 0x00000100UL
+#define SD_CLK_CTRL_CLKDIV_MASK 0x000000FFUL
+#define SD_CLOCK_ENABLE 0x00000100UL
+#define SD_CLOCK_DISABLE 0x00000000UL
+#define SD_CLK_WRITE_MASK 0x000003FFUL
+#define SD_CLK_CLKDIV_CLEAR_MASK 0xFFFFFF0FUL
-/** @brief SD_OPTION
- */
+/* SD_OPTION */
#define SD_OPTION_TIMEOUT_CNT_MASK 0x000000F0UL
-/** @brief MMC Clock Frequency
+/*
+ * MMC Clock Frequency
* 200MHz * 1/x = output clock
*/
-#define MMC_CLK_OFF 0UL /* Clock output is disabled */
-#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
-#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
-#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz High speed mode 26Mhz */
-#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz High speed mode 52Mhz */
-#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
-#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
+#define MMC_CLK_OFF 0UL /* Clock output is disabled */
+#define MMC_400KHZ 512UL /* 200MHz * 1/512 = 390 KHz */
+#define MMC_20MHZ 16UL /* 200MHz * 1/16 = 12.5 MHz Normal speed mode */
+#define MMC_26MHZ 8UL /* 200MHz * 1/8 = 25 MHz HS mode 26Mhz */
+#define MMC_52MHZ 4UL /* 200MHz * 1/4 = 50 MHz HS mode 52Mhz */
+#define MMC_100MHZ 2UL /* 200MHz * 1/2 = 100 MHz */
+#define MMC_200MHZ 1UL /* 200MHz * 1/1 = 200 MHz */
#define MMC_FREQ_52MHZ 52000000UL
#define MMC_FREQ_26MHZ 26000000UL
#define MMC_FREQ_20MHZ 20000000UL
-/** @brief MMC Clock DIV
- */
-#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
-#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
-#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
-#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
-#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
-#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
-#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
-#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
-#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
-#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
-#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
-#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
+/* MMC Clock DIV */
+#define MMC_SD_CLK_START 0x00000100UL /* CLOCK On */
+#define MMC_SD_CLK_STOP (~0x00000100UL) /* CLOCK stop */
+#define MMC_SD_CLK_DIV1 0x000000FFUL /* 1/1 */
+#define MMC_SD_CLK_DIV2 0x00000000UL /* 1/2 */
+#define MMC_SD_CLK_DIV4 0x00000001UL /* 1/4 */
+#define MMC_SD_CLK_DIV8 0x00000002UL /* 1/8 */
+#define MMC_SD_CLK_DIV16 0x00000004UL /* 1/16 */
+#define MMC_SD_CLK_DIV32 0x00000008UL /* 1/32 */
+#define MMC_SD_CLK_DIV64 0x00000010UL /* 1/64 */
+#define MMC_SD_CLK_DIV128 0x00000020UL /* 1/128 */
+#define MMC_SD_CLK_DIV256 0x00000040UL /* 1/256 */
+#define MMC_SD_CLK_DIV512 0x00000080UL /* 1/512 */
-/** @brief DM_CM_DTRAN_MODE
- */
-#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
-#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
+/* DM_CM_DTRAN_MODE */
+#define DM_CM_DTRAN_MODE_CH0 0x00000000UL /* CH0(downstream) */
+#define DM_CM_DTRAN_MODE_CH1 0x00010000UL /* CH1(upstream) */
#define DM_CM_DTRAN_MODE_BIT_WIDTH 0x00000030UL
-/** @brief CC_EXT_MODE
- */
+/* CC_EXT_MODE */
#define CC_EXT_MODE_DMASDRW_ENABLE 0x00000002UL /* SD_BUF Read/Write DMA Transfer */
-#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
+#define CC_EXT_MODE_CLEAR 0x00001010UL /* BIT 12 & 4 always 1. */
-/** @brief DM_CM_INFO_MASK
- */
+/* DM_CM_INFO_MASK */
#define DM_CM_INFO_MASK_CLEAR 0xFFFCFFFEUL
#define DM_CM_INFO_CH0_ENABLE 0x00010001UL
#define DM_CM_INFO_CH1_ENABLE 0x00020001UL
-/** @brief DM_DTRAN_ADDR
- */
+/* DM_DTRAN_ADDR */
#define DM_DTRAN_ADDR_WRITE_MASK 0xFFFFFFF8UL
-/** @brief DM_CM_DTRAN_CTRL
- */
+/* DM_CM_DTRAN_CTRL */
#define DM_CM_DTRAN_CTRL_START 0x00000001UL
-/** @brief SYSC Registers
- */
+/* SYSC Registers */
#if USE_MMC_CH == MMC_CH0
#define CPG_MSTP_MMC (BIT12) /* SDHI2/MMC0 */
#else /* USE_MMC_CH == MMC_CH0 */
#define CPG_MSTP_MMC (BIT11) /* SDHI3/MMC1 */
#endif /* USE_MMC_CH == MMC_CH0 */
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
-
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
-
-/* ********************************* CODE ********************************** */
-
#endif /* EMMC_REGISTERS_H */
-/* ******************************** END ************************************ */
diff --git a/drivers/renesas/rcar/emmc/emmc_std.h b/drivers/renesas/rcar/emmc/emmc_std.h
index 99cb6b9..087c6e9 100644
--- a/drivers/renesas/rcar/emmc/emmc_std.h
+++ b/drivers/renesas/rcar/emmc/emmc_std.h
@@ -1,23 +1,14 @@
/*
- * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
-/**
- * @file emmc_std.h
- * @brief eMMC boot is expecting this header file
- *
- */
-
#ifndef EMMC_STD_H
#define EMMC_STD_H
#include "emmc_hal.h"
-/* ************************ HEADER (INCLUDE) SECTION *********************** */
-
-/* ***************** MACROS, CONSTANTS, COMPILATION FLAGS ****************** */
#ifndef FALSE
#define FALSE 0U
#endif
@@ -25,29 +16,24 @@
#define TRUE 1U
#endif
-/** @brief 64bit registers
- **/
-#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
-#define GETR_64(r) (*(volatile uint64_t *)(r))
+/* 64bit registers */
+#define SETR_64(r, v) (*(volatile uint64_t *)(r) = (v))
+#define GETR_64(r) (*(volatile uint64_t *)(r))
-/** @brief 32bit registers
- **/
-#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
-#define GETR_32(r) (*(volatile uint32_t *)(r))
+/* 32bit registers */
+#define SETR_32(r, v) (*(volatile uint32_t *)(r) = (v))
+#define GETR_32(r) (*(volatile uint32_t *)(r))
-/** @brief 16bit registers
- */
-#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
-#define GETR_16(r) (*(volatile uint16_t *)(r))
+/* 16bit registers */
+#define SETR_16(r, v) (*(volatile uint16_t *)(r) = (v))
+#define GETR_16(r) (*(volatile uint16_t *)(r))
-/** @brief 8bit registers
- */
-#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
-#define GETR_8(r) (*(volatile uint8_t *)(r))
+/* 8bit registers */
+#define SETR_8(r, v) (*(volatile uint8_t *)(r) = (v))
+#define GETR_8(r) (*(volatile uint8_t *)(r))
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
+/* CSD register Macros */
+#define EMMC_GET_CID(x, y) (emmc_bit_field(mmc_drv_obj.cid_data, (x), (y)))
#define EMMC_CID_MID() (EMMC_GET_CID(127, 120))
#define EMMC_CID_CBX() (EMMC_GET_CID(113, 112))
@@ -59,267 +45,269 @@
#define EMMC_CID_MDT() (EMMC_GET_CID(15, 8))
#define EMMC_CID_CRC() (EMMC_GET_CID(7, 1))
-/** @brief CSD register Macros
- */
-#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
+/* CSD register Macros */
+#define EMMC_GET_CSD(x, y) (emmc_bit_field(mmc_drv_obj.csd_data, (x), (y)))
-#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
-#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
-#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
-#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
-#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
-#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
-#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
-#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
-#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
-#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
-#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
-#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
-#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
-#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
-#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
-#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
-#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
-#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
-#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
-#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
-#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
-#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
-#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
-#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
-#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
-#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
-#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
-#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
-#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
-#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
-#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
-#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
-#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
+#define EMMC_CSD_CSD_STRUCTURE() (EMMC_GET_CSD(127, 126))
+#define EMMC_CSD_SPEC_VARS() (EMMC_GET_CSD(125, 122))
+#define EMMC_CSD_TAAC() (EMMC_GET_CSD(119, 112))
+#define EMMC_CSD_NSAC() (EMMC_GET_CSD(111, 104))
+#define EMMC_CSD_TRAN_SPEED() (EMMC_GET_CSD(103, 96))
+#define EMMC_CSD_CCC() (EMMC_GET_CSD(95, 84))
+#define EMMC_CSD_READ_BL_LEN() (EMMC_GET_CSD(83, 80))
+#define EMMC_CSD_READ_BL_PARTIAL() (EMMC_GET_CSD(79, 79))
+#define EMMC_CSD_WRITE_BLK_MISALIGN() (EMMC_GET_CSD(78, 78))
+#define EMMC_CSD_READ_BLK_MISALIGN() (EMMC_GET_CSD(77, 77))
+#define EMMC_CSD_DSR_IMP() (EMMC_GET_CSD(76, 76))
+#define EMMC_CSD_C_SIZE() (EMMC_GET_CSD(73, 62))
+#define EMMC_CSD_VDD_R_CURR_MIN() (EMMC_GET_CSD(61, 59))
+#define EMMC_CSD_VDD_R_CURR_MAX() (EMMC_GET_CSD(58, 56))
+#define EMMC_CSD_VDD_W_CURR_MIN() (EMMC_GET_CSD(55, 53))
+#define EMMC_CSD_VDD_W_CURR_MAX() (EMMC_GET_CSD(52, 50))
+#define EMMC_CSD_C_SIZE_MULT() (EMMC_GET_CSD(49, 47))
+#define EMMC_CSD_ERASE_GRP_SIZE() (EMMC_GET_CSD(46, 42))
+#define EMMC_CSD_ERASE_GRP_MULT() (EMMC_GET_CSD(41, 37))
+#define EMMC_CSD_WP_GRP_SIZE() (EMMC_GET_CSD(36, 32))
+#define EMMC_CSD_WP_GRP_ENABLE() (EMMC_GET_CSD(31, 31))
+#define EMMC_CSD_DEFALT_ECC() (EMMC_GET_CSD(30, 29))
+#define EMMC_CSD_R2W_FACTOR() (EMMC_GET_CSD(28, 26))
+#define EMMC_CSD_WRITE_BL_LEN() (EMMC_GET_CSD(25, 22))
+#define EMMC_CSD_WRITE_BL_PARTIAL() (EMMC_GET_CSD(21, 21))
+#define EMMC_CSD_CONTENT_PROT_APP() (EMMC_GET_CSD(16, 16))
+#define EMMC_CSD_FILE_FORMAT_GRP() (EMMC_GET_CSD(15, 15))
+#define EMMC_CSD_COPY() (EMMC_GET_CSD(14, 14))
+#define EMMC_CSD_PERM_WRITE_PROTECT() (EMMC_GET_CSD(13, 13))
+#define EMMC_CSD_TMP_WRITE_PROTECT() (EMMC_GET_CSD(12, 12))
+#define EMMC_CSD_FILE_FORMAT() (EMMC_GET_CSD(11, 10))
+#define EMMC_CSD_ECC() (EMMC_GET_CSD(9, 8))
+#define EMMC_CSD_CRC() (EMMC_GET_CSD(7, 1))
-/** @brief for sector access
- */
-#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
-#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
-#define EMMC_SECTOR_SIZE 512
-#define EMMC_BLOCK_LENGTH 512
-#define EMMC_BLOCK_LENGTH_DW 128
-#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
+/* sector access */
+#define EMMC_4B_BOUNDARY_CHECK_MASK 0x00000003
+#define EMMC_SECTOR_SIZE_SHIFT 9U /* 512 = 2^9 */
+#define EMMC_SECTOR_SIZE 512
+#define EMMC_BLOCK_LENGTH 512
+#define EMMC_BLOCK_LENGTH_DW 128
+#define EMMC_BUF_SIZE_SHIFT 3U /* 8byte = 2^3 */
-/** @brief eMMC specification clock
- */
-#define EMMC_CLOCK_SPEC_400K 400000UL /**< initialize clock 400KHz */
-#define EMMC_CLOCK_SPEC_20M 20000000UL /**< normal speed 20MHz */
-#define EMMC_CLOCK_SPEC_26M 26000000UL /**< high speed 26MHz */
-#define EMMC_CLOCK_SPEC_52M 52000000UL /**< high speed 52MHz */
-#define EMMC_CLOCK_SPEC_100M 100000000UL /**< high speed 100MHz */
+/* eMMC specification clock */
+#define EMMC_CLOCK_SPEC_400K 400000UL /* initialize clock 400KHz */
+#define EMMC_CLOCK_SPEC_20M 20000000UL /* normal speed 20MHz */
+#define EMMC_CLOCK_SPEC_26M 26000000UL /* high speed 26MHz */
+#define EMMC_CLOCK_SPEC_52M 52000000UL /* high speed 52MHz */
+#define EMMC_CLOCK_SPEC_100M 100000000UL /* high speed 100MHz */
-/** @brief EMMC driver error code. (extended HAL_MEMCARD_RETURN)
- */
+/* EMMC driver error code. (extended HAL_MEMCARD_RETURN) */
typedef enum {
- EMMC_ERR = 0, /**< unknown error */
- EMMC_SUCCESS, /**< OK */
- EMMC_ERR_FROM_DMAC, /**< DMAC allocation error */
- EMMC_ERR_FROM_DMAC_TRANSFER, /**< DMAC transfer error */
- EMMC_ERR_CARD_STATUS_BIT, /**< card status error. Non-masked error bit was set in the card status */
- EMMC_ERR_CMD_TIMEOUT, /**< command timeout error */
- EMMC_ERR_DATA_TIMEOUT, /**< data timeout error */
- EMMC_ERR_CMD_CRC, /**< command CRC error */
- EMMC_ERR_DATA_CRC, /**< data CRC error */
- EMMC_ERR_PARAM, /**< parameter error */
- EMMC_ERR_RESPONSE, /**< response error */
- EMMC_ERR_RESPONSE_BUSY, /**< response busy error */
- EMMC_ERR_TRANSFER, /**< data transfer error */
- EMMC_ERR_READ_SECTOR, /**< read sector error */
- EMMC_ERR_WRITE_SECTOR, /**< write sector error */
- EMMC_ERR_STATE, /**< state error */
- EMMC_ERR_TIMEOUT, /**< timeout error */
- EMMC_ERR_ILLEGAL_CARD, /**< illegal card */
- EMMC_ERR_CARD_BUSY, /**< Busy state */
- EMMC_ERR_CARD_STATE, /**< card state error */
- EMMC_ERR_SET_TRACE, /**< trace information error */
- EMMC_ERR_FROM_TIMER, /**< Timer error */
- EMMC_ERR_FORCE_TERMINATE, /**< Force terminate */
- EMMC_ERR_CARD_POWER, /**< card power fail */
- EMMC_ERR_ERASE_SECTOR, /**< erase sector error */
- EMMC_ERR_INFO2 /**< exec cmd error info2 */
+ EMMC_ERR = 0, /* unknown error */
+ EMMC_SUCCESS, /* OK */
+ EMMC_ERR_FROM_DMAC, /* DMAC allocation error */
+ EMMC_ERR_FROM_DMAC_TRANSFER, /* DMAC transfer error */
+ EMMC_ERR_CARD_STATUS_BIT, /* card status error */
+ EMMC_ERR_CMD_TIMEOUT, /* command timeout error */
+ EMMC_ERR_DATA_TIMEOUT, /* data timeout error */
+ EMMC_ERR_CMD_CRC, /* command CRC error */
+ EMMC_ERR_DATA_CRC, /* data CRC error */
+ EMMC_ERR_PARAM, /* parameter error */
+ EMMC_ERR_RESPONSE, /* response error */
+ EMMC_ERR_RESPONSE_BUSY, /* response busy error */
+ EMMC_ERR_TRANSFER, /* data transfer error */
+ EMMC_ERR_READ_SECTOR, /* read sector error */
+ EMMC_ERR_WRITE_SECTOR, /* write sector error */
+ EMMC_ERR_STATE, /* state error */
+ EMMC_ERR_TIMEOUT, /* timeout error */
+ EMMC_ERR_ILLEGAL_CARD, /* illegal card */
+ EMMC_ERR_CARD_BUSY, /* Busy state */
+ EMMC_ERR_CARD_STATE, /* card state error */
+ EMMC_ERR_SET_TRACE, /* trace information error */
+ EMMC_ERR_FROM_TIMER, /* Timer error */
+ EMMC_ERR_FORCE_TERMINATE, /* Force terminate */
+ EMMC_ERR_CARD_POWER, /* card power fail */
+ EMMC_ERR_ERASE_SECTOR, /* erase sector error */
+ EMMC_ERR_INFO2 /* exec cmd error info2 */
} EMMC_ERROR_CODE;
-/** @brief Function number */
-#define EMMC_FUNCNO_NONE 0U
-#define EMMC_FUNCNO_DRIVER_INIT 1U
-#define EMMC_FUNCNO_CARD_POWER_ON 2U
-#define EMMC_FUNCNO_MOUNT 3U
-#define EMMC_FUNCNO_CARD_INIT 4U
-#define EMMC_FUNCNO_HIGH_SPEED 5U
-#define EMMC_FUNCNO_BUS_WIDTH 6U
-#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
-#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
-#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
-#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
-#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
-#define EMMC_FUNCNO_SET_CLOCK 12U
-#define EMMC_FUNCNO_EXEC_CMD 13U
-#define EMMC_FUNCNO_READ_SECTOR 14U
-#define EMMC_FUNCNO_WRITE_SECTOR 15U
-#define EMMC_FUNCNO_ERASE_SECTOR 16U
-#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
-/** @brief Response
+/* Function number */
+#define EMMC_FUNCNO_NONE 0U
+#define EMMC_FUNCNO_DRIVER_INIT 1U
+#define EMMC_FUNCNO_CARD_POWER_ON 2U
+#define EMMC_FUNCNO_MOUNT 3U
+#define EMMC_FUNCNO_CARD_INIT 4U
+#define EMMC_FUNCNO_HIGH_SPEED 5U
+#define EMMC_FUNCNO_BUS_WIDTH 6U
+#define EMMC_FUNCNO_MULTI_BOOT_SELECT_PARTITION 7U
+#define EMMC_FUNCNO_MULTI_BOOT_READ_SECTOR 8U
+#define EMMC_FUNCNO_TRANS_DATA_READ_SECTOR 9U
+#define EMMC_FUNCNO_UBOOT_IMAGE_SELECT_PARTITION 10U
+#define EMMC_FUNCNO_UBOOT_IMAGE_READ_SECTOR 11U
+#define EMMC_FUNCNO_SET_CLOCK 12U
+#define EMMC_FUNCNO_EXEC_CMD 13U
+#define EMMC_FUNCNO_READ_SECTOR 14U
+#define EMMC_FUNCNO_WRITE_SECTOR 15U
+#define EMMC_FUNCNO_ERASE_SECTOR 16U
+#define EMMC_FUNCNO_GET_PERTITION_ACCESS 17U
+/*
+ * Response
+ * R1
+ * Type 'E' bit and bit14(must be 0). ignore bit22
*/
-/** R1 */
-#define EMMC_R1_ERROR_MASK 0xFDBFE080U /* Type 'E' bit and bit14(must be 0). ignore bit22 */
-#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U) /* Ignore bit23 (Not check CRC error) */
-#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
-#define EMMC_R1_READY 0x00000100U /* bit8 */
-#define EMMC_R1_STATE_SHIFT 9
+#define EMMC_R1_ERROR_MASK 0xFDBFE080U
+/* Ignore bit23 (Not check CRC error) */
+#define EMMC_R1_ERROR_MASK_WITHOUT_CRC (0xFD3FE080U)
+#define EMMC_R1_STATE_MASK 0x00001E00U /* [12:9] */
+#define EMMC_R1_READY 0x00000100U /* bit8 */
+#define EMMC_R1_STATE_SHIFT 9
-/** R4 */
-#define EMMC_R4_RCA_MASK 0xFFFF0000UL
-#define EMMC_R4_STATUS 0x00008000UL
+/* R4 */
+#define EMMC_R4_RCA_MASK 0xFFFF0000UL
+#define EMMC_R4_STATUS 0x00008000UL
-/** CSD */
-#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
-#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
-#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
-#define EMMC_TRANSPEED_MULT_SHIFT 3
+/* CSD */
+#define EMMC_TRANSPEED_FREQ_UNIT_MASK 0x07 /* bit[2:0] */
+#define EMMC_TRANSPEED_FREQ_UNIT_SHIFT 0
+#define EMMC_TRANSPEED_MULT_MASK 0x78 /* bit[6:3] */
+#define EMMC_TRANSPEED_MULT_SHIFT 3
-/** OCR */
-#define EMMC_HOST_OCR_VALUE 0x40FF8080
-#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
-#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
-#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
-#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
+/* OCR */
+#define EMMC_HOST_OCR_VALUE 0x40FF8080
+#define EMMC_OCR_STATUS_BIT 0x80000000L /* Card power up status bit */
+#define EMMC_OCR_ACCESS_MODE_MASK 0x60000000L /* bit[30:29] */
+#define EMMC_OCR_ACCESS_MODE_SECT 0x40000000L
+#define EMMC_OCR_ACCESS_MODE_BYTE 0x00000000L
-/** EXT_CSD */
-#define EMMC_EXT_CSD_S_CMD_SET 504
-#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
-#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
-#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
-#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
-#define EMMC_EXT_CSD_TRIM_MULT 232
-#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
-#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
-#define EMMC_EXT_CSD_BOOT_INFO 228
-#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
-#define EMMC_EXT_CSD_ACC_SIZE 225
-#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
-#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
-#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
-#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
-#define EMMC_EXT_CSD_S_C_VCC 220
-#define EMMC_EXT_CSD_S_C_VCCQ 219
-#define EMMC_EXT_CSD_S_A_TIMEOUT 217
-#define EMMC_EXT_CSD_SEC_COUNT 215
-#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
-#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
-#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
-#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
-#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
-#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
-#define EMMC_EXT_CSD_PWR_CL_26_360 203
-#define EMMC_EXT_CSD_PWR_CL_52_360 202
-#define EMMC_EXT_CSD_PWR_CL_26_195 201
-#define EMMC_EXT_CSD_PWR_CL_52_195 200
-#define EMMC_EXT_CSD_CARD_TYPE 196
-#define EMMC_EXT_CSD_CSD_STRUCTURE 194
-#define EMMC_EXT_CSD_EXT_CSD_REV 192
-#define EMMC_EXT_CSD_CMD_SET 191
-#define EMMC_EXT_CSD_CMD_SET_REV 189
-#define EMMC_EXT_CSD_POWER_CLASS 187
-#define EMMC_EXT_CSD_HS_TIMING 185
-#define EMMC_EXT_CSD_BUS_WIDTH 183
-#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
-#define EMMC_EXT_CSD_PARTITION_CONFIG 179
-#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
-#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
-#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
-#define EMMC_EXT_CSD_BOOT_WP 173
-#define EMMC_EXT_CSD_USER_WP 171
-#define EMMC_EXT_CSD_FW_CONFIG 169
-#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
-#define EMMC_EXT_CSD_RST_n_FUNCTION 162
-#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
-#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
-#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
-#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
-#define EMMC_EXT_CSD_GP_SIZE_MULT 154
-#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
-#define EMMC_EXT_CSD_ENH_START_ADDR 139
-#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
+/* EXT_CSD */
+#define EMMC_EXT_CSD_S_CMD_SET 504
+#define EMMC_EXT_CSD_INI_TIMEOUT_AP 241
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_360 239
+#define EMMC_EXT_CSD_PWR_CL_DDR_52_195 238
+#define EMMC_EXT_CSD_MIN_PERF_DDR_W_8_52 235
+#define EMMC_EXT_CSD_MIN_PERF_DDR_R_8_52 234
+#define EMMC_EXT_CSD_TRIM_MULT 232
+#define EMMC_EXT_CSD_SEC_FEATURE_SUPPORT 231
+#define EMMC_EXT_CSD_SEC_ERASE_MULT 229
+#define EMMC_EXT_CSD_BOOT_INFO 228
+#define EMMC_EXT_CSD_BOOT_SIZE_MULTI 226
+#define EMMC_EXT_CSD_ACC_SIZE 225
+#define EMMC_EXT_CSD_HC_ERASE_GRP_SIZE 224
+#define EMMC_EXT_CSD_ERASE_TIMEOUT_MULT 223
+#define EMMC_EXT_CSD_PEL_WR_SEC_C 222
+#define EMMC_EXT_CSD_HC_WP_GRP_SIZE 221
+#define EMMC_EXT_CSD_S_C_VCC 220
+#define EMMC_EXT_CSD_S_C_VCCQ 219
+#define EMMC_EXT_CSD_S_A_TIMEOUT 217
+#define EMMC_EXT_CSD_SEC_COUNT 215
+#define EMMC_EXT_CSD_MIN_PERF_W_8_52 210
+#define EMMC_EXT_CSD_MIN_PERF_R_8_52 209
+#define EMMC_EXT_CSD_MIN_PERF_W_8_26_4_52 208
+#define EMMC_EXT_CSD_MIN_PERF_R_8_26_4_52 207
+#define EMMC_EXT_CSD_MIN_PERF_W_4_26 206
+#define EMMC_EXT_CSD_MIN_PERF_R_4_26 205
+#define EMMC_EXT_CSD_PWR_CL_26_360 203
+#define EMMC_EXT_CSD_PWR_CL_52_360 202
+#define EMMC_EXT_CSD_PWR_CL_26_195 201
+#define EMMC_EXT_CSD_PWR_CL_52_195 200
+#define EMMC_EXT_CSD_CARD_TYPE 196
+#define EMMC_EXT_CSD_CSD_STRUCTURE 194
+#define EMMC_EXT_CSD_EXT_CSD_REV 192
+#define EMMC_EXT_CSD_CMD_SET 191
+#define EMMC_EXT_CSD_CMD_SET_REV 189
+#define EMMC_EXT_CSD_POWER_CLASS 187
+#define EMMC_EXT_CSD_HS_TIMING 185
+#define EMMC_EXT_CSD_BUS_WIDTH 183
+#define EMMC_EXT_CSD_ERASED_MEM_CONT 181
+#define EMMC_EXT_CSD_PARTITION_CONFIG 179
+#define EMMC_EXT_CSD_BOOT_CONFIG_PROT 178
+#define EMMC_EXT_CSD_BOOT_BUS_WIDTH 177
+#define EMMC_EXT_CSD_ERASE_GROUP_DEF 175
+#define EMMC_EXT_CSD_BOOT_WP 173
+#define EMMC_EXT_CSD_USER_WP 171
+#define EMMC_EXT_CSD_FW_CONFIG 169
+#define EMMC_EXT_CSD_RPMB_SIZE_MULT 168
+#define EMMC_EXT_CSD_RST_n_FUNCTION 162
+#define EMMC_EXT_CSD_PARTITIONING_SUPPORT 160
+#define EMMC_EXT_CSD_MAX_ENH_SIZE_MULT 159
+#define EMMC_EXT_CSD_PARTITIONS_ATTRIBUTE 156
+#define EMMC_EXT_CSD_PARTITION_SETTING_COMPLETED 155
+#define EMMC_EXT_CSD_GP_SIZE_MULT 154
+#define EMMC_EXT_CSD_ENH_SIZE_MULT 142
+#define EMMC_EXT_CSD_ENH_START_ADDR 139
+#define EMMC_EXT_CSD_SEC_BAD_BLK_MGMNT 134
-#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
-#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
-#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
+#define EMMC_EXT_CSD_CARD_TYPE_26MHZ 0x01
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ 0x02
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_12V 0x04
+#define EMMC_EXT_CSD_CARD_TYPE_DDR_52MHZ_18V 0x08
+#define EMMC_EXT_CSD_CARD_TYPE_52MHZ_MASK 0x0e
-/** SWITCH (CMD6) argument */
-#define EXTCSD_ACCESS_BYTE (BIT25|BIT24)
-#define EXTCSD_SET_BITS BIT24
+/* SWITCH (CMD6) argument */
+#define EXTCSD_ACCESS_BYTE (BIT25 | BIT24)
+#define EXTCSD_SET_BITS BIT24
-#define HS_TIMING_ADD (185<<16) /* H'b9 */
-#define HS_TIMING_1 (1<<8)
-#define HS_TIMING_HS200 (2<<8)
-#define HS_TIMING_HS400 (3<<8)
+#define HS_TIMING_ADD (185 << 16) /* H'b9 */
+#define HS_TIMING_1 (1 << 8)
+#define HS_TIMING_HS200 (2 << 8)
+#define HS_TIMING_HS400 (3 << 8)
-#define BUS_WIDTH_ADD (183<<16) /* H'b7 */
-#define BUS_WIDTH_1 (0<<8)
-#define BUS_WIDTH_4 (1<<8)
-#define BUS_WIDTH_8 (2<<8)
-#define BUS_WIDTH_4DDR (5<<8)
-#define BUS_WIDTH_8DDR (6<<8)
+#define BUS_WIDTH_ADD (183 << 16) /* H'b7 */
+#define BUS_WIDTH_1 (0 << 8)
+#define BUS_WIDTH_4 (1 << 8)
+#define BUS_WIDTH_8 (2 << 8)
+#define BUS_WIDTH_4DDR (5 << 8)
+#define BUS_WIDTH_8DDR (6 << 8)
-#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD|HS_TIMING_1) /**< H'03b90100 */
-#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE|HS_TIMING_ADD) /**< H'03b90000 */
+#define EMMC_SWITCH_HS_TIMING (EXTCSD_ACCESS_BYTE | HS_TIMING_ADD |\
+ HS_TIMING_1) /* H'03b90100 */
+#define EMMC_SWITCH_HS_TIMING_OFF (EXTCSD_ACCESS_BYTE |\
+ HS_TIMING_ADD) /* H'03b90000 */
-#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_1) /**< H'03b70000 */
-#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4) /**< H'03b70100 */
-#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8) /**< H'03b70200 */
-#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_4DDR) /**< H'03b70500 */
-#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE|BUS_WIDTH_ADD|BUS_WIDTH_8DDR) /**< H'03b70600 */
-#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL /**< Partition config = 0x00 */
+#define EMMC_SWITCH_BUS_WIDTH_1 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_1) /* H'03b70000 */
+#define EMMC_SWITCH_BUS_WIDTH_4 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4) /* H'03b70100 */
+#define EMMC_SWITCH_BUS_WIDTH_8 (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8) /* H'03b70200 */
+#define EMMC_SWITCH_BUS_WIDTH_4DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_4DDR) /* H'03b70500 */
+#define EMMC_SWITCH_BUS_WIDTH_8DDR (EXTCSD_ACCESS_BYTE | BUS_WIDTH_ADD |\
+ BUS_WIDTH_8DDR) /* H'03b70600 */
+/* Partition config = 0x00 */
+#define EMMC_SWITCH_PARTITION_CONFIG 0x03B30000UL
-#define TIMING_HIGH_SPEED 1UL
+#define TIMING_HIGH_SPEED 1UL
#define EMMC_BOOT_PARTITION_EN_MASK 0x38U
#define EMMC_BOOT_PARTITION_EN_SHIFT 3U
-/** Bus width */
-#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
-#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
-#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
+/* Bus width */
+#define EMMC_BUSWIDTH_1BIT CE_CMD_SET_DATW_1BIT
+#define EMMC_BUSWIDTH_4BIT CE_CMD_SET_DATW_4BIT
+#define EMMC_BUSWIDTH_8BIT CE_CMD_SET_DATW_8BIT
-/** for st_mmc_base */
-#define EMMC_MAX_RESPONSE_LENGTH 17
-#define EMMC_MAX_CID_LENGTH 16
-#define EMMC_MAX_CSD_LENGTH 16
-#define EMMC_MAX_EXT_CSD_LENGTH 512U
-#define EMMC_RES_REG_ALIGNED 4U
-#define EMMC_BUF_REG_ALIGNED 8U
-
-/** @brief for TAAC mask
- */
-#define TAAC_TIME_UNIT_MASK (0x07)
-#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
+/* for st_mmc_base */
+#define EMMC_MAX_RESPONSE_LENGTH 17
+#define EMMC_MAX_CID_LENGTH 16
+#define EMMC_MAX_CSD_LENGTH 16
+#define EMMC_MAX_EXT_CSD_LENGTH 512U
+#define EMMC_RES_REG_ALIGNED 4U
+#define EMMC_BUF_REG_ALIGNED 8U
-/* ********************** STRUCTURES, TYPE DEFINITIONS ********************* */
+/* TAAC mask */
+#define TAAC_TIME_UNIT_MASK (0x07)
+#define TAAC_MULTIPLIER_FACTOR_MASK (0x0F)
-/** @brief Partition id
- */
+/* Partition id */
typedef enum {
- PARTITION_ID_USER = 0x0, /**< User Area */
- PARTITION_ID_BOOT_1 = 0x1, /**< boot partition 1 */
- PARTITION_ID_BOOT_2 = 0x2, /**< boot partition 2 */
- PARTITION_ID_RPMB = 0x3, /**< Replay Protected Memory Block */
- PARTITION_ID_GP_1 = 0x4, /**< General Purpose partition 1 */
- PARTITION_ID_GP_2 = 0x5, /**< General Purpose partition 2 */
- PARTITION_ID_GP_3 = 0x6, /**< General Purpose partition 3 */
- PARTITION_ID_GP_4 = 0x7, /**< General Purpose partition 4 */
- PARTITION_ID_MASK = 0x7 /**< [2:0] */
+ PARTITION_ID_USER = 0x0, /* User Area */
+ PARTITION_ID_BOOT_1 = 0x1, /* boot partition 1 */
+ PARTITION_ID_BOOT_2 = 0x2, /* boot partition 2 */
+ PARTITION_ID_RPMB = 0x3, /* Replay Protected Memory Block */
+ PARTITION_ID_GP_1 = 0x4, /* General Purpose partition 1 */
+ PARTITION_ID_GP_2 = 0x5, /* General Purpose partition 2 */
+ PARTITION_ID_GP_3 = 0x6, /* General Purpose partition 3 */
+ PARTITION_ID_GP_4 = 0x7, /* General Purpose partition 4 */
+ PARTITION_ID_MASK = 0x7 /* [2:0] */
} EMMC_PARTITION_ID;
-/** @brief card state in R1 response [12:9]
- */
+/* card state in R1 response [12:9] */
typedef enum {
EMMC_R1_STATE_IDLE = 0,
EMMC_R1_STATE_READY,
@@ -349,126 +337,139 @@
ESTATE_END
} EMMC_INT_STATE;
-/** @brief eMMC boot driver error information
- */
+/* eMMC boot driver error information */
typedef struct {
- uint16_t num; /**< error no */
- uint16_t code; /**< error code */
- volatile uint32_t info1; /**< SD_INFO1 register value. (hardware dependence) */
- volatile uint32_t info2; /**< SD_INFO2 register value. (hardware dependence) */
- volatile uint32_t status1;/**< SD_ERR_STS1 register value. (hardware dependence) */
- volatile uint32_t status2;/**< SD_ERR_STS2 register value. (hardware dependence) */
- volatile uint32_t dm_info1;/**< DM_CM_INFO1 register value. (hardware dependence) */
- volatile uint32_t dm_info2;/**< DM_CM_INFO2 register value. (hardware dependence) */
+ uint16_t num; /* error no */
+ uint16_t code; /* error code */
+
+ volatile uint32_t info1; /* SD_INFO1. (hw dependent) */
+ volatile uint32_t info2; /* SD_INFO2. (hw dependent) */
+ volatile uint32_t status1; /* SD_ERR_STS1. (hw dependent) */
+ volatile uint32_t status2; /* SD_ERR_STS2. (hw dependent) */
+ volatile uint32_t dm_info1; /* DM_CM_INFO1. (hw dependent) */
+ volatile uint32_t dm_info2; /* DM_CM_INFO2. (hw dependent) */
} st_error_info;
-/** @brief Command information
- */
+/* Command information */
typedef struct {
- HAL_MEMCARD_COMMAND cmd; /**< Command information */
- uint32_t arg; /**< argument */
- HAL_MEMCARD_OPERATION dir; /**< direction */
- uint32_t hw; /**< H/W dependence. SD_CMD register value. */
+ HAL_MEMCARD_COMMAND cmd; /* Command information */
+ uint32_t arg; /* argument */
+ HAL_MEMCARD_OPERATION dir; /* direction */
+ uint32_t hw; /* SD_CMD register value. */
} st_command_info;
-/** @brief MMC driver base
- */
+/* MMC driver base */
typedef struct {
- st_error_info error_info; /**< error information */
- st_command_info cmd_info; /**< command information */
+ st_error_info error_info; /* error information */
+ st_command_info cmd_info; /* command information */
/* for data transfer */
- uint32_t *buff_address_virtual; /**< Dest or Src buff */
- uint32_t *buff_address_physical; /**< Dest or Src buff */
- HAL_MEMCARD_DATA_WIDTH bus_width;
- /**< bus width */
- uint32_t trans_size; /**< transfer size for this command */
- uint32_t remain_size; /**< remain size for this command */
- uint32_t response_length; /**< response length for this command */
- uint32_t sector_size; /**< sector_size */
+ uint32_t *buff_address_virtual; /* Dest or Src buff */
+ uint32_t *buff_address_physical; /* Dest or Src buff */
+ HAL_MEMCARD_DATA_WIDTH bus_width; /* bus width */
+
+ uint32_t trans_size; /* transfer size for this command */
+ uint32_t remain_size; /* remain size for this command */
+ uint32_t response_length; /* response length for this command */
+ uint32_t sector_size; /* sector_size */
/* clock */
- uint32_t base_clock; /**< MMC host controller clock */
- uint32_t max_freq; /**< Max frequency (Card Spec)[Hz]. It changes dynamically by CSD and EXT_CSD. */
- uint32_t request_freq; /**< request freq [Hz] (400K, 26MHz, 52MHz, etc) */
- uint32_t current_freq; /**< current MMC clock[Hz] (the closest frequency supported by HW) */
+ uint32_t base_clock; /* MMC host controller clock */
+ /*
+ * Max freq (Card Spec)[Hz]. It changes dynamically by CSD and
+ * EXT_CSD.
+ */
+ uint32_t max_freq;
+ /* request freq [Hz] (400K, 26MHz, 52MHz, etc) */
+ uint32_t request_freq;
+ /* current MMC clock[Hz] (the closest frequency supported by HW) */
+ uint32_t current_freq;
/* state flag */
+ /* presence status of the memory card */
HAL_MEMCARD_PRESENCE_STATUS card_present;
- /**< presence status of the memory card */
- uint32_t card_power_enable; /**< True : Power ON */
- uint32_t clock_enable; /**< True : Clock ON */
- uint32_t initialize; /**< True : initialize complete. */
- uint32_t access_mode; /**< True : sector access, FALSE : byte access */
- uint32_t mount; /**< True : mount complete. */
- uint32_t selected; /**< True : selected card. */
+
+ uint32_t card_power_enable;
+ uint32_t clock_enable;
+ /* True : initialize complete. */
+ uint32_t initialize;
+ /* True : sector access, FALSE : byte access */
+ uint32_t access_mode;
+ /* True : mount complete. */
+ uint32_t mount;
+ /* True : selected card. */
+ uint32_t selected;
+ /* 0: DMA, 1:PIO */
HAL_MEMCARD_DATA_TRANSFER_MODE transfer_mode;
- /**< 0: DMA, 1:PIO */
- uint32_t image_num; /**< loaded ISSW image No. ISSW have copy image. */
- EMMC_R1_STATE current_state; /**< card state */
- volatile uint32_t during_cmd_processing; /**< True : during command processing */
- volatile uint32_t during_transfer; /**< True : during transfer */
- volatile uint32_t during_dma_transfer; /**< True : during transfer (DMA)*/
- volatile uint32_t dma_error_flag; /**< True : occurred DMAC error */
- volatile uint32_t force_terminate; /**< force terminate flag */
- volatile uint32_t state_machine_blocking; /**< state machine blocking flag : True or False */
+
+ /* loaded ISSW image No. ISSW have copy image. */
+ uint32_t image_num;
+ /* card state */
+ EMMC_R1_STATE current_state;
+ /* True : during command processing */
+ volatile uint32_t during_cmd_processing;
+ /* True : during transfer */
+ volatile uint32_t during_transfer;
+ /* True : during transfer (DMA) */
+ volatile uint32_t during_dma_transfer;
+ /* True : occurred DMAC error */
+ volatile uint32_t dma_error_flag;
+ /* force terminate flag */
+ volatile uint32_t force_terminate;
+ /* state machine blocking flag : True or False */
+ volatile uint32_t state_machine_blocking;
+ /* True : get partition access processing */
volatile uint32_t get_partition_access_flag;
- /**< True : get partition access processing */
- EMMC_PARTITION_ID boot_partition_en; /**< Boot partition */
- EMMC_PARTITION_ID partition_access; /**< Current access partition */
+ EMMC_PARTITION_ID boot_partition_en; /* Boot partition */
+ EMMC_PARTITION_ID partition_access; /* Current access partition */
/* timeout */
- uint32_t hs_timing; /**< high speed */
+ uint32_t hs_timing;
- /* timeout */
- uint32_t data_timeout; /**< read and write data timeout.*/
+ /* read and write data timeout */
+ uint32_t data_timeout;
/* retry */
- uint32_t retries_after_fail; /**< how many times to try after fail, for instance sending command */
+ uint32_t retries_after_fail;
/* interrupt */
- volatile uint32_t int_event1; /**< interrupt SD_INFO1 Event */
- volatile uint32_t int_event2; /**< interrupt SD_INFO2 Event */
- volatile uint32_t dm_event1; /**< interrupt DM_CM_INFO1 Event */
- volatile uint32_t dm_event2; /**< interrupt DM_CM_INFO2 Event */
+ volatile uint32_t int_event1; /* interrupt SD_INFO1 Event */
+ volatile uint32_t int_event2; /* interrupt SD_INFO2 Event */
+ volatile uint32_t dm_event1; /* interrupt DM_CM_INFO1 Event */
+ volatile uint32_t dm_event2; /* interrupt DM_CM_INFO2 Event */
/* response */
- uint32_t *response; /**< pointer to buffer for executing command. */
- uint32_t r1_card_status; /**< R1 response data */
- uint32_t r3_ocr; /**< R3 response data */
- uint32_t r4_resp; /**< R4 response data */
- uint32_t r5_resp; /**< R5 response data */
+ uint32_t *response; /* buffer ptr for executing command. */
+ uint32_t r1_card_status; /* R1 response data */
+ uint32_t r3_ocr; /* R3 response data */
+ uint32_t r4_resp; /* R4 response data */
+ uint32_t r5_resp; /* R5 response data */
+ /* True : clock mode is low. (MMC clock = Max26MHz) */
uint32_t low_clock_mode_enable;
- /**< True : clock mode is low. (MMC clock = Max26MHz) */
+
uint32_t reserved2;
uint32_t reserved3;
uint32_t reserved4;
/* CSD registers (4byte align) */
- uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /**< CSD */
+ uint8_t csd_data[EMMC_MAX_CSD_LENGTH] /* CSD */
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
/* CID registers (4byte align) */
- uint8_t cid_data[EMMC_MAX_CID_LENGTH] /**< CID */
+ uint8_t cid_data[EMMC_MAX_CID_LENGTH] /* CID */
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
/* EXT CSD registers (8byte align) */
- uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /**< EXT_CSD */
+ uint8_t ext_csd_data[EMMC_MAX_EXT_CSD_LENGTH] /* EXT_CSD */
__attribute__ ((aligned(EMMC_BUF_REG_ALIGNED)));
/* Response registers (4byte align) */
- uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /**< other response */
+ uint8_t response_data[EMMC_MAX_RESPONSE_LENGTH] /* other response */
__attribute__ ((aligned(EMMC_RES_REG_ALIGNED)));
} st_mmc_base;
typedef int (*func) (void);
-/* ********************** DECLARATION OF EXTERNAL DATA ********************* */
-
-/* ************************** FUNCTION PROTOTYPES ************************** */
uint32_t emmc_get_csd_time(void);
#define MMC_DEBUG
-/* ********************************* CODE ********************************** */
-
-/* ******************************** END ************************************ */
#endif /* EMMC_STD_H */
diff --git a/drivers/renesas/rcar/emmc/emmc_utility.c b/drivers/renesas/rcar/emmc/emmc_utility.c
index 39d9ede..2e88abc 100644
--- a/drivers/renesas/rcar/emmc/emmc_utility.c
+++ b/drivers/renesas/rcar/emmc/emmc_utility.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
+ * Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,10 +7,10 @@
#include <common/debug.h>
#include "emmc_config.h"
+#include "emmc_def.h"
#include "emmc_hal.h"
-#include "emmc_std.h"
#include "emmc_registers.h"
-#include "emmc_def.h"
+#include "emmc_std.h"
static const uint32_t cmd_reg_hw[EMMC_CMD_MAX + 1] = {
0x00000000, /* CMD0 */
@@ -97,8 +97,8 @@
value =
(uint32_t) ((data[index_top] << 24) |
(data[index_top + 1] << 16) |
- (data[index_top + 2] << 8) | data[index_top +
- 3]);
+ (data[index_top + 2] << 8) |
+ data[index_top + 3]);
}
value = ((value >> (bottom & 0x07)) & ((1 << (top - bottom + 1)) - 1));
@@ -150,7 +150,7 @@
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R1b:
- mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
+ mmc_drv_obj.cmd_info.hw |= BIT10; /* bit10 = R1 busy bit */
mmc_drv_obj.response = &mmc_drv_obj.r1_card_status;
break;
case HAL_MEMCARD_RESPONSE_R2:
diff --git a/plat/marvell/armada/a3k/common/a3700_common.mk b/plat/marvell/armada/a3k/common/a3700_common.mk
index e2022fa..712b162 100644
--- a/plat/marvell/armada/a3k/common/a3700_common.mk
+++ b/plat/marvell/armada/a3k/common/a3700_common.mk
@@ -1,5 +1,5 @@
#
-# Copyright (C) 2018 Marvell International Ltd.
+# Copyright (C) 2018-2020 Marvell International Ltd.
#
# SPDX-License-Identifier: BSD-3-Clause
# https://spdx.org/licenses
@@ -64,6 +64,10 @@
$(PLAT_COMMON_BASE)/a3700_sip_svc.c \
$(MARVELL_DRV)
+ifeq ($(CM3_SYSTEM_RESET),1)
+BL31_SOURCES += $(PLAT_COMMON_BASE)/cm3_system_reset.c
+endif
+
ifdef WTP
DOIMAGEPATH := $(WTP)
diff --git a/plat/marvell/armada/a3k/common/cm3_system_reset.c b/plat/marvell/armada/a3k/common/cm3_system_reset.c
new file mode 100644
index 0000000..548ff51
--- /dev/null
+++ b/plat/marvell/armada/a3k/common/cm3_system_reset.c
@@ -0,0 +1,62 @@
+/*
+ * Copyright (C) 2020 Marek Behun, CZ.NIC
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ * https://spdx.org/licenses
+ */
+
+#include <stdbool.h>
+
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <lib/mmio.h>
+
+#include <mvebu_def.h>
+
+/* Cortex-M3 Secure Processor Mailbox Registers */
+#define MVEBU_RWTM_PARAM0_REG (MVEBU_RWTM_REG_BASE)
+#define MVEBU_RWTM_CMD_REG (MVEBU_RWTM_REG_BASE + 0x40)
+#define MVEBU_RWTM_HOST_INT_RESET_REG (MVEBU_RWTM_REG_BASE + 0xC8)
+#define MVEBU_RWTM_HOST_INT_MASK_REG (MVEBU_RWTM_REG_BASE + 0xCC)
+#define MVEBU_RWTM_HOST_INT_SP_COMPLETE BIT(0)
+
+#define MVEBU_RWTM_REBOOT_CMD 0x0009
+#define MVEBU_RWTM_REBOOT_MAGIC 0xDEADBEEF
+
+static inline bool rwtm_completed(void)
+{
+ return (mmio_read_32(MVEBU_RWTM_HOST_INT_RESET_REG) &
+ MVEBU_RWTM_HOST_INT_SP_COMPLETE) != 0;
+}
+
+static bool rwtm_wait(int ms)
+{
+ while (ms && !rwtm_completed()) {
+ mdelay(1);
+ --ms;
+ }
+
+ return rwtm_completed();
+}
+
+void cm3_system_reset(void)
+{
+ int tries = 5;
+
+ for (; tries > 0; --tries) {
+ mmio_clrbits_32(MVEBU_RWTM_HOST_INT_RESET_REG,
+ MVEBU_RWTM_HOST_INT_SP_COMPLETE);
+
+ mmio_write_32(MVEBU_RWTM_PARAM0_REG, MVEBU_RWTM_REBOOT_MAGIC);
+ mmio_write_32(MVEBU_RWTM_CMD_REG, MVEBU_RWTM_REBOOT_CMD);
+
+ if (rwtm_wait(10)) {
+ break;
+ }
+
+ mdelay(100);
+ }
+
+ /* If we reach here, the command is not implemented. */
+ ERROR("System reset command not implemented in WTMI firmware!\n");
+}
diff --git a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
index c7f40ad..d23f5be 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_plat_def.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -119,4 +119,10 @@
*/
#define MVEBU_COMPHY_REG_BASE (MVEBU_REGS_BASE + 0x18300)
+/*****************************************************************************
+ * Cortex-M3 Secure Processor Mailbox constants
+ *****************************************************************************
+ */
+#define MVEBU_RWTM_REG_BASE (MVEBU_REGS_BASE + 0xB0000)
+
#endif /* A3700_PLAT_DEF_H */
diff --git a/plat/marvell/armada/a3k/common/include/a3700_pm.h b/plat/marvell/armada/a3k/common/include/a3700_pm.h
index cc6cf43..44dbb9f 100644
--- a/plat/marvell/armada/a3k/common/include/a3700_pm.h
+++ b/plat/marvell/armada/a3k/common/include/a3700_pm.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2016 Marvell International Ltd.
+ * Copyright (C) 2016-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -48,4 +48,6 @@
struct pm_wake_up_src_config *mv_wake_up_src_config_get(void);
+void cm3_system_reset(void);
+
#endif /* A3700_PM_H */
diff --git a/plat/marvell/armada/a3k/common/plat_pm.c b/plat/marvell/armada/a3k/common/plat_pm.c
index f8ce6fe..2bae37e 100644
--- a/plat/marvell/armada/a3k/common/plat_pm.c
+++ b/plat/marvell/armada/a3k/common/plat_pm.c
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2018 Marvell International Ltd.
+ * Copyright (C) 2018-2020 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
@@ -763,6 +763,11 @@
panic();
}
+#pragma weak cm3_system_reset
+void cm3_system_reset(void)
+{
+}
+
/*****************************************************************************
* A3700 handlers to reset the system
*****************************************************************************
@@ -780,6 +785,9 @@
2 * sizeof(uint64_t));
#endif
+ /* Use Cortex-M3 secure coprocessor for system reset */
+ cm3_system_reset();
+
/* Trigger the warm reset */
mmio_write_32(MVEBU_WARM_RESET_REG, MVEBU_WARM_RESET_MAGIC);
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 9da904e..f165fb0 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -282,17 +282,29 @@
{
unsigned int shift;
enum pm_ret_status ret;
+ unsigned int val, mask;
- if (nid == NODE_SD_0)
+ if (nid == NODE_SD_0) {
shift = 0;
- else if (nid == NODE_SD_1)
+ mask = ZYNQMP_SD0_DLL_RST_MASK;
+ } else if (nid == NODE_SD_1) {
shift = ZYNQMP_SD_TAP_OFFSET;
- else
+ mask = ZYNQMP_SD1_DLL_RST_MASK;
+ } else {
return PM_RET_ERROR_ARGS;
+ }
- ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
- if (ret != PM_RET_SUCCESS)
+ ret = pm_mmio_read(ZYNQMP_SD_DLL_CTRL, &val);
+ if (ret != PM_RET_SUCCESS) {
return ret;
+ }
+
+ if ((val & mask) == 0) {
+ ret = pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_ASSERT);
+ if (ret != PM_RET_SUCCESS) {
+ return ret;
+ }
+ }
if (type == PM_TAPDELAY_INPUT) {
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
@@ -300,9 +312,15 @@
(ZYNQMP_SD_ITAPCHGWIN << shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
- ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
- (ZYNQMP_SD_ITAPDLYENA_MASK << shift),
- (ZYNQMP_SD_ITAPDLYENA << shift));
+ if (value == 0)
+ ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+ (ZYNQMP_SD_ITAPDLYENA_MASK <<
+ shift), 0);
+ else
+ ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
+ (ZYNQMP_SD_ITAPDLYENA_MASK <<
+ shift), (ZYNQMP_SD_ITAPDLYENA <<
+ shift));
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_ITAP_DLY,
@@ -314,8 +332,7 @@
(ZYNQMP_SD_ITAPCHGWIN_MASK << shift), 0);
} else if (type == PM_TAPDELAY_OUTPUT) {
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
- (ZYNQMP_SD_OTAPDLYENA_MASK << shift),
- (ZYNQMP_SD_OTAPDLYENA << shift));
+ (ZYNQMP_SD_OTAPDLYENA_MASK << shift), 0);
if (ret != PM_RET_SUCCESS)
goto reset_release;
ret = pm_mmio_write(ZYNQMP_SD_OTAP_DLY,
@@ -326,7 +343,10 @@
}
reset_release:
- pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
+ if ((val & mask) == 0) {
+ (void)pm_ioctl_sd_dll_reset(nid, PM_DLL_RESET_RELEASE);
+ }
+
return ret;
}