diff --git a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
index 0567aa9..15314e7 100644
--- a/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
+++ b/plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
@@ -30,6 +30,7 @@
  * provide typical implementations that will be overridden by a SoC.
  */
 #pragma weak plat_memctrl_tzdram_setup
+
 void plat_memctrl_tzdram_setup(uint64_t phys_base, uint64_t size_in_bytes)
 {
 	; /* do nothing */
@@ -155,25 +156,9 @@
 void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes)
 {
 	/*
-	 * Setup the Memory controller to allow only secure accesses to
-	 * the TZDRAM carveout
-	 */
-	INFO("Configuring TrustZone DRAM Memory Carveout\n");
-
-	tegra_mc_write_32(MC_SECURITY_CFG0_0, (uint32_t)phys_base);
-	tegra_mc_write_32(MC_SECURITY_CFG3_0, (uint32_t)(phys_base >> 32));
-	tegra_mc_write_32(MC_SECURITY_CFG1_0, size_in_bytes >> 20);
-
-	/*
 	 * Perform platform specific steps.
 	 */
 	plat_memctrl_tzdram_setup(phys_base, size_in_bytes);
-
-	/*
-	 * MCE propagates the security configuration values across the
-	 * CCPLEX.
-	 */
-	mce_update_gsc_tzdram();
 }
 
 /*