Merge "fix(intel): correct macro naming" into integration
diff --git a/include/lib/cpus/aarch64/cortex_a720_ae.h b/include/lib/cpus/aarch64/cortex_a720_ae.h
new file mode 100644
index 0000000..c88b1f9
--- /dev/null
+++ b/include/lib/cpus/aarch64/cortex_a720_ae.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef CORTEX_A720_AE_H
+#define CORTEX_A720_AE_H
+
+#define CORTEX_A720_AE_MIDR U(0x410FD890)
+
+/*******************************************************************************
+ * CPU Extended Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A720_AE_CPUECTLR_EL1 S3_0_C15_C1_4
+
+/*******************************************************************************
+ * CPU Power Control register specific definitions
+ ******************************************************************************/
+#define CORTEX_A720_AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
+#define CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
+
+#endif /* CORTEX_A720_AE_H */
diff --git a/lib/cpus/aarch64/cortex_a720_ae.S b/lib/cpus/aarch64/cortex_a720_ae.S
new file mode 100644
index 0000000..42d49c3
--- /dev/null
+++ b/lib/cpus/aarch64/cortex_a720_ae.S
@@ -0,0 +1,65 @@
+/*
+ * Copyright (c) 2024, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <asm_macros.S>
+#include <common/bl_common.h>
+#include <cortex_a720_ae.h>
+#include <cpu_macros.S>
+#include <plat_macros.S>
+
+/* Hardware handled coherency */
+#if HW_ASSISTED_COHERENCY == 0
+#error "Cortex-A720AE must be compiled with HW_ASSISTED_COHERENCY enabled"
+#endif
+
+/* 64-bit only core */
+#if CTX_INCLUDE_AARCH32_REGS == 1
+#error "Cortex-A720AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
+#endif
+
+cpu_reset_func_start cortex_a720_ae
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_a720_ae
+
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_a720_ae_core_pwr_dwn
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_A720_AE_CPUPWRCTLR_EL1, CORTEX_A720_AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
+ isb
+ ret
+endfunc cortex_a720_ae_core_pwr_dwn
+
+ /* ---------------------------------------------
+ * This function provides Cortex-A720AE specific
+ * register information for crash reporting.
+ * It needs to return with x6 pointing to
+ * a list of register names in ascii and
+ * x8 - x15 having values of registers to be
+ * reported.
+ * ---------------------------------------------
+ */
+.section .rodata.cortex_a720_ae_regs, "aS"
+cortex_a720_ae_regs: /* The ascii list of register names to be reported */
+ .asciz "cpuectlr_el1", ""
+
+func cortex_a720_ae_cpu_reg_dump
+ adr x6, cortex_a720_ae_regs
+ mrs x8, CORTEX_A720_AE_CPUECTLR_EL1
+ ret
+endfunc cortex_a720_ae_cpu_reg_dump
+
+declare_cpu_ops cortex_a720_ae, CORTEX_A720_AE_MIDR, \
+ cortex_a720_ae_reset_func, \
+ cortex_a720_ae_core_pwr_dwn
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 1ec1943..7cb3982 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -196,6 +196,7 @@
lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/cortex_a715.S \
lib/cpus/aarch64/cortex_a720.S \
+ lib/cpus/aarch64/cortex_a720_ae.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_n2.S \
diff --git a/plat/arm/board/tc/include/platform_def.h b/plat/arm/board/tc/include/platform_def.h
index 613f508..86fce0e 100644
--- a/plat/arm/board/tc/include/platform_def.h
+++ b/plat/arm/board/tc/include/platform_def.h
@@ -222,8 +222,11 @@
#define TC_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)
-
+#if TARGET_PLATFORM == 2
+#define PLAT_ARM_NSTIMER_FRAME_ID U(0)
+#else
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
+#endif
#define PLAT_ARM_TRUSTED_ROM_BASE 0x0
diff --git a/plat/intel/soc/agilex/include/socfpga_plat_def.h b/plat/intel/soc/agilex/include/socfpga_plat_def.h
index 72ffbe2..94fed3a 100644
--- a/plat/intel/soc/agilex/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex/include/socfpga_plat_def.h
@@ -24,6 +24,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
diff --git a/plat/intel/soc/agilex5/include/agilex5_pinmux.h b/plat/intel/soc/agilex5/include/agilex5_pinmux.h
index 8a8e8c7..78d19af 100644
--- a/plat/intel/soc/agilex5/include/agilex5_pinmux.h
+++ b/plat/intel/soc/agilex5/include/agilex5_pinmux.h
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2019-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -7,19 +8,13 @@
#ifndef AGX5_PINMUX_H
#define AGX5_PINMUX_H
-/* PINMUX REGISTER ADDRESS */
-#define AGX5_PINMUX_PIN0SEL 0x10d13000
-#define AGX5_PINMUX_IO0CTRL 0x10d13130
-#define AGX5_PINMUX_EMAC0_USEFPGA 0x10d13300
-#define AGX5_PINMUX_IO0_DELAY 0x10d13400
-#define AGX5_PERIPHERAL 0x10d14044
-
#include "socfpga_handoff.h"
-/* PINMUX DEFINE */
-#define PINMUX_HANDOFF_ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-#define PINMUX_HANDOFF_CONFIG_ADDR 0xbeec
-#define PINMUX_HANDOFF_CONFIG_VAL 0x7e000
+/* PINMUX REGISTER ADDRESS */
+#define AGX5_PINMUX_PIN0SEL 0x10D13000
+#define AGX5_PINMUX_IO0CTRL 0x10D13130
+#define AGX5_PINMUX_EMAC0_USEFPGA 0x10D13300
+#define AGX5_PINMUX_IO0_DELAY 0x10D13400
/* Macros */
#define SOCFPGA_PINMUX_SEL_NAND (0x03)
@@ -142,6 +137,9 @@
#define SOCFPGA_PINMUX_JTAG_USEFPGA (0x50)
#define SOCFPGA_PINMUX_SDMMC_USEFPGA (0x54)
+#define SOCFPGA_PINUMX_USEFPGA(_reg) (AGX5_PINMUX_EMAC0_USEFPGA \
+ + SOCFPGA_PINMUX_##_reg)
+
#define SOCFPGA_PINMUX_IO0DELAY (0x00)
#define SOCFPGA_PINMUX_IO1DELAY (0x04)
#define SOCFPGA_PINMUX_IO2DELAY (0x08)
@@ -198,5 +196,4 @@
+ (SOCFPGA_PINMUX_##_reg))
void config_pinmux(handoff *handoff);
-void config_peripheral(handoff *handoff);
#endif
diff --git a/plat/intel/soc/agilex5/include/socfpga_plat_def.h b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
index ab6e2bc..3a0aea1 100644
--- a/plat/intel/soc/agilex5/include/socfpga_plat_def.h
+++ b/plat/intel/soc/agilex5/include/socfpga_plat_def.h
@@ -28,6 +28,7 @@
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF2_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_L2_RESET_REQ 0xB007C0DE
+#define PLAT_HANDOFF_OFFSET 0x0007F000
#define PLAT_TIMER_BASE_ADDR 0x10D01000
/* System Counter */
diff --git a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
index 7c4eb57..317b4d8 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_pinmux.c
@@ -187,14 +187,54 @@
0x0000011c, 0x00000000
};
-void config_fpgaintf_mod(void)
+static void config_fpgaintf_mod(void)
{
- mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), 1<<8);
+ uint32_t fpgaintf_en_val;
+
+ /*
+ * System manager FPGA interface enable2 register, disable individual
+ * interfaces between the FPGA and HPS.
+ */
+ fpgaintf_en_val = 0U;
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(NAND_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(4);
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SDMMC_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(8);
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM0_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(16);
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(SPIM1_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(24);
+ mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_2), fpgaintf_en_val);
+
+ /*
+ * System manager FPGA interface enable3 register, disable individual
+ * interfaces between the FPGA and HPS.
+ */
+ fpgaintf_en_val = 0U;
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC0_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(0);
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC1_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(8);
+ if ((mmio_read_32(SOCFPGA_PINUMX_USEFPGA(EMAC2_USEFPGA)) & 0x01) != 0)
+ fpgaintf_en_val |= BIT(16);
+ mmio_write_32(SOCFPGA_SYSMGR(FPGAINTF_EN_3), fpgaintf_en_val);
}
void config_pinmux(handoff *hoff_ptr)
{
- unsigned int i;
+ uint32_t i;
+
+ /* Configure the pin selection */
+ for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_sel_array); i += 2) {
+ mmio_write_32(AGX5_PINMUX_PIN0SEL + hoff_ptr->pinmux_sel_array[i],
+ hoff_ptr->pinmux_sel_array[i+1]);
+ }
+
+ /* Configure the pin control */
+ for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_io_array); i += 2) {
+ mmio_write_32(AGX5_PINMUX_IO0CTRL + hoff_ptr->pinmux_io_array[i],
+ hoff_ptr->pinmux_io_array[i+1]);
+ }
/*
* Configure the FPGA use.
@@ -207,24 +247,12 @@
hoff_ptr->pinmux_fpga_array[i+1]);
}
- config_fpgaintf_mod();
-}
-
-void config_peripheral(handoff *hoff_ptr)
-{
-
- // TODO: This need to be update due to peripheral_pwr_gate_array handoff change
- // Pending SDM to pass over handoff data
- // unsigned int i;
-
- // for (i = 0; i < 4; i += 2) {
- // mmio_write_32(AGX_EDGE_PERIPHERAL +
- // hoff_ptr->peripheral_pwr_gate_array[i],
- // hoff_ptr->peripheral_pwr_gate_array[i+1]);
- // }
-
+ /* Configure the IO delay */
+ for (i = 0; i < ARRAY_SIZE(hoff_ptr->pinmux_iodelay_array); i += 2) {
+ mmio_write_32(AGX5_PINMUX_IO0_DELAY + hoff_ptr->pinmux_iodelay_array[i],
+ hoff_ptr->pinmux_iodelay_array[i+1]);
+ }
- // TODO: This need to be update due to peripheral_pwr_gate_array handoff change
- mmio_write_32(AGX5_PERIPHERAL,
- hoff_ptr->peripheral_pwr_gate_array);
+ /* Enable/Disable individual interfaces between the FPGA and HPS */
+ config_fpgaintf_mod();
}
diff --git a/plat/intel/soc/agilex5/soc/agilex5_power_manager.c b/plat/intel/soc/agilex5/soc/agilex5_power_manager.c
index 0d81970..ef3acf9 100644
--- a/plat/intel/soc/agilex5/soc/agilex5_power_manager.c
+++ b/plat/intel/soc/agilex5/soc/agilex5_power_manager.c
@@ -1,5 +1,6 @@
/*
* Copyright (c) 2022-2023, Intel Corporation. All rights reserved.
+ * Copyright (c) 2024, Altera Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -13,7 +14,7 @@
#include "agilex5_power_manager.h"
#include "socfpga_reset_manager.h"
-int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff)
+static int wait_verify_fsm(uint16_t timeout, uint32_t peripheral_handoff)
{
uint32_t data = 0;
uint32_t count = 0;
@@ -38,7 +39,7 @@
return 0;
}
-int pss_sram_power_off(handoff *hoff_ptr)
+static int pss_sram_power_off(handoff *hoff_ptr)
{
int ret = 0;
uint32_t peripheral_handoff = 0;
@@ -66,7 +67,7 @@
{
int ret = 0;
- switch (hoff_ptr->header_magic) {
+ switch (hoff_ptr->peripheral_pwr_gate_magic) {
case HANDOFF_MAGIC_PERIPHERAL:
ret = pss_sram_power_off(hoff_ptr);
break;
diff --git a/plat/intel/soc/common/include/platform_def.h b/plat/intel/soc/common/include/platform_def.h
index 0788ab8..b388456 100644
--- a/plat/intel/soc/common/include/platform_def.h
+++ b/plat/intel/soc/common/include/platform_def.h
@@ -31,23 +31,15 @@
/* Define next boot image name and offset */
/* Get non-secure image entrypoint for BL33. Zephyr and Linux */
-#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
-#ifndef PRELOADED_BL33_BASE
-#define PLAT_NS_IMAGE_OFFSET 0x80200000
-#else
+#ifdef PRELOADED_BL33_BASE
#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
-#endif
-#define PLAT_HANDOFF_OFFSET 0x0003F000
-
#else
-/* Legacy Products. Please refactor with Agilex5 */
-#ifndef PRELOADED_BL33_BASE
-#define PLAT_NS_IMAGE_OFFSET 0x10000000
+#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
+#define PLAT_NS_IMAGE_OFFSET 0x80200000
#else
-#define PLAT_NS_IMAGE_OFFSET PRELOADED_BL33_BASE
-#endif
-#define PLAT_HANDOFF_OFFSET 0xFFE3F000
+#define PLAT_NS_IMAGE_OFFSET 0x10000000
#endif
+#endif /* #if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 */
#define PLAT_QSPI_DATA_BASE (0x3C00000)
#define PLAT_NAND_DATA_BASE (0x0200000)
diff --git a/plat/intel/soc/n5x/include/socfpga_plat_def.h b/plat/intel/soc/n5x/include/socfpga_plat_def.h
index c5e66c7..c477787 100644
--- a/plat/intel/soc/n5x/include/socfpga_plat_def.h
+++ b/plat/intel/soc/n5x/include/socfpga_plat_def.h
@@ -19,6 +19,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index cd4c163..cd5b076 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -18,6 +18,7 @@
#define PLAT_PRIMARY_CPU 0
#define PLAT_CLUSTER_ID_MPIDR_AFF_SHIFT MPIDR_AFF1_SHIFT
#define PLAT_CPU_ID_MPIDR_AFF_SHIFT MPIDR_AFF0_SHIFT
+#define PLAT_HANDOFF_OFFSET 0xFFE3F000
#define PLAT_TIMER_BASE_ADDR 0xFFD01000
/* FPGA config helpers */