Merge "fix: bl2 start address for RESET_TO_BL2+ENABLE_PIE" into integration
diff --git a/bl1/bl1.mk b/bl1/bl1.mk
index 95fe50e..53946ab 100644
--- a/bl1/bl1.mk
+++ b/bl1/bl1.mk
@@ -25,6 +25,10 @@
BL1_SOURCES += bl1/bl1_fwu.c
endif
+ifeq (${ENABLE_PMF},1)
+BL1_SOURCES += lib/pmf/pmf_main.c
+endif
+
ifneq ($(findstring gcc,$(notdir $(LD))),)
BL1_LDFLAGS += -Wl,--sort-section=alignment
else ifneq ($(findstring ld,$(notdir $(LD))),)
diff --git a/bl1/bl1_main.c b/bl1/bl1_main.c
index 3f64e27..6fe5511 100644
--- a/bl1/bl1_main.c
+++ b/bl1/bl1_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,7 +17,9 @@
#include <drivers/auth/auth_mod.h>
#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
#include <lib/cpus/errata.h>
+#include <lib/pmf/pmf.h>
#include <lib/utils.h>
#include <plat/common/platform.h>
#include <smccc_helpers.h>
@@ -31,6 +33,11 @@
uint64_t bl1_apiakey[2];
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE)
+#endif
+
/*******************************************************************************
* Helper utility to calculate the BL2 memory layout taking into consideration
* the BL1 RW data assuming that it is at the top of the memory layout.
@@ -81,6 +88,10 @@
{
unsigned int image_id;
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_ENTRY, PMF_CACHE_MAINT);
+#endif
+
/* Announce our arrival */
NOTICE(FIRMWARE_WELCOME_STR);
NOTICE("BL1: %s\n", version_string);
@@ -156,6 +167,10 @@
bl1_prepare_next_image(image_id);
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL1_EXIT, PMF_CACHE_MAINT);
+#endif
+
console_flush();
}
diff --git a/bl2/bl2.mk b/bl2/bl2.mk
index 1663c52..b70a3fb 100644
--- a/bl2/bl2.mk
+++ b/bl2/bl2.mk
@@ -49,3 +49,7 @@
BL2_DEFAULT_LINKER_SCRIPT_SOURCE := bl2/bl2_el3.ld.S
endif
+
+ifeq (${ENABLE_PMF},1)
+BL2_SOURCES += lib/pmf/pmf_main.c
+endif
\ No newline at end of file
diff --git a/bl2/bl2_main.c b/bl2/bl2_main.c
index ce83692..923a554 100644
--- a/bl2/bl2_main.c
+++ b/bl2/bl2_main.c
@@ -16,7 +16,9 @@
#include <drivers/auth/crypto_mod.h>
#include <drivers/console.h>
#include <drivers/fwu/fwu.h>
+#include <lib/bootmarker_capture.h>
#include <lib/extensions/pauth.h>
+#include <lib/pmf/pmf.h>
#include <plat/common/platform.h>
#include "bl2_private.h"
@@ -27,6 +29,11 @@
#define NEXT_IMAGE "BL32"
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE);
+#endif
+
#if RESET_TO_BL2
/*******************************************************************************
* Setup function for BL2 when RESET_TO_BL2=1
@@ -81,6 +88,10 @@
{
entry_point_info_t *next_bl_ep_info;
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_ENTRY, PMF_CACHE_MAINT);
+#endif
+
NOTICE("BL2: %s\n", version_string);
NOTICE("BL2: %s\n", build_message);
@@ -118,8 +129,6 @@
disable_mmu_icache_secure();
#endif /* !__aarch64__ */
- console_flush();
-
#if ENABLE_PAUTH
/*
* Disable pointer authentication before running next boot image
@@ -127,6 +136,12 @@
pauth_disable_el1();
#endif /* ENABLE_PAUTH */
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
+
+ console_flush();
+
/*
* Run next BL image via an SMC to BL1. Information on how to pass
* control to the BL32 (if present) and BL33 software images will
@@ -137,6 +152,9 @@
NOTICE("BL2: Booting " NEXT_IMAGE "\n");
print_entry_point_info(next_bl_ep_info);
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL2_EXIT, PMF_CACHE_MAINT);
+#endif
console_flush();
#if ENABLE_PAUTH
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 8f1f043..cae55f3 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -17,6 +17,7 @@
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
#include <drivers/console.h>
+#include <lib/bootmarker_capture.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/pmf/pmf.h>
#include <lib/runtime_instr.h>
@@ -24,10 +25,15 @@
#include <services/std_svc.h>
#if ENABLE_RUNTIME_INSTRUMENTATION
-PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
- RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
+ PMF_REGISTER_SERVICE_SMC(rt_instr_svc, PMF_RT_INSTR_SVC_ID,
+ RT_INSTR_TOTAL_IDS, PMF_STORE_ENABLE)
#endif
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_REGISTER_SERVICE(bl_svc, PMF_RT_INSTR_SVC_ID,
+ BL_TOTAL_IDS, PMF_DUMP_ENABLE)
+#endif
+
/*******************************************************************************
* This function pointer is used to initialise the BL32 image. It's initialized
* by SPD calling bl31_register_bl32_init after setting up all things necessary
@@ -123,6 +129,10 @@
detect_arch_features();
#endif /* FEATURE_DETECTION */
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_ENTRY, PMF_CACHE_MAINT);
+#endif
+
#ifdef SUPPORT_UNKNOWN_MPID
if (unsupported_mpid_flag == 0) {
NOTICE("Unsupported MPID detected!\n");
@@ -163,6 +173,7 @@
if (bl32_init != NULL) {
INFO("BL31: Initializing BL32\n");
+ console_flush();
int32_t rc = (*bl32_init)();
if (rc == 0) {
@@ -178,6 +189,7 @@
if (rmm_init != NULL) {
INFO("BL31: Initializing RMM\n");
+ console_flush();
int32_t rc = (*rmm_init)();
if (rc == 0) {
@@ -199,6 +211,11 @@
* from BL31
*/
bl31_plat_runtime_setup();
+
+#if ENABLE_RUNTIME_INSTRUMENTATION
+ PMF_CAPTURE_TIMESTAMP(bl_svc, BL31_EXIT, PMF_CACHE_MAINT);
+ console_flush();
+#endif
}
/*******************************************************************************
diff --git a/changelog.yaml b/changelog.yaml
index 3534cb0..9f5d4b7 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -1350,5 +1350,8 @@
- title: Node Package Manager (NPM)
scope: npm
+ - title: Poetry
+ scope: poetry
+
- title: zlib
scope: zlib
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 20c56fd..026a463 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -635,6 +635,13 @@
:|F|: docs/plat/imx8m.rst
:|F|: plat/imx/imx8m/
+NXP i.MX9 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Jacky Bai <ping.bai@nxp.com>
+:|G|: `JackyBai`_
+:|F|: docs/plat/imx9.rst
+:|F|: plat/imx/imx93/
+
NXP QorIQ Layerscape common code for platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
:|M|: Pankaj Gupta <pankaj.gupta@nxp.com>
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index 69d3722..d1bf0d3 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -604,6 +604,9 @@
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
+- ``ERRATA_N2_2009478``: This applies errata 2009478 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
+
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
@@ -715,6 +718,10 @@
CPU. This needs to be enabled only for revisions r0p0, r1p0 and r1p1 of the
CPU, it is still open.
+- ``ERRATA_X3_2742421``: This applies errata 2742421 workaround to
+ Cortex-X3 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
+ r1p1. It is fixed in r1p2.
+
For Cortex-A510, the following errata build flags are defined :
- ``ERRATA_A510_1922240``: This applies errata 1922240 workaround to
diff --git a/docs/getting_started/prerequisites.rst b/docs/getting_started/prerequisites.rst
index f4c3c28..332ed58 100644
--- a/docs/getting_started/prerequisites.rst
+++ b/docs/getting_started/prerequisites.rst
@@ -77,7 +77,7 @@
The following libraries are required for Trusted Board Boot and Measured Boot
support:
-- mbed TLS == 3.4.0 (tag: ``mbedtls-3.4.0``)
+- mbed TLS == 3.4.1 (tag: ``mbedtls-3.4.1``)
These tools are optional:
diff --git a/docs/perf/psci-performance-instr.rst b/docs/perf/psci-performance-instr.rst
index 16f386f..41094b2 100644
--- a/docs/perf/psci-performance-instr.rst
+++ b/docs/perf/psci-performance-instr.rst
@@ -13,16 +13,17 @@
Performance Measurement Framework
---------------------------------
-The Performance Measurement Framework `PMF`_ is a framework that provides
-mechanisms for collecting and retrieving timestamps at runtime from the
-Performance Measurement Unit (`PMU`_). The PMU is a generalized abstraction for
-accessing CPU hardware registers used to measure hardware events. This means,
-for instance, that the PMU might be used to place instrumentation points at
-logical locations in code for tracing purposes.
+The Performance Measurement Framework :ref:`PMF <firmware_design_pmf>`
+is a framework that provides mechanisms for collecting and retrieving timestamps
+at runtime from the Performance Measurement Unit
+(:ref:`PMU <Performance Monitoring Unit>`).
+The PMU is a generalized abstraction for accessing CPU hardware registers used to
+measure hardware events. This means, for instance, that the PMU might be used to
+place instrumentation points at logical locations in code for tracing purposes.
TF-A utilises the PMF as a backend for the two instrumentation services it
provides--PSCI Statistics and Runtime Instrumentation. The PMF is used by
-these services to facilitate collection and retrieval of timestamps. For
+these services to facilitate collection and retrieval of timestamps. For
instance, the PSCI Statistics service registers the PMF service
``psci_svc`` to track its residency statistics.
@@ -112,6 +113,4 @@
*Copyright (c) 2023, Arm Limited. All rights reserved.*
-.. _PMF: ../design/firmware-design.html#performance-measurement-framework
-.. _PMU: performance-monitoring-unit.html
.. _PSCI: https://developer.arm.com/documentation/den0022/latest/
diff --git a/docs/perf/psci-performance-juno.rst b/docs/perf/psci-performance-juno.rst
index 7a484b8..d458d86 100644
--- a/docs/perf/psci-performance-juno.rst
+++ b/docs/perf/psci-performance-juno.rst
@@ -34,8 +34,9 @@
- TF-A [`v2.9-rc0`_]
- TFTF [`v2.9-rc0`_]
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>`
+page for more details.
Procedure
---------
@@ -418,4 +419,3 @@
.. _Juno R1 platform: https://developer.arm.com/documentation/100122/latest/
.. _TF master as of 31/01/2017: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?id=c38b36d
.. _v2.9-rc0: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/tree/?h=v2.9-rc0
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
diff --git a/docs/perf/psci-performance-n1sdp.rst b/docs/perf/psci-performance-n1sdp.rst
index 70a1436..ae1b89b 100644
--- a/docs/perf/psci-performance-n1sdp.rst
+++ b/docs/perf/psci-performance-n1sdp.rst
@@ -10,8 +10,8 @@
- TFTF [`v2.9-rc0`_]
- SCP/MCP `Prebuilt Images`_
-Please see the Runtime Instrumentation `Testing Methodology`_ page for more
-details.
+Please see the Runtime Instrumentation :ref:`Testing Methodology
+<Runtime Instrumentation Methodology>` page for more details.
Procedure
---------
@@ -200,4 +200,3 @@
.. _user guide: https://gitlab.arm.com/arm-reference-solutions/arm-reference-solutions-docs/-/blob/master/docs/n1sdp/user-guide.rst
.. _Prebuilt Images: https://downloads.trustedfirmware.org/tf-a/css_scp_2.11.0/n1sdp/release/
.. _N1SDP: https://developer.arm.com/documentation/101489/latest
-.. _Testing Methodology: ../perf/psci-performance-methodology.html
\ No newline at end of file
diff --git a/docs/threat_model/threat_model.rst b/docs/threat_model/threat_model.rst
index c50ed8e..57a5e1b 100644
--- a/docs/threat_model/threat_model.rst
+++ b/docs/threat_model/threat_model.rst
@@ -85,6 +85,8 @@
+-----------------+--------------------------------------------------------+
+.. _threat_analysis:
+
***************
Threat Analysis
***************
diff --git a/docs/threat_model/threat_model_el3_spm.rst b/docs/threat_model/threat_model_el3_spm.rst
index c3af7a2..8adf3df 100644
--- a/docs/threat_model/threat_model_el3_spm.rst
+++ b/docs/threat_model/threat_model_el3_spm.rst
@@ -4,7 +4,7 @@
************
Introduction
************
-This document provides a threat model for the TF-A `EL3 Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`EL3 Secure Partition Manager`
(EL3 SPM) implementation. The EL3 SPM implementation is based on the
`Arm Firmware Framework for Arm A-profile`_ specification.
@@ -13,7 +13,8 @@
********************
In this threat model, the target of evaluation is the ``Secure Partition Manager Core``
component (SPMC) within the EL3 firmware.
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The scope for this threat model is:
@@ -70,8 +71,8 @@
Threat Analysis
***************
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
-The following sections define:
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`. The following sections define:
- Trust boundaries
- Assets
@@ -115,7 +116,8 @@
Threat types
============
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
are re-used:
- Spoofing
@@ -642,9 +644,7 @@
---------------
-*Copyright (c) 2022, Arm Limited. All rights reserved.*
+*Copyright (c) 2022-2023, Arm Limited. All rights reserved.*
.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _EL3 Secure Partition Manager: ../components/el3-spmc.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/docs/threat_model/threat_model_spm.rst b/docs/threat_model/threat_model_spm.rst
index 9458a9f..24a115b 100644
--- a/docs/threat_model/threat_model_spm.rst
+++ b/docs/threat_model/threat_model_spm.rst
@@ -4,7 +4,7 @@
************************
Introduction
************************
-This document provides a threat model for the TF-A `Secure Partition Manager`_
+This document provides a threat model for the TF-A :ref:`Secure Partition Manager`
(SPM) implementation or more generally the S-EL2 reference firmware running on
systems implementing the FEAT_SEL2 (formerly Armv8.4 Secure EL2) architecture
extension. The SPM implementation is based on the `Arm Firmware Framework for
@@ -28,7 +28,8 @@
************************
In this threat model, the target of evaluation is the S-EL2 firmware or the
``Secure Partition Manager Core`` component (SPMC).
-The monitor and SPMD at EL3 are covered by the `Generic TF-A threat model`_.
+The monitor and SPMD at EL3 are covered by the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The scope for this threat model is:
@@ -92,7 +93,8 @@
Threat Analysis
*********************
-This threat model follows a similar methodology to the `Generic TF-A threat model`_.
+This threat model follows a similar methodology to the :ref:`Generic TF-A threat model
+<threat_analysis>`.
The following sections define:
- Trust boundaries
@@ -141,7 +143,8 @@
Threat types
============================
-The following threat categories as exposed in the `Generic TF-A threat model`_
+The following threat categories as exposed in the :ref:`Generic TF-A threat model
+<threat_analysis>`
are re-used:
- Spoofing
@@ -1333,7 +1336,5 @@
*Copyright (c) 2021-2023, Arm Limited. All rights reserved.*
.. _Arm Firmware Framework for Arm A-profile: https://developer.arm.com/docs/den0077/latest
-.. _Secure Partition Manager: ../components/secure-partition-manager.html
-.. _Generic TF-A threat model: ./threat_model.html#threat-analysis
.. _FF-A ACS: https://github.com/ARM-software/ff-a-acs/releases
diff --git a/drivers/cadence/uart/aarch64/cdns_console.S b/drivers/cadence/uart/aarch64/cdns_console.S
index 4c1a80e..1bdaa48 100644
--- a/drivers/cadence/uart/aarch64/cdns_console.S
+++ b/drivers/cadence/uart/aarch64/cdns_console.S
@@ -197,7 +197,14 @@
cmp x0, #0
ASM_ASSERT(ne)
#endif /* ENABLE_ASSERTIONS */
- /* Placeholder */
+ /* Loop until the transmit FIFO is empty */
+check_txfifo_empty:
+ ldr w2, [x0, #R_UART_SR]
+ tbz w2, #UART_SR_INTR_TEMPTY_BIT, check_txfifo_empty
+ /* Wait until the Transmit is Inactive */
+check_tx_inactive_state:
+ ldr w2, [x0, #R_UART_SR]
+ tbnz w2, #UART_SR_INTR_TACTIVE_BIT, check_tx_inactive_state
ret
endfunc console_cdns_core_flush
diff --git a/fdts/morello-fvp.dts b/fdts/morello-fvp.dts
index dc3df41..fda0f55 100644
--- a/fdts/morello-fvp.dts
+++ b/fdts/morello-fvp.dts
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,6 +25,32 @@
};
};
+ /*
+ * The timings below are just to demonstrate working cpuidle.
+ * These values may be inaccurate.
+ */
+ idle-states {
+ entry-method = "psci";
+
+ cluster_sleep: cluster-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000022>;
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1000>;
+ min-residency-us = <2500>;
+ };
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000002>;
+ local-timer-stop;
+ entry-latency-us = <150>;
+ exit-latency-us = <300>;
+ min-residency-us = <200>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -53,6 +79,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU1: cpu1@100 {
compatible = "arm,armv8";
@@ -60,6 +87,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 0>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU2: cpu2@10000 {
compatible = "arm,armv8";
@@ -67,6 +95,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
CPU3: cpu3@10100 {
compatible = "arm,armv8";
@@ -74,6 +103,7 @@
device_type = "cpu";
enable-method = "psci";
clocks = <&scmi_dvfs 1>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
};
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index f207c06..fba904b 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -26,6 +26,32 @@
};
};
+ /*
+ * The timings below are just to demonstrate working cpuidle.
+ * These values may be inaccurate.
+ */
+ idle-states {
+ entry-method = "psci";
+
+ cluster_sleep: cluster-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000022>;
+ local-timer-stop;
+ entry-latency-us = <500>;
+ exit-latency-us = <1000>;
+ min-residency-us = <2500>;
+ };
+
+ cpu_sleep: cpu-sleep {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x40000002>;
+ local-timer-stop;
+ entry-latency-us = <150>;
+ exit-latency-us = <300>;
+ min-residency-us = <200>;
+ };
+ };
+
cpus {
#address-cells = <2>;
#size-cells = <0>;
@@ -44,6 +70,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu1: cpu1@100 {
compatible = "arm,armv8";
@@ -60,6 +87,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu2: cpu2@10000 {
compatible = "arm,armv8";
@@ -76,6 +104,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
cpu3: cpu3@10100 {
compatible = "arm,armv8";
@@ -92,6 +121,7 @@
1800000 750000
>;
#cooling-cells = <2>;
+ cpu-idle-states = <&cpu_sleep &cluster_sleep>;
};
};
diff --git a/include/drivers/cadence/cdns_uart.h b/include/drivers/cadence/cdns_uart.h
index 30ca910..327c1d9 100644
--- a/include/drivers/cadence/cdns_uart.h
+++ b/include/drivers/cadence/cdns_uart.h
@@ -22,6 +22,7 @@
#define UART_SR_INTR_REMPTY_BIT 1
#define UART_SR_INTR_TFUL_BIT 4
#define UART_SR_INTR_TEMPTY_BIT 3
+#define UART_SR_INTR_TACTIVE_BIT 11
#define R_UART_TX 0x30
#define R_UART_RX 0x30
diff --git a/include/lib/bootmarker_capture.h b/include/lib/bootmarker_capture.h
new file mode 100644
index 0000000..31fe048
--- /dev/null
+++ b/include/lib/bootmarker_capture.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2023, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef BOOTMARKER_CAPTURE_H
+#define BOOTMARKER_CAPTURE_H
+
+#define BL1_ENTRY U(0)
+#define BL1_EXIT U(1)
+#define BL2_ENTRY U(2)
+#define BL2_EXIT U(3)
+#define BL31_ENTRY U(4)
+#define BL31_EXIT U(5)
+#define BL_TOTAL_IDS U(6)
+
+#ifdef __ASSEMBLER__
+PMF_DECLARE_CAPTURE_TIMESTAMP(bl_svc)
+#endif /*__ASSEMBLER__*/
+
+#endif /*BOOTMARKER_CAPTURE_H*/
diff --git a/include/lib/cpus/aarch64/cortex_x3.h b/include/lib/cpus/aarch64/cortex_x3.h
index ceafe66..e648734 100644
--- a/include/lib/cpus/aarch64/cortex_x3.h
+++ b/include/lib/cpus/aarch64/cortex_x3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -31,4 +31,11 @@
#define CORTEX_X3_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_X3_CPUACTLR2_EL1_BIT_36 (ULL(1) << 36)
+/*******************************************************************************
+ * CPU Auxiliary Control register 5 specific definitions.
+ ******************************************************************************/
+#define CORTEX_X3_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
+#define CORTEX_X3_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
+
#endif /* CORTEX_X3_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index e8461f5..2fdbfb7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -39,6 +39,20 @@
* - Region 1 with secure access only;
* - the remaining DRAM regions access from the given Non-Secure masters.
******************************************************************************/
+
+#if ENABLE_RME
+#define ARM_TZC_RME_REGIONS_DEF \
+ {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
+ {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
+ {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ /* Realm and Shared area share the same PAS */ \
+ {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
+ PLAT_ARM_TZC_NS_DEV_ACCESS}
+#endif
+
#if SPM_MM
#define ARM_TZC_REGIONS_DEF \
{ARM_AP_TZC_DRAM1_BASE, ARM_EL3_TZC_DRAM1_END + ARM_L1_GPT_SIZE,\
@@ -52,16 +66,16 @@
PLAT_ARM_TZC_NS_DEV_ACCESS}
#elif ENABLE_RME
-#define ARM_TZC_REGIONS_DEF \
- {ARM_AP_TZC_DRAM1_BASE, ARM_AP_TZC_DRAM1_END, TZC_REGION_S_RDWR, 0},\
- {ARM_EL3_TZC_DRAM1_BASE, ARM_L1_GPT_END, TZC_REGION_S_RDWR, 0}, \
- {ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- /* Realm and Shared area share the same PAS */ \
- {ARM_REALM_BASE, ARM_EL3_RMM_SHARED_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}, \
- {ARM_DRAM2_BASE, ARM_DRAM2_END, ARM_TZC_NS_DRAM_S_ACCESS, \
- PLAT_ARM_TZC_NS_DEV_ACCESS}
+#if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
+MEASURED_BOOT
+#define ARM_TZC_REGIONS_DEF \
+ ARM_TZC_RME_REGIONS_DEF, \
+ {ARM_EVENT_LOG_DRAM1_BASE, ARM_EVENT_LOG_DRAM1_END, \
+ TZC_REGION_S_RDWR, 0}
+#else
+#define ARM_TZC_REGIONS_DEF \
+ ARM_TZC_RME_REGIONS_DEF
+#endif
#else
#define ARM_TZC_REGIONS_DEF \
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index c781d38..98d148e 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -42,6 +42,14 @@
check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
+workaround_reset_start cortex_x3, ERRATUM(2742421), ERRATA_X3_2742421
+ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+ sysreg_bit_set CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_55
+ sysreg_bit_clear CORTEX_X3_CPUACTLR5_EL1, CORTEX_X3_CPUACTLR5_EL1_BIT_56
+workaround_reset_end cortex_x3, ERRATUM(2742421)
+
+check_erratum_ls cortex_x3, ERRATUM(2742421), CPU_REV(1, 1)
+
workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
#if IMAGE_BL31
override_vector_table wa_cve_vbar_cortex_x3
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index acf8dee..ead3908 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -68,6 +68,22 @@
check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ /* Stash ERRSELR_EL1 in x2 */
+ mrs x2, ERRSELR_EL1
+
+ /* Select error record 0 and clear ED bit */
+ msr ERRSELR_EL1, xzr
+ mrs x1, ERXCTLR_EL1
+ bfi x1, xzr, #ERXCTLR_ED_SHIFT, #1
+ msr ERXCTLR_EL1, x1
+
+ /* Restore ERRSELR_EL1 from x2 */
+ msr ERRSELR_EL1, x2
+workaround_runtime_end neoverse_n2, ERRATUM(2009478), NO_ISB
+
+check_erratum_ls neoverse_n2, ERRATUM(2009478), CPU_REV(0, 0)
+
workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
/* Apply instruction patching sequence */
mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
@@ -233,7 +249,9 @@
func neoverse_n2_core_pwr_dwn
- apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
+ apply_erratum neoverse_n2, ERRATUM(2009478), ERRATA_N2_2009478
+ apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639, NO_GET_CPU_REV
+
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 8df0a29..0d8f4d4 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -615,6 +615,10 @@
# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
+# Flag to apply erratum 2009478 workaround during powerdown. This erratum
+# applies to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
+CPU_FLAG_LIST += ERRATA_N2_2009478
+
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2067956
@@ -738,6 +742,10 @@
# to revisions r0p0, r1p0, r1p1 of the Cortex-X3 cpu, it is still open.
CPU_FLAG_LIST += ERRATA_X3_2615812
+# Flag to apply erratum 2742421 workaround on reset. This erratum applies
+# to revisions r0p0, r1p0 and r1p1 of the Cortex-X3 cpu, it is fixed in r1p2.
+CPU_FLAG_LIST += ERRATA_X3_2742421
+
# Flag to apply erratum 1922240 workaround during reset. This erratum applies
# to revision r0p0 of the Cortex-A510 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_A510_1922240
diff --git a/make_helpers/tbbr/tbbr_tools.mk b/make_helpers/tbbr/tbbr_tools.mk
index a3351eb..3a2c53f 100644
--- a/make_helpers/tbbr/tbbr_tools.mk
+++ b/make_helpers/tbbr/tbbr_tools.mk
@@ -118,8 +118,10 @@
ifeq (${NEED_BL32},yes)
$(if ${BL32_KEY},$(eval $(call CERT_ADD_CMD_OPT,${BL32_KEY},--tos-fw-key)))
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_content.crt,--tos-fw-cert))
+ifneq (${COT},cca)
$(eval $(call TOOL_ADD_PAYLOAD,${BUILD_PLAT}/tos_fw_key.crt,--tos-fw-key-cert))
endif
+endif
# Add the BL33 CoT (key cert + img cert)
ifneq (${BL33},)
diff --git a/package-lock.json b/package-lock.json
index 89ebd51..e23f9a4 100644
--- a/package-lock.json
+++ b/package-lock.json
@@ -3894,9 +3894,9 @@
}
},
"node_modules/word-wrap": {
- "version": "1.2.3",
- "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz",
- "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==",
+ "version": "1.2.4",
+ "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz",
+ "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==",
"dev": true,
"engines": {
"node": ">=0.10.0"
@@ -4022,7 +4022,7 @@
}
},
"tools/conventional-changelog-tf-a": {
- "version": "2.7.0",
+ "version": "2.9.0",
"dev": true,
"license": "BSD-3-Clause",
"dependencies": {
@@ -6978,9 +6978,9 @@
}
},
"word-wrap": {
- "version": "1.2.3",
- "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.3.tgz",
- "integrity": "sha512-Hz/mrNwitNRh/HUAtM/VT/5VH+ygD6DV7mYKZAtHOrbs8U7lvPS6xf7EJKMF0uW1KJCl0H701g3ZGus+muE5vQ==",
+ "version": "1.2.4",
+ "resolved": "https://registry.npmjs.org/word-wrap/-/word-wrap-1.2.4.tgz",
+ "integrity": "sha512-2V81OA4ugVo5pRo46hAoD2ivUJx8jXmWXfUkY4KFNw0hEptvN0QfH3K4nHiwzGeKl5rFKedV48QVoqYavy4YpA==",
"dev": true
},
"wordwrap": {
diff --git a/plat/arm/board/common/board_common.mk b/plat/arm/board/common/board_common.mk
index 777784d..4665827 100644
--- a/plat/arm/board/common/board_common.mk
+++ b/plat/arm/board/common/board_common.mk
@@ -52,8 +52,6 @@
# Force generation of the new hash if ROT_KEY is specified
ifdef ROT_KEY
HASH_PREREQUISITES = $(ROT_KEY) FORCE
-else
- HASH_PREREQUISITES = $(ROT_KEY)
endif
$(ARM_ROTPK_HASH) : $(HASH_PREREQUISITES)
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index df04617..826fca2 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -168,8 +168,13 @@
# define MAX_XLAT_TABLES 6
# endif
#elif !USE_ROMLIB
-# define PLAT_ARM_MMAP_ENTRIES 11
-# define MAX_XLAT_TABLES 5
+# if ENABLE_RME && defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES 12
+# define MAX_XLAT_TABLES 6
+# else
+# define PLAT_ARM_MMAP_ENTRIES 11
+# define MAX_XLAT_TABLES 5
+# endif /* (IMAGE_BL2 && ENABLE_RME) */
#else
# define PLAT_ARM_MMAP_ENTRIES 12
# if (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd)) && \
@@ -437,7 +442,12 @@
/*
* Maximum size of Event Log buffer used in Measured Boot Event Log driver
*/
+#if ENABLE_RME && (defined(SPD_tspd) || defined(SPD_opteed) || defined(SPD_spmd))
+/* Account for additional measurements of secure partitions and SPM. */
+#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x800)
+#else
#define PLAT_ARM_EVENT_LOG_MAX_SIZE UL(0x400)
+#endif
/*
* Maximum size of Event Log buffer used for DRTM
diff --git a/plat/arm/board/morello/platform.mk b/plat/arm/board/morello/platform.mk
index 0ae7693..12ffb5a 100644
--- a/plat/arm/board/morello/platform.mk
+++ b/plat/arm/board/morello/platform.mk
@@ -89,6 +89,9 @@
override ARM_BL31_IN_DRAM := 1
+override PSCI_EXTENDED_STATE_ID := 1
+override ARM_RECOM_STATE_ID_ENC := 1
+
# Errata workarounds:
ERRATA_N1_1868343 := 1
diff --git a/plat/qemu/common/common.mk b/plat/qemu/common/common.mk
index b8b57d2..a4933c9 100644
--- a/plat/qemu/common/common.mk
+++ b/plat/qemu/common/common.mk
@@ -20,12 +20,25 @@
lib/cpus/aarch64/cortex_a57.S \
lib/cpus/aarch64/cortex_a72.S \
lib/cpus/aarch64/cortex_a76.S \
+ lib/cpus/aarch64/cortex_a710.S \
lib/cpus/aarch64/neoverse_n_common.S \
lib/cpus/aarch64/neoverse_n1.S \
lib/cpus/aarch64/neoverse_v1.S \
lib/cpus/aarch64/qemu_max.S
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
+
+# Cpu core architecture level:
+# v8.0: a53, a57, a72
+# v8.2: a76, n1
+# v8.4: v1
+# v9.0: a710
+#
+# let treat v9.0 as v8.5 as they share cpu features
+# https://developer.arm.com/documentation/102378/0201/Armv8-x-and-Armv9-x-extensions-and-features
+
+ARM_ARCH_MAJOR := 8
+ARM_ARCH_MINOR := 5
endif
PLAT_BL_COMMON_SOURCES := ${PLAT_QEMU_COMMON_PATH}/qemu_common.c \
diff --git a/plat/qemu/qemu/qemu_bl1_measured_boot.c b/plat/qemu/qemu/qemu_bl1_measured_boot.c
index 3d20f97..7984781 100644
--- a/plat/qemu/qemu/qemu_bl1_measured_boot.c
+++ b/plat/qemu/qemu/qemu_bl1_measured_boot.c
@@ -26,3 +26,9 @@
{
return 0;
}
+
+int plat_mboot_measure_key(const void *pk_oid, const void *pk_ptr,
+ size_t pk_len)
+{
+ return 0;
+}
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 7f93340..012aaa6 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -37,7 +37,7 @@
}
/* Reserve memory used by Trusted Firmware. */
- if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE + 1)) {
+ if (fdt_add_reserved_memory(dtb, "tf-a", BL31_BASE, BL31_LIMIT - BL31_BASE)) {
WARN("Failed to add reserved memory nodes for BL31 to DT.\n");
return;
}
diff --git a/poetry.lock b/poetry.lock
index 12d546a..08b2b37 100644
--- a/poetry.lock
+++ b/poetry.lock
@@ -1,4 +1,4 @@
-# This file is automatically @generated by Poetry 1.5.0 and should not be changed by hand.
+# This file is automatically @generated by Poetry 1.6.1 and should not be changed by hand.
[[package]]
name = "alabaster"
@@ -556,13 +556,13 @@
[[package]]
name = "requests"
-version = "2.30.0"
+version = "2.31.0"
description = "Python HTTP for Humans."
optional = false
python-versions = ">=3.7"
files = [
- {file = "requests-2.30.0-py3-none-any.whl", hash = "sha256:10e94cc4f3121ee6da529d358cdaeaff2f1c409cd377dbc72b825852f2f7e294"},
- {file = "requests-2.30.0.tar.gz", hash = "sha256:239d7d4458afcb28a692cdd298d87542235f4ca8d36d03a15bfc128a6559a2f4"},
+ {file = "requests-2.31.0-py3-none-any.whl", hash = "sha256:58cd2187c01e70e6e26505bca751777aa9f2ee0b7f4300988b709f44e013003f"},
+ {file = "requests-2.31.0.tar.gz", hash = "sha256:942c5a758f98d790eaed1a29cb6eefc7ffb0d1cf7af05c3d2791656dbd6ad1e1"},
]
[package.dependencies]
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 9906fac..e24a621 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -28,6 +28,7 @@
#include <cortex_a715.h>
#include <cortex_x1.h>
#include <cortex_x2.h>
+#include <cortex_x3.h>
#include <neoverse_n1.h>
#include <neoverse_n2.h>
#include <neoverse_v1.h>
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index 71a907b..8fee6ac 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -332,24 +332,25 @@
.cpu_partnumber = NEOVERSE_N2_MIDR,
.cpu_errata_list = {
[0] = {2002655, 0x00, 0x00, ERRATA_N2_2002655},
- [1] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
- [2] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
- [3] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
- [4] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
- [5] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
- [6] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
- [7] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
- [8] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
- [9] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
- [10] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
- [11] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
- [12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
- [13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
+ [1] = {2009478, 0x00, 0x00, ERRATA_N2_2009478},
+ [2] = {2025414, 0x00, 0x00, ERRATA_N2_2025414},
+ [3] = {2067956, 0x00, 0x00, ERRATA_N2_2067956},
+ [4] = {2138953, 0x00, 0x00, ERRATA_N2_2138953},
+ [5] = {2138956, 0x00, 0x00, ERRATA_N2_2138956},
+ [6] = {2138958, 0x00, 0x00, ERRATA_N2_2138958},
+ [7] = {2189731, 0x00, 0x00, ERRATA_N2_2189731},
+ [8] = {2242400, 0x00, 0x00, ERRATA_N2_2242400},
+ [9] = {2242415, 0x00, 0x00, ERRATA_N2_2242415},
+ [10] = {2280757, 0x00, 0x00, ERRATA_N2_2280757},
+ [11] = {2326639, 0x00, 0x00, ERRATA_N2_2326639},
+ [12] = {2376738, 0x00, 0x00, ERRATA_N2_2376738},
+ [13] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
+ [14] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
- [15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
- [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [15] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
+ [16] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [17] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
+ [18 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */
@@ -417,6 +418,18 @@
}
},
#endif /* CORTEX_A715_H_INC */
+
+#if CORTEX_X3_H_INC
+{
+ .cpu_partnumber = CORTEX_X3_MIDR,
+ .cpu_errata_list = {
+ [0] = {2313909, 0x00, 0x10, ERRATA_X3_2313909},
+ [1] = {2615812, 0x00, 0x11, ERRATA_X3_2615812},
+ [2] = {2742421, 0x00, 0x11, ERRATA_X3_2742421},
+ [3 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ }
+},
+#endif /* CORTEX_X3_H_INC */
};
/*