Provide cm_get/set_context() for current CPU
All callers of cm_get_context() pass the calling CPU MPIDR to the
function. Providing a specialised version for the current
CPU results in a reduction in code size and better readability.
The current function has been renamed to cm_get_context_by_mpidr()
and the existing name is now used for the current-CPU version.
The same treatment has been done to cm_set_context(), although
only both forms are used at present in the PSCI and TSPD code.
Change-Id: I91cb0c2f7bfcb950a045dbd9ff7595751c0c0ffb
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index f79a122..6765e60 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -71,9 +71,6 @@
******************************************************************************/
void bl31_main(void)
{
-#if DEBUG
- unsigned long mpidr = read_mpidr();
-#endif
/* Perform remaining generic architectural setup from EL3 */
bl31_arch_setup();
@@ -98,7 +95,7 @@
* structure which has an exception stack allocated. The PSCI
* service should have set the context.
*/
- assert(cm_get_context(mpidr, NON_SECURE));
+ assert(cm_get_context(NON_SECURE));
cm_set_next_eret_context(NON_SECURE);
cm_init_pcpu_ptr_cache();
write_vbar_el3((uint64_t) runtime_exceptions);
@@ -195,7 +192,7 @@
* Save the args generated in BL2 for the image in the right context
* used on its entry
*/
- ctx = cm_get_context(read_mpidr(), image_type);
+ ctx = cm_get_context(image_type);
gp_regs = get_gpregs_ctx(ctx);
memcpy(gp_regs, (void *)&next_image_info->args, sizeof(aapcs64_params_t));
diff --git a/bl31/context_mgmt.c b/bl31/context_mgmt.c
index b3dcf2d..b602840 100644
--- a/bl31/context_mgmt.c
+++ b/bl31/context_mgmt.c
@@ -77,10 +77,10 @@
/*******************************************************************************
* This function returns a pointer to the most recent 'cpu_context' structure
- * that was set as the context for the specified security state. NULL is
- * returned if no such structure has been specified.
+ * for the CPU identified by MPIDR that was set as the context for the specified
+ * security state. NULL is returned if no such structure has been specified.
******************************************************************************/
-void *cm_get_context(uint64_t mpidr, uint32_t security_state)
+void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state)
{
uint32_t linear_id = platform_get_core_pos(mpidr);
@@ -90,10 +90,24 @@
}
/*******************************************************************************
+ * This function returns a pointer to the most recent 'cpu_context' structure
+ * for the calling CPU that was set as the context for the specified security
+ * state. NULL is returned if no such structure has been specified.
+ ******************************************************************************/
+void *cm_get_context(uint32_t security_state)
+{
+ uint32_t linear_id = platform_get_core_pos(read_mpidr());
+
+ assert(security_state <= NON_SECURE);
+
+ return cm_context_info[linear_id].ptr[security_state];
+}
+
+/*******************************************************************************
* This function sets the pointer to the current 'cpu_context' structure for the
- * specified security state.
+ * specified security state for the CPU identified by MPIDR
******************************************************************************/
-void cm_set_context(uint64_t mpidr, void *context, uint32_t security_state)
+void cm_set_context_by_mpidr(uint64_t mpidr, void *context, uint32_t security_state)
{
uint32_t linear_id = platform_get_core_pos(mpidr);
@@ -103,6 +117,15 @@
}
/*******************************************************************************
+ * This function sets the pointer to the current 'cpu_context' structure for the
+ * specified security state for the calling CPU
+ ******************************************************************************/
+void cm_set_context(void *context, uint32_t security_state)
+{
+ cm_set_context_by_mpidr(read_mpidr(), context, security_state);
+}
+
+/*******************************************************************************
* The next four functions are used by runtime services to save and restore EL3
* and EL1 contexts on the 'cpu_context' structure for the specified security
* state.
@@ -111,7 +134,7 @@
{
cpu_context_t *ctx;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
el3_sysregs_context_save(get_el3state_ctx(ctx));
@@ -121,7 +144,7 @@
{
cpu_context_t *ctx;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
el3_sysregs_context_restore(get_el3state_ctx(ctx));
@@ -131,7 +154,7 @@
{
cpu_context_t *ctx;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
el1_sysregs_context_save(get_sysregs_ctx(ctx));
@@ -141,7 +164,7 @@
{
cpu_context_t *ctx;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
el1_sysregs_context_restore(get_sysregs_ctx(ctx));
@@ -159,7 +182,7 @@
cpu_context_t *ctx;
el3_state_t *state;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
/* Program the interrupt routing model for this security state */
@@ -183,7 +206,7 @@
cpu_context_t *ctx;
el3_state_t *state;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
/* Populate EL3 state so that ERET jumps to the correct entry */
@@ -204,7 +227,7 @@
el3_state_t *state;
uint32_t scr_el3;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
/* Ensure that the bit position is a valid one */
@@ -233,7 +256,7 @@
cpu_context_t *ctx;
el3_state_t *state;
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
/* Populate EL3 state so that ERET jumps to the correct entry */
@@ -253,7 +276,7 @@
uint64_t sp_mode;
#endif
- ctx = cm_get_context(read_mpidr(), security_state);
+ ctx = cm_get_context(security_state);
assert(ctx);
#if DEBUG
diff --git a/include/bl31/context_mgmt.h b/include/bl31/context_mgmt.h
index ce4f7a8..86bbc58 100644
--- a/include/bl31/context_mgmt.h
+++ b/include/bl31/context_mgmt.h
@@ -37,10 +37,12 @@
* Function & variable prototypes
******************************************************************************/
void cm_init(void);
-void *cm_get_context(uint64_t mpidr, uint32_t security_state);
-void cm_set_context(uint64_t mpidr,
- void *context,
- uint32_t security_state);
+void *cm_get_context_by_mpidr(uint64_t mpidr, uint32_t security_state);
+void *cm_get_context(uint32_t security_state);
+void cm_set_context_by_mpidr(uint64_t mpidr,
+ void *context,
+ uint32_t security_state);
+void cm_set_context(void *context, uint32_t security_state);
void cm_el3_sysregs_context_save(uint32_t security_state);
void cm_el3_sysregs_context_restore(uint32_t security_state);
void cm_el1_sysregs_context_save(uint32_t security_state);
diff --git a/services/spd/tspd/tspd_common.c b/services/spd/tspd/tspd_common.c
index 6b3592e..9242702 100644
--- a/services/spd/tspd/tspd_common.c
+++ b/services/spd/tspd/tspd_common.c
@@ -100,7 +100,7 @@
/* Associate this context with the cpu specified */
tsp_ctx->mpidr = mpidr;
- cm_set_context(mpidr, &tsp_ctx->cpu_ctx, SECURE);
+ cm_set_context(&tsp_ctx->cpu_ctx, SECURE);
spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
cm_set_el3_eret_context(SECURE, entrypoint, spsr, scr);
@@ -122,7 +122,7 @@
assert(tsp_ctx->c_rt_ctx == 0);
/* Apply the Secure EL1 system register context and switch to it */
- assert(cm_get_context(read_mpidr(), SECURE) == &tsp_ctx->cpu_ctx);
+ assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
cm_el1_sysregs_context_restore(SECURE);
cm_set_next_eret_context(SECURE);
@@ -146,7 +146,7 @@
void tspd_synchronous_sp_exit(tsp_context_t *tsp_ctx, uint64_t ret)
{
/* Save the Secure EL1 system register context */
- assert(cm_get_context(read_mpidr(), SECURE) == &tsp_ctx->cpu_ctx);
+ assert(cm_get_context(SECURE) == &tsp_ctx->cpu_ctx);
cm_el1_sysregs_context_save(SECURE);
assert(tsp_ctx->c_rt_ctx != 0);
diff --git a/services/spd/tspd/tspd_main.c b/services/spd/tspd/tspd_main.c
index 1a6913a..35bc6e2 100644
--- a/services/spd/tspd/tspd_main.c
+++ b/services/spd/tspd/tspd_main.c
@@ -95,7 +95,7 @@
/* Sanity check the pointer to this cpu's context */
mpidr = read_mpidr();
- assert(handle == cm_get_context(mpidr, NON_SECURE));
+ assert(handle == cm_get_context(NON_SECURE));
/* Save the non-secure context before entering the TSP */
cm_el1_sysregs_context_save(NON_SECURE);
@@ -103,7 +103,7 @@
/* Get a reference to this cpu's TSP context */
linear_id = platform_get_core_pos(mpidr);
tsp_ctx = &tspd_sp_context[linear_id];
- assert(&tsp_ctx->cpu_ctx == cm_get_context(mpidr, SECURE));
+ assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
/*
* Determine if the TSP was previously preempted. Its last known
@@ -275,10 +275,10 @@
if (ns)
SMC_RET1(handle, SMC_UNK);
- assert(handle == cm_get_context(mpidr, SECURE));
+ assert(handle == cm_get_context(SECURE));
cm_el1_sysregs_context_save(SECURE);
/* Get a reference to the non-secure context */
- ns_cpu_context = cm_get_context(mpidr, NON_SECURE);
+ ns_cpu_context = cm_get_context(NON_SECURE);
assert(ns_cpu_context);
/*
@@ -300,7 +300,7 @@
if (ns)
SMC_RET1(handle, SMC_UNK);
- assert(handle == cm_get_context(mpidr, SECURE));
+ assert(handle == cm_get_context(SECURE));
/*
* Restore the relevant EL3 state which saved to service
@@ -316,7 +316,7 @@
}
/* Get a reference to the non-secure context */
- ns_cpu_context = cm_get_context(mpidr, NON_SECURE);
+ ns_cpu_context = cm_get_context(NON_SECURE);
assert(ns_cpu_context);
/*
@@ -339,7 +339,7 @@
if (ns)
SMC_RET1(handle, SMC_UNK);
- assert(handle == cm_get_context(mpidr, SECURE));
+ assert(handle == cm_get_context(SECURE));
/* Assert that standard SMC execution has been preempted */
assert(get_std_smc_active_flag(tsp_ctx->state));
@@ -348,7 +348,7 @@
cm_el1_sysregs_context_save(SECURE);
/* Get a reference to the non-secure context */
- ns_cpu_context = cm_get_context(mpidr, NON_SECURE);
+ ns_cpu_context = cm_get_context(NON_SECURE);
assert(ns_cpu_context);
/* Restore non-secure state */
@@ -434,7 +434,7 @@
* registers need to be preserved, save the non-secure
* state and send the request to the secure payload.
*/
- assert(handle == cm_get_context(mpidr, NON_SECURE));
+ assert(handle == cm_get_context(NON_SECURE));
/* Check if we are already preempted */
if (get_std_smc_active_flag(tsp_ctx->state))
@@ -457,7 +457,7 @@
* payload. Entry into S-EL1 will take place upon exit
* from this function.
*/
- assert(&tsp_ctx->cpu_ctx == cm_get_context(mpidr, SECURE));
+ assert(&tsp_ctx->cpu_ctx == cm_get_context(SECURE));
/* Set appropriate entry for SMC.
* We expect the TSP to manage the PSTATE.I and PSTATE.F
@@ -482,11 +482,11 @@
* into the non-secure context, save the secure state
* and return to the non-secure state.
*/
- assert(handle == cm_get_context(mpidr, SECURE));
+ assert(handle == cm_get_context(SECURE));
cm_el1_sysregs_context_save(SECURE);
/* Get a reference to the non-secure context */
- ns_cpu_context = cm_get_context(mpidr, NON_SECURE);
+ ns_cpu_context = cm_get_context(NON_SECURE);
assert(ns_cpu_context);
/* Restore non-secure state */
@@ -515,7 +515,7 @@
* save the non-secure state and send the request to
* the secure payload.
*/
- assert(handle == cm_get_context(mpidr, NON_SECURE));
+ assert(handle == cm_get_context(NON_SECURE));
/* Check if we are already preempted before resume */
if (!get_std_smc_active_flag(tsp_ctx->state))
diff --git a/services/std_svc/psci/psci_afflvl_on.c b/services/std_svc/psci/psci_afflvl_on.c
index e3a1831..443e6af 100644
--- a/services/std_svc/psci/psci_afflvl_on.c
+++ b/services/std_svc/psci/psci_afflvl_on.c
@@ -378,7 +378,7 @@
* structure. The calling cpu should have set the
* context already
*/
- assert(cm_get_context(mpidr, NON_SECURE));
+ assert(cm_get_context(NON_SECURE));
cm_set_next_eret_context(NON_SECURE);
cm_init_pcpu_ptr_cache();
write_vbar_el3((uint64_t) runtime_exceptions);
diff --git a/services/std_svc/psci/psci_afflvl_suspend.c b/services/std_svc/psci/psci_afflvl_suspend.c
index 377afdf..a986e5c 100644
--- a/services/std_svc/psci/psci_afflvl_suspend.c
+++ b/services/std_svc/psci/psci_afflvl_suspend.c
@@ -180,7 +180,7 @@
* The EL3 state to PoC since it will be accessed after a
* reset with the caches turned off
*/
- saved_el3_state = get_el3state_ctx(cm_get_context(mpidr, NON_SECURE));
+ saved_el3_state = get_el3state_ctx(cm_get_context(NON_SECURE));
flush_dcache_range((uint64_t) saved_el3_state, sizeof(*saved_el3_state));
/* Set the secure world (EL3) re-entry point after BL1 */
@@ -496,7 +496,6 @@
* structure. The non-secure context should have been
* set on this cpu prior to suspension.
*/
- assert(cm_get_context(mpidr, NON_SECURE));
cm_set_next_eret_context(NON_SECURE);
cm_init_pcpu_ptr_cache();
write_vbar_el3((uint64_t) runtime_exceptions);
diff --git a/services/std_svc/psci/psci_common.c b/services/std_svc/psci/psci_common.c
index b1ee10d..3cbacd7 100644
--- a/services/std_svc/psci/psci_common.c
+++ b/services/std_svc/psci/psci_common.c
@@ -219,7 +219,6 @@
void psci_get_ns_entry_info(unsigned int index)
{
unsigned long sctlr = 0, scr, el_status, id_aa64pfr0;
- uint64_t mpidr = read_mpidr();
cpu_context_t *ns_entry_context;
gp_regs_t *ns_entry_gpregs;
@@ -253,7 +252,7 @@
write_sctlr_el1(sctlr);
/* Fulfill the cpu_on entry reqs. as per the psci spec */
- ns_entry_context = (cpu_context_t *) cm_get_context(mpidr, NON_SECURE);
+ ns_entry_context = (cpu_context_t *) cm_get_context(NON_SECURE);
assert(ns_entry_context);
/*
diff --git a/services/std_svc/psci/psci_setup.c b/services/std_svc/psci/psci_setup.c
index a1587b7..015beab 100644
--- a/services/std_svc/psci/psci_setup.c
+++ b/services/std_svc/psci/psci_setup.c
@@ -210,9 +210,9 @@
linear_id = platform_get_core_pos(mpidr);
assert(linear_id < PLATFORM_CORE_COUNT);
- cm_set_context(mpidr,
- (void *) &psci_ns_context[linear_id],
- NON_SECURE);
+ cm_set_context_by_mpidr(mpidr,
+ (void *) &psci_ns_context[linear_id],
+ NON_SECURE);
}