tree 59db68cb28a53c34e6678dd9f1b6281fddbc8955
parent 03aa014174398daa8027011518c5ec6b5378ba88
author Varun Wadekar <vwadekar@nvidia.com> 1521827080 -0700
committer Varun Wadekar <vwadekar@nvidia.com> 1579798949 -0800

Tegra194: access XUSB_PADCTL registers on Si/FPGA platforms

Many simulation/emulation platforms do not support this hardware block
leading to SErrors during register accesses.

This patch conditionally accesses the registers from this block only
on actual Si and FPGA platforms.

Change-Id: Ic22817a8c9f81978ba88c5362bfd734a0040d35d
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>