diff --git a/drivers/st/clk/stm32mp1_clk.c b/drivers/st/clk/stm32mp1_clk.c
index e4cc9b9..02866a2 100644
--- a/drivers/st/clk/stm32mp1_clk.c
+++ b/drivers/st/clk/stm32mp1_clk.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  */
@@ -777,7 +777,7 @@
 	return clock;
 }
 
-bool stm32mp1_clk_is_enabled(unsigned long id)
+bool stm32mp_clk_is_enabled(unsigned long id)
 {
 	struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
 	const struct stm32mp1_clk_gate *gate = priv->data->gate;
@@ -791,7 +791,7 @@
 		 BIT(gate[i].bit)) != 0U);
 }
 
-int stm32mp1_clk_enable(unsigned long id)
+int stm32mp_clk_enable(unsigned long id)
 {
 	struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
 	const struct stm32mp1_clk_gate *gate = priv->data->gate;
@@ -810,7 +810,7 @@
 	return 0;
 }
 
-int stm32mp1_clk_disable(unsigned long id)
+int stm32mp_clk_disable(unsigned long id)
 {
 	struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
 	const struct stm32mp1_clk_gate *gate = priv->data->gate;
@@ -831,7 +831,7 @@
 	return 0;
 }
 
-unsigned long stm32mp1_clk_get_rate(unsigned long id)
+unsigned long stm32mp_clk_get_rate(unsigned long id)
 {
 	struct stm32mp1_clk_priv *priv = &stm32mp1_clk_priv_data;
 	int p = stm32mp1_clk_get_parent(priv, id);
diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index 79aff6e..b934754 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -639,7 +639,7 @@
 	 */
 
 	/* Change Bypass Mode Frequency Range */
-	if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) {
+	if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
 		mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
 				DDRPHYC_DLLGCR_BPS200);
 	} else {
diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c
index e65fbea..532062e 100644
--- a/drivers/st/ddr/stm32mp1_ram.c
+++ b/drivers/st/ddr/stm32mp1_ram.c
@@ -31,7 +31,7 @@
 
 	ddr_enable_clock();
 
-	ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC);
+	ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
 
 	VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
 		mem_speed, ddrphy_clk / 1000U);
@@ -65,10 +65,10 @@
 	uint32_t pattern;
 
 	for (pattern = 1U; pattern != 0U; pattern <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE, pattern);
+		mmio_write_32(STM32MP_DDR_BASE, pattern);
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) {
-			return (uint32_t)STM32MP1_DDR_BASE;
+		if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
+			return (uint32_t)STM32MP_DDR_BASE;
 		}
 	}
 
@@ -92,44 +92,44 @@
 	/* Write the default pattern at each of the power-of-two offsets. */
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset,
 			      DDR_PATTERN);
 	}
 
 	/* Check for address bits stuck high. */
-	mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 		      DDR_ANTIPATTERN);
 
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1) {
-		if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) !=
+		if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) !=
 		    DDR_PATTERN) {
-			return (uint32_t)(STM32MP1_DDR_BASE + offset);
+			return (uint32_t)(STM32MP_DDR_BASE + offset);
 		}
 	}
 
-	mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
+	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
 
 	/* Check for address bits stuck low or shorted. */
 	for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
 	     testoffset <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 			      DDR_ANTIPATTERN);
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
-			return STM32MP1_DDR_BASE;
+		if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+			return STM32MP_DDR_BASE;
 		}
 
 		for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 		     offset <<= 1) {
-			if ((mmio_read_32(STM32MP1_DDR_BASE +
+			if ((mmio_read_32(STM32MP_DDR_BASE +
 					  (uint32_t)offset) != DDR_PATTERN) &&
 			    (offset != testoffset)) {
-				return (uint32_t)(STM32MP1_DDR_BASE + offset);
+				return (uint32_t)(STM32MP_DDR_BASE + offset);
 			}
 		}
 
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 			      DDR_PATTERN);
 	}
 
@@ -147,13 +147,13 @@
 {
 	uint32_t offset = sizeof(uint32_t);
 
-	mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN);
+	mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
 
-	while (offset < STM32MP1_DDR_MAX_SIZE) {
-		mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN);
+	while (offset < STM32MP_DDR_MAX_SIZE) {
+		mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
 		dsb();
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
+		if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
 			break;
 		}
 
@@ -240,15 +240,15 @@
 		}
 	}
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
+	if (!stm32mp_clk_is_enabled(RTCAPB)) {
 		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
+		if (stm32mp_clk_enable(RTCAPB) != 0) {
 			return -EINVAL;
 		}
 	}
 
 	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
+		if (stm32mp_clk_disable(RTCAPB) != 0) {
 			return -EINVAL;
 		}
 	}
@@ -306,7 +306,7 @@
 	priv->pwr = PWR_BASE;
 	priv->rcc = RCC_BASE;
 
-	priv->info.base = STM32MP1_DDR_BASE;
+	priv->info.base = STM32MP_DDR_BASE;
 	priv->info.size = 0;
 
 	return stm32mp1_ddr_setup();
diff --git a/drivers/st/gpio/stm32_gpio.c b/drivers/st/gpio/stm32_gpio.c
index 5fee82c..1d8111a 100644
--- a/drivers/st/gpio/stm32_gpio.c
+++ b/drivers/st/gpio/stm32_gpio.c
@@ -208,7 +208,7 @@
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp1_clk_enable(clock);
+	stm32mp_clk_enable(clock);
 
 	mmio_clrbits_32(base + GPIO_MODE_OFFSET,
 			((uint32_t)GPIO_MODE_MASK << (pin << 1)));
@@ -254,7 +254,7 @@
 	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
 		mmio_read_32(base + GPIO_AFRH_OFFSET));
 
-	stm32mp1_clk_disable(clock);
+	stm32mp_clk_disable(clock);
 }
 
 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
@@ -264,7 +264,7 @@
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp1_clk_enable(clock);
+	stm32mp_clk_enable(clock);
 
 	if (secure) {
 		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@@ -272,5 +272,5 @@
 		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
 	}
 
-	stm32mp1_clk_disable(clock);
+	stm32mp_clk_disable(clock);
 }
diff --git a/drivers/st/mmc/stm32_sdmmc2.c b/drivers/st/mmc/stm32_sdmmc2.c
index 57812d8..10fd5f5 100644
--- a/drivers/st/mmc/stm32_sdmmc2.c
+++ b/drivers/st/mmc/stm32_sdmmc2.c
@@ -19,9 +19,9 @@
 #include <drivers/mmc.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32_sdmmc2.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <dt-bindings/reset/stm32mp1-resets.h>
 #include <lib/mmio.h>
@@ -159,7 +159,7 @@
 	uintptr_t base = sdmmc2_params.reg_base;
 
 	clock_div = div_round_up(sdmmc2_params.clk_rate,
-				 STM32MP1_MMC_INIT_FREQ * 2);
+				 STM32MP_MMC_INIT_FREQ * 2);
 
 	mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
 		      sdmmc2_params.negedge |
@@ -429,15 +429,15 @@
 
 	if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
 		if (max_bus_freq >= 52000000U) {
-			max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ;
+			max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
 		} else {
-			max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ;
+			max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
 		}
 	} else {
 		if (max_bus_freq >= 50000000U) {
-			max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ;
+			max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
 		} else {
-			max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ;
+			max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
 		}
 	}
 
@@ -720,19 +720,19 @@
 		return -ENOMEM;
 	}
 
-	ret = stm32mp1_clk_enable(sdmmc2_params.clock_id);
+	ret = stm32mp_clk_enable(sdmmc2_params.clock_id);
 	if (ret != 0) {
 		ERROR("%s: clock %d failed\n", __func__,
 		      sdmmc2_params.clock_id);
 		return ret;
 	}
 
-	stm32mp1_reset_assert(sdmmc2_params.reset_id);
+	stm32mp_reset_assert(sdmmc2_params.reset_id);
 	udelay(2);
-	stm32mp1_reset_deassert(sdmmc2_params.reset_id);
+	stm32mp_reset_deassert(sdmmc2_params.reset_id);
 	mdelay(1);
 
-	sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id);
+	sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
 
 	return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
 			sdmmc2_params.bus_width, sdmmc2_params.flags,
diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 6beabc1..eb5c6e6 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -167,7 +167,7 @@
 		panic();
 	}
 
-	if (stm32mp1_clk_enable((uint32_t)i2c_info.clock) < 0) {
+	if (stm32mp_clk_enable((uint32_t)i2c_info.clock) < 0) {
 		ERROR("I2C clock enable failed\n");
 		panic();
 	}
diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c
index f58e10b..aac74e1 100644
--- a/drivers/st/reset/stm32mp1_reset.c
+++ b/drivers/st/reset/stm32mp1_reset.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,14 +10,14 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
 
 #define RST_CLR_OFFSET	4U
 
-void stm32mp1_reset_assert(uint32_t id)
+void stm32mp_reset_assert(uint32_t id)
 {
 	uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
 	uint32_t bit = id % (uint32_t)__LONG_BIT;
@@ -28,7 +28,7 @@
 	}
 }
 
-void stm32mp1_reset_deassert(uint32_t id)
+void stm32mp_reset_deassert(uint32_t id)
 {
 	uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
 			  RST_CLR_OFFSET;
diff --git a/include/drivers/st/stm32mp1_clk.h b/include/drivers/st/stm32mp1_clk.h
index 5594e23..11ff7bf 100644
--- a/include/drivers/st/stm32mp1_clk.h
+++ b/include/drivers/st/stm32mp1_clk.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,16 +7,10 @@
 #ifndef STM32MP1_CLK_H
 #define STM32MP1_CLK_H
 
-#include <stdbool.h>
-
 #include <arch_helpers.h>
 
 int stm32mp1_clk_probe(void);
 int stm32mp1_clk_init(void);
-bool stm32mp1_clk_is_enabled(unsigned long id);
-int stm32mp1_clk_enable(unsigned long id);
-int stm32mp1_clk_disable(unsigned long id);
-unsigned long stm32mp1_clk_get_rate(unsigned long id);
 void stm32mp1_stgen_increment(unsigned long long offset_in_ms);
 
 static inline uint32_t get_timer(uint32_t base)
diff --git a/include/drivers/st/stm32mp1_reset.h b/include/drivers/st/stm32mp1_reset.h
deleted file mode 100644
index cd488cc..0000000
--- a/include/drivers/st/stm32mp1_reset.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef STM32MP1_RESET_H
-#define STM32MP1_RESET_H
-
-#include <stdint.h>
-
-void stm32mp1_reset_assert(uint32_t reset_id);
-void stm32mp1_reset_deassert(uint32_t reset_id);
-
-#endif /* STM32MP1_RESET_H */
diff --git a/include/drivers/st/stm32mp_reset.h b/include/drivers/st/stm32mp_reset.h
new file mode 100644
index 0000000..2da5adf
--- /dev/null
+++ b/include/drivers/st/stm32mp_reset.h
@@ -0,0 +1,15 @@
+/*
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_RESET_H
+#define STM32MP_RESET_H
+
+#include <stdint.h>
+
+void stm32mp_reset_assert(uint32_t reset_id);
+void stm32mp_reset_deassert(uint32_t reset_id);
+
+#endif /* STM32MP_RESET_H */
diff --git a/plat/st/common/bl2_io_storage.c b/plat/st/common/bl2_io_storage.c
index 18342aa..5b649a3 100644
--- a/plat/st/common/bl2_io_storage.c
+++ b/plat/st/common/bl2_io_storage.c
@@ -57,12 +57,12 @@
 
 static const io_block_spec_t bl32_block_spec = {
 	.offset = BL32_BASE,
-	.length = STM32MP1_BL32_SIZE
+	.length = STM32MP_BL32_SIZE
 };
 
 static const io_block_spec_t bl2_block_spec = {
 	.offset = BL2_BASE,
-	.length = STM32MP1_BL2_SIZE,
+	.length = STM32MP_BL2_SIZE,
 };
 
 static const struct stm32image_part_info bl33_partition_spec = {
@@ -163,7 +163,7 @@
 	}
 }
 
-void stm32mp1_io_setup(void)
+void stm32mp_io_setup(void)
 {
 	int io_result __unused;
 	uint8_t idx;
@@ -173,7 +173,7 @@
 	uintptr_t mmc_default_instance;
 	const partition_entry_t *entry;
 	boot_api_context_t *boot_context =
-		(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
+		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 
 	print_boot_device(boot_context);
 
@@ -200,21 +200,21 @@
 		if (boot_context->boot_interface_selected ==
 		    BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) {
 			device_info.mmc_dev_type = MMC_IS_EMMC;
-			mmc_default_instance = STM32MP1_SDMMC2_BASE;
+			mmc_default_instance = STM32MP_SDMMC2_BASE;
 		} else {
 			device_info.mmc_dev_type = MMC_IS_SD;
-			mmc_default_instance = STM32MP1_SDMMC1_BASE;
+			mmc_default_instance = STM32MP_SDMMC1_BASE;
 		}
 
 		switch (boot_context->boot_interface_instance) {
 		case 1:
-			params.reg_base = STM32MP1_SDMMC1_BASE;
+			params.reg_base = STM32MP_SDMMC1_BASE;
 			break;
 		case 2:
-			params.reg_base = STM32MP1_SDMMC2_BASE;
+			params.reg_base = STM32MP_SDMMC2_BASE;
 			break;
 		case 3:
-			params.reg_base = STM32MP1_SDMMC3_BASE;
+			params.reg_base = STM32MP_SDMMC3_BASE;
 			break;
 		default:
 			WARN("SDMMC instance not found, using default\n");
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 11dd845..269d8ac 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -7,9 +7,11 @@
 #ifndef STM32MP_COMMON_H
 #define STM32MP_COMMON_H
 
+#include <stdbool.h>
+
 /* Functions to save and get boot context address given by ROM code */
-void stm32mp1_save_boot_ctx_address(uintptr_t address);
-uintptr_t stm32mp1_get_boot_ctx_address(void);
+void stm32mp_save_boot_ctx_address(uintptr_t address);
+uintptr_t stm32mp_get_boot_ctx_address(void);
 
 /*
  * Platform util functions for the GPIO driver
@@ -28,7 +30,16 @@
 unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
 uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
 
+/*
+ * Util for clock gating and to get clock rate for stm32 and platform drivers
+ * @id: Target clock ID, ID used in clock DT bindings
+ */
+bool stm32mp_clk_is_enabled(unsigned long id);
+int stm32mp_clk_enable(unsigned long id);
+int stm32mp_clk_disable(unsigned long id);
+unsigned long stm32mp_clk_get_rate(unsigned long id);
+
 /* Initialise the IO layer and register platform IO devices */
-void stm32mp1_io_setup(void);
+void stm32mp_io_setup(void);
 
 #endif /* STM32MP_COMMON_H */
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 7744aa0..20aa57d 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -25,12 +25,12 @@
 
 static uintptr_t boot_ctx_address;
 
-void stm32mp1_save_boot_ctx_address(uintptr_t address)
+void stm32mp_save_boot_ctx_address(uintptr_t address)
 {
 	boot_ctx_address = address;
 }
 
-uintptr_t stm32mp1_get_boot_ctx_address(void)
+uintptr_t stm32mp_get_boot_ctx_address(void)
 {
 	return boot_ctx_address;
 }
diff --git a/plat/st/common/stm32mp_dt.c b/plat/st/common/stm32mp_dt.c
index 2eaa9d9..0b6a0d3 100644
--- a/plat/st/common/stm32mp_dt.c
+++ b/plat/st/common/stm32mp_dt.c
@@ -21,7 +21,7 @@
 
 static int fdt_checked;
 
-static void *fdt = (void *)(uintptr_t)STM32MP1_DTB_BASE;
+static void *fdt = (void *)(uintptr_t)STM32MP_DTB_BASE;
 
 /*******************************************************************************
  * This function checks device tree file with its header.
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 5525efd..beea69a 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -17,11 +17,11 @@
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/stm32_console.h>
 #include <drivers/st/stm32mp_pmic.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_pwr.h>
 #include <drivers/st/stm32mp1_ram.h>
 #include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
@@ -120,7 +120,7 @@
 				  u_register_t arg2 __unused,
 				  u_register_t arg3 __unused)
 {
-	stm32mp1_save_boot_ctx_address(arg0);
+	stm32mp_save_boot_ctx_address(arg0);
 }
 
 void bl2_platform_setup(void)
@@ -146,7 +146,7 @@
 	struct dt_node_info dt_uart_info;
 	const char *board_model;
 	boot_api_context_t *boot_context =
-		(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
+		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 	uint32_t clk_rate;
 
 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
@@ -159,9 +159,9 @@
 			MT_MEMORY | MT_RO | MT_SECURE);
 
 	/* Map non secure DDR for BL33 load and DDR training area restore */
-	mmap_add_region(STM32MP1_DDR_BASE,
-			STM32MP1_DDR_BASE,
-			STM32MP1_DDR_MAX_SIZE,
+	mmap_add_region(STM32MP_DDR_BASE,
+			STM32MP_DDR_BASE,
+			STM32MP_DDR_MAX_SIZE,
 			MT_MEMORY | MT_RW | MT_NS);
 
 	/* Prevent corruption of preloaded Device Tree */
@@ -221,19 +221,19 @@
 		goto skip_console_init;
 	}
 
-	if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
+	if (stm32mp_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
 		goto skip_console_init;
 	}
 
-	stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
+	stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
 	udelay(2);
-	stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
+	stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
 	mdelay(1);
 
-	clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
+	clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
 
 	if (console_stm32_register(dt_uart_info.base, clk_rate,
-				   STM32MP1_UART_BAUDRATE, &console) == 0) {
+				   STM32MP_UART_BAUDRATE, &console) == 0) {
 		panic();
 	}
 
@@ -254,5 +254,5 @@
 
 	print_reset_reason();
 
-	stm32mp1_io_setup();
+	stm32mp_io_setup();
 }
diff --git a/plat/st/stm32mp1/include/platform_def.h b/plat/st/stm32mp1/include/platform_def.h
index 6d3d36d..5019b1a 100644
--- a/plat/st/stm32mp1/include/platform_def.h
+++ b/plat/st/stm32mp1/include/platform_def.h
@@ -29,8 +29,8 @@
 #define BL33_IMAGE_NAME			"ssbl"
 #define BL33_BINARY_TYPE		U(0x0)
 
-#define STM32MP1_PRIMARY_CPU		U(0x0)
-#define STM32MP1_SECONDARY_CPU		U(0x1)
+#define STM32MP_PRIMARY_CPU		U(0x0)
+#define STM32MP_SECONDARY_CPU		U(0x1)
 
 #define PLATFORM_CLUSTER_COUNT		ULL(1)
 #define PLATFORM_CLUSTER0_CORE_COUNT	U(2)
@@ -50,33 +50,33 @@
  * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
  * size plus a little space for growth.
  */
-#define BL2_BASE			STM32MP1_BL2_BASE
-#define BL2_LIMIT			(STM32MP1_BL2_BASE + \
-					 STM32MP1_BL2_SIZE)
+#define BL2_BASE			STM32MP_BL2_BASE
+#define BL2_LIMIT			(STM32MP_BL2_BASE + \
+					 STM32MP_BL2_SIZE)
 
 /*******************************************************************************
  * BL32 specific defines.
  ******************************************************************************/
-#define BL32_BASE			STM32MP1_BL32_BASE
-#define BL32_LIMIT			(STM32MP1_BL32_BASE + \
-					 STM32MP1_BL32_SIZE)
+#define BL32_BASE			STM32MP_BL32_BASE
+#define BL32_LIMIT			(STM32MP_BL32_BASE + \
+					 STM32MP_BL32_SIZE)
 
 /*******************************************************************************
  * BL33 specific defines.
  ******************************************************************************/
-#define BL33_BASE			STM32MP1_BL33_BASE
+#define BL33_BASE			STM32MP_BL33_BASE
 
 /*
  * Load address of BL33 for this platform port
  */
-#define PLAT_STM32MP1_NS_IMAGE_OFFSET	BL33_BASE
+#define PLAT_STM32MP_NS_IMAGE_OFFSET	BL33_BASE
 
 /*******************************************************************************
  * DTB specific defines.
  ******************************************************************************/
-#define DTB_BASE			STM32MP1_DTB_BASE
-#define DTB_LIMIT			(STM32MP1_DTB_BASE + \
-					 STM32MP1_DTB_SIZE)
+#define DTB_BASE			STM32MP_DTB_BASE
+#define DTB_LIMIT			(STM32MP_DTB_BASE + \
+					 STM32MP_DTB_SIZE)
 
 /*******************************************************************************
  * Platform specific page table and MMU setup constants
diff --git a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
index 6214194..0da93e4 100644
--- a/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
+++ b/plat/st/stm32mp1/plat_bl2_mem_params_desc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -50,7 +50,7 @@
 				      VERSION_2, entry_point_info_t,
 				      NON_SECURE | EXECUTABLE),
 
-		.ep_info.pc = PLAT_STM32MP1_NS_IMAGE_OFFSET,
+		.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
 		.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
 					    SPSR_E_LITTLE,
 					    DISABLE_ALL_EXCEPTIONS),
@@ -58,9 +58,9 @@
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
 
-		.image_info.image_base = PLAT_STM32MP1_NS_IMAGE_OFFSET,
-		.image_info.image_max_size = STM32MP1_DDR_MAX_SIZE -
-			(PLAT_STM32MP1_NS_IMAGE_OFFSET - STM32MP1_DDR_BASE),
+		.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
+		.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
+			(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	}
diff --git a/plat/st/stm32mp1/sp_min/sp_min_setup.c b/plat/st/stm32mp1/sp_min/sp_min_setup.c
index f747ee7..329ff68 100644
--- a/plat/st/stm32mp1/sp_min/sp_min_setup.c
+++ b/plat/st/stm32mp1/sp_min/sp_min_setup.c
@@ -123,7 +123,7 @@
 
 	if ((result > 0) && (dt_uart_info.status != 0U)) {
 		if (console_stm32_register(dt_uart_info.base, 0,
-					   STM32MP1_UART_BAUDRATE, &console) ==
+					   STM32MP_UART_BAUDRATE, &console) ==
 		    0) {
 			panic();
 		}
diff --git a/plat/st/stm32mp1/stm32mp1.ld.S b/plat/st/stm32mp1/stm32mp1.ld.S
index a8e8220..c041fb6 100644
--- a/plat/st/stm32mp1/stm32mp1.ld.S
+++ b/plat/st/stm32mp1/stm32mp1.ld.S
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,7 @@
 
 MEMORY {
 	HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000
-	RAM (rwx) : ORIGIN = STM32MP1_BINARY_BASE, LENGTH = STM32MP1_BINARY_SIZE
+	RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
 }
 
 SECTIONS
@@ -32,7 +32,7 @@
         __HEADER_END__ = .;
     } >HEADER
 
-    . = STM32MP1_BINARY_BASE;
+    . = STM32MP_BINARY_BASE;
     .data . : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
@@ -43,7 +43,7 @@
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP1_DTB_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -53,7 +53,7 @@
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP1_BL2_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)
         __BL2_IMAGE_END__ = .;
@@ -63,7 +63,7 @@
          * The strongest and only alignment constraint is 8 words to simplify
          * memraise8 assembly code.
          */
-        . = ( STM32MP1_BL32_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE );
         __BL32_IMAGE_START__ = .;
         *(.bl32_image*)
         __BL32_IMAGE_END__ = .;
diff --git a/plat/st/stm32mp1/stm32mp1_context.c b/plat/st/stm32mp1/stm32mp1_context.c
index a8f9bf4..c402c20 100644
--- a/plat/st/stm32mp1/stm32mp1_context.c
+++ b/plat/st/stm32mp1/stm32mp1_context.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -23,9 +23,9 @@
 	uint32_t tamp_clk_off = 0;
 	uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
+	if (!stm32mp_clk_is_enabled(RTCAPB)) {
 		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
+		if (stm32mp_clk_enable(RTCAPB) != 0) {
 			return -EINVAL;
 		}
 	}
@@ -36,7 +36,7 @@
 			   TAMP_BOOT_ITF_SHIFT);
 
 	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
+		if (stm32mp_clk_disable(RTCAPB) != 0) {
 			return -EINVAL;
 		}
 	}
diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index d12a93f..a456f26 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -22,14 +22,13 @@
  * STM32MP1 memory map related constants
  ******************************************************************************/
 
-#define STM32MP1_SRAM_BASE		U(0x2FFC0000)
-#define STM32MP1_SRAM_SIZE		U(0x00040000)
+#define STM32MP_SYSRAM_BASE		U(0x2FFC0000)
+#define STM32MP_SYSRAM_SIZE		U(0x00040000)
 
 /* DDR configuration */
-#define STM32MP1_DDR_BASE		U(0xC0000000)
-#define STM32MP1_DDR_SIZE_DFLT		U(0x20000000)	/* 512 MB */
-#define STM32MP1_DDR_MAX_SIZE		U(0x40000000)	/* Max 1GB */
-#define STM32MP1_DDR_SPEED_DFLT		528
+#define STM32MP_DDR_BASE		U(0xC0000000)
+#define STM32MP_DDR_MAX_SIZE		U(0x40000000)	/* Max 1GB */
+#define STM32MP_DDR_SPEED_DFLT		528
 
 /* DDR power initializations */
 #ifndef __ASSEMBLY__
@@ -40,36 +39,36 @@
 #endif
 
 /* Section used inside TF binaries */
-#define STM32MP1_PARAM_LOAD_SIZE	U(0x00002400)	/* 9 Ko for param */
+#define STM32MP_PARAM_LOAD_SIZE		U(0x00002400)	/* 9 Ko for param */
 /* 256 Octets reserved for header */
-#define STM32MP1_HEADER_SIZE		U(0x00000100)
+#define STM32MP_HEADER_SIZE		U(0x00000100)
 
-#define STM32MP1_BINARY_BASE		(STM32MP1_SRAM_BASE +		\
-					 STM32MP1_PARAM_LOAD_SIZE +	\
-					 STM32MP1_HEADER_SIZE)
+#define STM32MP_BINARY_BASE		(STM32MP_SYSRAM_BASE +		\
+					 STM32MP_PARAM_LOAD_SIZE +	\
+					 STM32MP_HEADER_SIZE)
 
-#define STM32MP1_BINARY_SIZE		(STM32MP1_SRAM_SIZE -		\
-					 (STM32MP1_PARAM_LOAD_SIZE +	\
-					  STM32MP1_HEADER_SIZE))
+#define STM32MP_BINARY_SIZE		(STM32MP_SYSRAM_SIZE -		\
+					 (STM32MP_PARAM_LOAD_SIZE +	\
+					  STM32MP_HEADER_SIZE))
 
 #if STACK_PROTECTOR_ENABLED
-#define STM32MP1_BL32_SIZE		U(0x00012000)	/* 72 Ko for BL32 */
+#define STM32MP_BL32_SIZE		U(0x00012000)	/* 72 Ko for BL32 */
 #else
-#define STM32MP1_BL32_SIZE		U(0x00011000)	/* 68 Ko for BL32 */
+#define STM32MP_BL32_SIZE		U(0x00011000)	/* 68 Ko for BL32 */
 #endif
 
-#define STM32MP1_BL32_BASE		(STM32MP1_SRAM_BASE + \
-					 STM32MP1_SRAM_SIZE - \
-					 STM32MP1_BL32_SIZE)
+#define STM32MP_BL32_BASE		(STM32MP_SYSRAM_BASE + \
+					 STM32MP_SYSRAM_SIZE - \
+					 STM32MP_BL32_SIZE)
 
 #if STACK_PROTECTOR_ENABLED
-#define STM32MP1_BL2_SIZE		U(0x00015000)	/* 84 Ko for BL2 */
+#define STM32MP_BL2_SIZE		U(0x00015000)	/* 84 Ko for BL2 */
 #else
-#define STM32MP1_BL2_SIZE		U(0x00013000)	/* 76 Ko for BL2 */
+#define STM32MP_BL2_SIZE		U(0x00013000)	/* 76 Ko for BL2 */
 #endif
 
-#define STM32MP1_BL2_BASE		(STM32MP1_BL32_BASE - \
-					 STM32MP1_BL2_SIZE)
+#define STM32MP_BL2_BASE		(STM32MP_BL32_BASE - \
+					 STM32MP_BL2_SIZE)
 
 /* BL2 and BL32/sp_min require 5 tables */
 #define MAX_XLAT_TABLES			5
@@ -86,12 +85,12 @@
 #endif
 
 /* DTB initialization value */
-#define STM32MP1_DTB_SIZE		U(0x00004000)	/* 16Ko for DTB */
+#define STM32MP_DTB_SIZE		U(0x00004000)	/* 16Ko for DTB */
 
-#define STM32MP1_DTB_BASE		(STM32MP1_BL2_BASE - \
-					 STM32MP1_DTB_SIZE)
+#define STM32MP_DTB_BASE		(STM32MP_BL2_BASE - \
+					 STM32MP_DTB_SIZE)
 
-#define STM32MP1_BL33_BASE		(STM32MP1_DDR_BASE + U(0x100000))
+#define STM32MP_BL33_BASE		(STM32MP_DDR_BASE + U(0x100000))
 
 /*******************************************************************************
  * STM32MP1 device/io map related constants (used for MMU)
@@ -156,12 +155,12 @@
 #define USART6_BASE			U(0x44003000)
 #define UART7_BASE			U(0x40018000)
 #define UART8_BASE			U(0x40019000)
-#define STM32MP1_UART_BAUDRATE		U(115200)
+#define STM32MP_UART_BAUDRATE		U(115200)
 
 /* For UART crash console */
-#define STM32MP1_DEBUG_USART_BASE	UART4_BASE
+#define STM32MP_DEBUG_USART_BASE	UART4_BASE
 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
-#define STM32MP1_DEBUG_USART_CLK_FRQ	64000000
+#define STM32MP_DEBUG_USART_CLK_FRQ	64000000
 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS	GPIOG_BASE
 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG	RCC_MP_AHB4ENSETR
 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN	RCC_MP_AHB4ENSETR_GPIOGEN
@@ -193,15 +192,15 @@
 /*******************************************************************************
  * STM32MP1 SDMMC
  ******************************************************************************/
-#define STM32MP1_SDMMC1_BASE		U(0x58005000)
-#define STM32MP1_SDMMC2_BASE		U(0x58007000)
-#define STM32MP1_SDMMC3_BASE		U(0x48004000)
+#define STM32MP_SDMMC1_BASE		U(0x58005000)
+#define STM32MP_SDMMC2_BASE		U(0x58007000)
+#define STM32MP_SDMMC3_BASE		U(0x48004000)
 
-#define STM32MP1_MMC_INIT_FREQ			400000		/*400 KHz*/
-#define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ	25000000	/*25 MHz*/
-#define STM32MP1_SD_HIGH_SPEED_MAX_FREQ		50000000	/*50 MHz*/
-#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ	26000000	/*26 MHz*/
-#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ	52000000	/*52 MHz*/
+#define STM32MP_MMC_INIT_FREQ			400000		/*400 KHz*/
+#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ	25000000	/*25 MHz*/
+#define STM32MP_SD_HIGH_SPEED_MAX_FREQ		50000000	/*50 MHz*/
+#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ	26000000	/*26 MHz*/
+#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ	52000000	/*52 MHz*/
 
 /*******************************************************************************
  * STM32MP1 BSEC / OTP
diff --git a/plat/st/stm32mp1/stm32mp1_helper.S b/plat/st/stm32mp1/stm32mp1_helper.S
index 8c2e1b6..c675965 100644
--- a/plat/st/stm32mp1/stm32mp1_helper.S
+++ b/plat/st/stm32mp1/stm32mp1_helper.S
@@ -74,7 +74,7 @@
 	ldcopr	r0, MPIDR
 	ldr	r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
 	and	r0, r1
-	cmp	r0, #STM32MP1_PRIMARY_CPU
+	cmp	r0, #STM32MP_PRIMARY_CPU
 	moveq	r0, #1
 	movne	r0, #0
 	bx	lr
@@ -143,9 +143,9 @@
 	orr	r2, r2, #DEBUG_UART_TX_EN
 	str	r2, [r1]
 
-	ldr	r0, =STM32MP1_DEBUG_USART_BASE
-	ldr	r1, =STM32MP1_DEBUG_USART_CLK_FRQ
-	ldr	r2, =STM32MP1_UART_BAUDRATE
+	ldr	r0, =STM32MP_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_CLK_FRQ
+	ldr	r2, =STM32MP_UART_BAUDRATE
 	b	console_stm32_core_init
 endfunc plat_crash_console_init
 
@@ -156,7 +156,7 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_flush
-	ldr	r1, =STM32MP1_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_BASE
 	b	console_stm32_core_flush
 endfunc plat_crash_console_flush
 
@@ -172,6 +172,6 @@
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	ldr	r1, =STM32MP1_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_BASE
 	b	console_stm32_core_putc
 endfunc plat_crash_console_putc
diff --git a/plat/st/stm32mp1/stm32mp1_pm.c b/plat/st/stm32mp1/stm32mp1_pm.c
index 20f66e9..18921ef 100644
--- a/plat/st/stm32mp1/stm32mp1_pm.c
+++ b/plat/st/stm32mp1/stm32mp1_pm.c
@@ -70,15 +70,15 @@
 		return PSCI_E_INVALID_PARAMS;
 	}
 
-	if ((stm32_sec_entrypoint < STM32MP1_SRAM_BASE) ||
-	    (stm32_sec_entrypoint > (STM32MP1_SRAM_BASE +
-				     (STM32MP1_SRAM_SIZE - 1)))) {
+	if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) ||
+	    (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE +
+				     (STM32MP_SYSRAM_SIZE - 1)))) {
 		return PSCI_E_INVALID_ADDRESS;
 	}
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
+	if (!stm32mp_clk_is_enabled(RTCAPB)) {
 		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
+		if (stm32mp_clk_enable(RTCAPB) != 0) {
 			panic();
 		}
 	}
@@ -92,13 +92,13 @@
 	mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
 
 	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
+		if (stm32mp_clk_disable(RTCAPB) != 0) {
 			panic();
 		}
 	}
 
 	/* Generate an IT to core 1 */
-	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP1_SECONDARY_CPU);
+	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);
 
 	return PSCI_E_SUCCESS;
 }
@@ -194,7 +194,7 @@
 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
 {
 	/* The non-secure entry point must be in DDR */
-	if (entrypoint < STM32MP1_DDR_BASE) {
+	if (entrypoint < STM32MP_DDR_BASE) {
 		return PSCI_E_INVALID_ADDRESS;
 	}
 
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index f3beb59..20eb88e 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -8,8 +8,8 @@
 
 #include <lib/xlat_tables/xlat_tables_v2.h>
 
-#define MAP_SRAM	MAP_REGION_FLAT(STM32MP1_SRAM_BASE, \
-					STM32MP1_SRAM_SIZE, \
+#define MAP_SRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
+					STM32MP_SYSRAM_SIZE, \
 					MT_MEMORY | \
 					MT_RW | \
 					MT_SECURE | \
diff --git a/plat/st/stm32mp1/stm32mp1_security.c b/plat/st/stm32mp1/stm32mp1_security.c
index 99719e4..bb66b4b 100644
--- a/plat/st/stm32mp1/stm32mp1_security.c
+++ b/plat/st/stm32mp1/stm32mp1_security.c
@@ -22,7 +22,7 @@
 static void init_tzc400(void)
 {
 	unsigned long long region_base, region_top;
-	unsigned long long ddr_base = STM32MP1_DDR_BASE;
+	unsigned long long ddr_base = STM32MP_DDR_BASE;
 	unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
 
 	tzc400_init(STM32MP1_TZC_BASE);
@@ -62,11 +62,11 @@
  ******************************************************************************/
 static void early_init_tzc400(void)
 {
-	if (stm32mp1_clk_enable(TZC1) != 0) {
+	if (stm32mp_clk_enable(TZC1) != 0) {
 		ERROR("Cannot enable TZC1 clock\n");
 		panic();
 	}
-	if (stm32mp1_clk_enable(TZC2) != 0) {
+	if (stm32mp_clk_enable(TZC2) != 0) {
 		ERROR("Cannot enable TZC2 clock\n");
 		panic();
 	}
@@ -80,9 +80,9 @@
 	 * same configuration to all filters in the TZC.
 	 */
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
-				STM32MP1_DDR_BASE,
-				STM32MP1_DDR_BASE +
-				(STM32MP1_DDR_MAX_SIZE - 1U),
+				STM32MP_DDR_BASE,
+				STM32MP_DDR_BASE +
+				(STM32MP_DDR_MAX_SIZE - 1U),
 				TZC_REGION_S_RDWR,
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));