mediatek: mt8195: initialize GIC
MT8192 GIC driver can be shared with MT8195. Move GIC driver to common
and do the initialization.
Signed-off-by: christine.zhu <christine.zhu@mediatek.corp-partner.google.com>
Change-Id: I63f3e668b5ca6df8bcf17b5cd4d53fa84f330fed
diff --git a/plat/mediatek/mt8192/include/mt_gic_v3.h b/plat/mediatek/mt8192/include/mt_gic_v3.h
deleted file mode 100644
index c4ab44f..0000000
--- a/plat/mediatek/mt8192/include/mt_gic_v3.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef MT_GIC_V3_H
-#define MT_GIC_V3_H
-
-#include <drivers/arm/gicv3.h>
-#include <lib/mmio.h>
-
-void mt_gic_driver_init(void);
-void mt_gic_init(void);
-void mt_gic_set_pending(uint32_t irq);
-void mt_gic_distif_save(void);
-void mt_gic_distif_restore(void);
-void mt_gic_rdistif_init(void);
-void mt_gic_rdistif_save(void);
-void mt_gic_rdistif_restore(void);
-void mt_gic_rdistif_restore_all(void);
-void gic_sgi_save_all(void);
-void gic_sgi_restore_all(void);
-uint32_t mt_irq_get_pending(uint32_t irq);
-void mt_irq_set_pending(uint32_t irq);
-
-#endif /* MT_GIC_V3_H */
diff --git a/plat/mediatek/mt8192/include/platform_def.h b/plat/mediatek/mt8192/include/platform_def.h
index 540463d..2468dd6 100644
--- a/plat/mediatek/mt8192/include/platform_def.h
+++ b/plat/mediatek/mt8192/include/platform_def.h
@@ -61,7 +61,7 @@
#define SYS_COUNTER_FREQ_IN_MHZ 13
/*******************************************************************************
- * GIC-400 & interrupt handling related constants
+ * GIC-600 & interrupt handling related constants
******************************************************************************/
/* Base MTK_platform compatible GIC memory map */
diff --git a/plat/mediatek/mt8192/plat_mt_gic.c b/plat/mediatek/mt8192/plat_mt_gic.c
deleted file mode 100644
index ae8d697..0000000
--- a/plat/mediatek/mt8192/plat_mt_gic.c
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- * Copyright (c) 2020, MediaTek Inc. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-#include <stdint.h>
-#include <stdio.h>
-
-#include "../drivers/arm/gic/v3/gicv3_private.h"
-#include <bl31/interrupt_mgmt.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-
-#include <mt_gic_v3.h>
-#include <mtk_plat_common.h>
-#include <plat/common/platform.h>
-#include <plat_private.h>
-#include <platform_def.h>
-
-#define SGI_MASK 0xffff
-
-uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
-static uint32_t rdist_has_saved[PLATFORM_CORE_COUNT];
-
-/* we save and restore the GICv3 context on system suspend */
-gicv3_dist_ctx_t dist_ctx;
-
-static unsigned int mt_mpidr_to_core_pos(u_register_t mpidr)
-{
- return plat_core_pos_by_mpidr(mpidr);
-}
-
-gicv3_driver_data_t mt_gicv3_data = {
- .gicd_base = MT_GIC_BASE,
- .gicr_base = MT_GIC_RDIST_BASE,
- .rdistif_num = PLATFORM_CORE_COUNT,
- .rdistif_base_addrs = rdistif_base_addrs,
- .mpidr_to_core_pos = mt_mpidr_to_core_pos,
-};
-
-struct gic_chip_data {
- /* All cores share the same configuration */
- unsigned int saved_group;
- unsigned int saved_enable;
- unsigned int saved_conf0;
- unsigned int saved_conf1;
- unsigned int saved_grpmod;
- /* Per-core sgi */
- unsigned int saved_sgi[PLATFORM_CORE_COUNT];
-};
-
-static struct gic_chip_data gic_data;
-
-void mt_gic_driver_init(void)
-{
- gicv3_driver_init(&mt_gicv3_data);
-}
-
-void mt_gic_set_pending(uint32_t irq)
-{
- gicv3_set_interrupt_pending(irq, plat_my_core_pos());
-}
-
-void mt_gic_distif_save(void)
-{
- gicv3_distif_save(&dist_ctx);
-}
-
-void mt_gic_distif_restore(void)
-{
- gicv3_distif_init_restore(&dist_ctx);
-}
-
-void mt_gic_rdistif_init(void)
-{
- unsigned int proc_num;
- unsigned int index;
- uintptr_t gicr_base;
-
- proc_num = plat_my_core_pos();
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
-
- /* set all SGI/PPI as non-secure GROUP1 by default */
- mmio_write_32(gicr_base + GICR_IGROUPR0, ~0U);
- mmio_write_32(gicr_base + GICR_IGRPMODR0, 0x0);
-
- /* setup the default PPI/SGI priorities */
- for (index = 0; index < TOTAL_PCPU_INTR_NUM; index += 4U)
- gicr_write_ipriorityr(gicr_base, index,
- GICD_IPRIORITYR_DEF_VAL);
-}
-
-void mt_gic_rdistif_save(void)
-{
- unsigned int proc_num;
- uintptr_t gicr_base;
-
- proc_num = plat_my_core_pos();
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
-
- gic_data.saved_group = mmio_read_32(gicr_base + GICR_IGROUPR0);
- gic_data.saved_enable = mmio_read_32(gicr_base + GICR_ISENABLER0);
- gic_data.saved_conf0 = mmio_read_32(gicr_base + GICR_ICFGR0);
- gic_data.saved_conf1 = mmio_read_32(gicr_base + GICR_ICFGR1);
- gic_data.saved_grpmod = mmio_read_32(gicr_base + GICR_IGRPMODR0);
-
- rdist_has_saved[proc_num] = 1;
-}
-
-void mt_gic_rdistif_restore(void)
-{
- unsigned int proc_num;
- uintptr_t gicr_base;
-
- proc_num = plat_my_core_pos();
- if (rdist_has_saved[proc_num] == 1) {
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
- mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
- mmio_write_32(gicr_base + GICR_ISENABLER0,
- gic_data.saved_enable);
- mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
- mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
- mmio_write_32(gicr_base + GICR_IGRPMODR0,
- gic_data.saved_grpmod);
- }
-}
-
-void mt_gic_rdistif_restore_all(void)
-{
- unsigned int proc_num;
- uintptr_t gicr_base;
-
- for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
- mmio_write_32(gicr_base + GICR_IGROUPR0, gic_data.saved_group);
- mmio_write_32(gicr_base + GICR_ISENABLER0,
- gic_data.saved_enable);
- mmio_write_32(gicr_base + GICR_ICFGR0, gic_data.saved_conf0);
- mmio_write_32(gicr_base + GICR_ICFGR1, gic_data.saved_conf1);
- mmio_write_32(gicr_base + GICR_IGRPMODR0,
- gic_data.saved_grpmod);
- }
-}
-
-void gic_sgi_save_all(void)
-{
- unsigned int proc_num;
- uintptr_t gicr_base;
-
- for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
- gic_data.saved_sgi[proc_num] =
- mmio_read_32(gicr_base + GICR_ISPENDR0) & SGI_MASK;
- }
-}
-
-void gic_sgi_restore_all(void)
-{
- unsigned int proc_num;
- uintptr_t gicr_base;
-
- for (proc_num = 0; proc_num < PLATFORM_CORE_COUNT; proc_num++) {
- gicr_base = gicv3_driver_data->rdistif_base_addrs[proc_num];
- mmio_write_32(gicr_base + GICR_ICPENDR0, SGI_MASK);
- mmio_write_32(gicr_base + GICR_ISPENDR0,
- gic_data.saved_sgi[proc_num] & SGI_MASK);
- }
-}
-
-void mt_gic_init(void)
-{
- gicv3_distif_init();
- gicv3_rdistif_init(plat_my_core_pos());
- gicv3_cpuif_enable(plat_my_core_pos());
-}
-
-uint32_t mt_irq_get_pending(uint32_t irq)
-{
- uint32_t val;
-
- val = mmio_read_32(BASE_GICD_BASE + GICD_ISPENDR +
- irq / 32 * 4);
- val = (val >> (irq % 32)) & 1U;
- return val;
-}
-
-
-void mt_irq_set_pending(uint32_t irq)
-{
- uint32_t bit = 1U << (irq % 32);
-
- mmio_write_32(BASE_GICD_BASE + GICD_ISPENDR +
- irq / 32 * 4, bit);
-}
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index e45f649..109dac0 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -8,7 +8,8 @@
MTK_PLAT_SOC := ${MTK_PLAT}/${PLAT}
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
- -I${MTK_PLAT}/common/drivers/uart/ \
+ -I${MTK_PLAT}/common/drivers/gic600/ \
+ -I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
@@ -40,6 +41,7 @@
lib/cpus/aarch64/cortex_a55.S \
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_gicv3.c \
+ ${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
${MTK_PLAT}/common/drivers/uart/uart.c \
@@ -54,7 +56,6 @@
${MTK_PLAT_SOC}/drivers/rtc/rtc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_topology.c \
- ${MTK_PLAT_SOC}/plat_mt_gic.c \
${MTK_PLAT_SOC}/plat_mt_cirq.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \