zynqmp: pm_service: Add support for writing to AFI registers
Add support for writing to AFI registers.
So that after writing a bitstream the interface can be programmed.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com>
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
index 6f60e47..32c7357 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.c
@@ -453,6 +453,48 @@
}
/**
+ * pm_ioctl_afi() - Ioctl function for writing afi values
+ *
+ * @index AFI register index
+ * @value Register value to be written
+ *
+ *
+ * @return Returns status, either success or error+reason
+ */
+static enum pm_ret_status pm_ioctl_afi(unsigned int index,
+ unsigned int value)
+{
+ unsigned int mask;
+ unsigned int regarr[] = {0xFD360000,
+ 0xFD360014,
+ 0xFD370000,
+ 0xFD370014,
+ 0xFD380000,
+ 0xFD380014,
+ 0xFD390000,
+ 0xFD390014,
+ 0xFD3a0000,
+ 0xFD3a0014,
+ 0xFD3b0000,
+ 0xFD3b0014,
+ 0xFF9b0000,
+ 0xFF9b0014,
+ 0xFD615000,
+ 0xFF419000,
+ };
+
+ if (index >= ARRAY_SIZE(regarr))
+ return PM_RET_ERROR_ARGS;
+
+ if (index < AFIFM6_WRCTRL)
+ mask = FABRIC_WIDTH;
+ else
+ mask = 0xf00;
+
+ return pm_mmio_write(regarr[index], mask, value);
+}
+
+/**
* pm_ioctl_read_pggs() - Ioctl function for reading persistent
* global general storage (pggs)
* @index PGGS register index
@@ -594,6 +636,9 @@
case IOCTL_SET_BOOT_HEALTH_STATUS:
ret = pm_ioctl_set_boot_health_status(arg1);
break;
+ case IOCTL_AFI:
+ ret = pm_ioctl_afi(arg1, arg2);
+ break;
default:
ret = PM_RET_ERROR_NOTSUPPORTED;
break;
diff --git a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
index 29cd96e..d68c5e3 100644
--- a/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
+++ b/plat/xilinx/zynqmp/pm_service/pm_api_ioctl.h
@@ -36,6 +36,7 @@
IOCTL_ULPI_RESET,
/* Set healthy bit value */
IOCTL_SET_BOOT_HEALTH_STATUS,
+ IOCTL_AFI,
};
//RPU operation mode
diff --git a/plat/xilinx/zynqmp/zynqmp_def.h b/plat/xilinx/zynqmp/zynqmp_def.h
index bfd6197..8bd75e4 100644
--- a/plat/xilinx/zynqmp/zynqmp_def.h
+++ b/plat/xilinx/zynqmp/zynqmp_def.h
@@ -339,4 +339,8 @@
#define PM_BOOT_HEALTH_STATUS_REG (GGS_BASEADDR + U(0x10))
#define PM_BOOT_HEALTH_STATUS_MASK U(0x01)
+/*AFI registers */
+#define AFIFM6_WRCTRL U(13)
+#define FABRIC_WIDTH U(3)
+
#endif /* __ZYNQMP_DEF_H__ */