commit a1ad9b7676b147a6dc0c7c5013729f1a37aae667
author kalyani chidambaram <kalyanic@nvidia.com> Tue Mar 06 16:36:57 2018 -0800
committer Varun Wadekar <vwadekar@nvidia.com> Thu Jan 31 08:49:05 2019 -0800
tree 25688cec02df99004daeaadc8537103bcb364eaf
parent dae2796a3deb6c91b299ab646812f1c09b8dc73b

Tegra210: SiP handlers to allow PMC access

This patch adds SiP handler for Tegra210 platforms to service
read/write requests for PMC block. None of the secure registers
are accessible to the NS world though.

Change-Id: I7dc1f10c6a6ee6efc642ddcfb1170fb36d3accff
Signed-off-by: kalyani chidambaram <kalyanic@nvidia.com>

plat/nvidia/tegra/include/t210/tegra_def.h

diff --git a/plat/nvidia/tegra/include/t210/tegra_def.h b/plat/nvidia/tegra/include/t210/tegra_def.h
index eed443d..0f24f32 100644
--- a/plat/nvidia/tegra/include/t210/tegra_def.h
+++ b/plat/nvidia/tegra/include/t210/tegra_def.h
@@ -196,6 +196,7 @@
  * Tegra Power Mgmt Controller constants
  ******************************************************************************/
 #define TEGRA_PMC_BASE			U(0x7000E400)
+#define TEGRA_PMC_SIZE			U(0xC00) /* 3k */
 
 /*******************************************************************************
  * Tegra Atomics constants