fix(intel): update Agilex5 warm reset subroutines
Update the 'plat_get_my_entrypoint' assembly routine to
differentiate between cold reset, warm reset and SMP
secondary boot cores request.
Add secondary core boot request markup in BL31.
Perform CACHE flush/clean ops in case of warm reset request also.
Change-Id: I7d33e362a3a513c60c8333e062ce832aa7facf38
Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
Signed-off-by: Sieu Mun Tang <sieu.mun.tang@intel.com>
diff --git a/plat/intel/soc/common/aarch64/plat_helpers.S b/plat/intel/soc/common/aarch64/plat_helpers.S
index 9a17587..b3d5665 100644
--- a/plat/intel/soc/common/aarch64/plat_helpers.S
+++ b/plat/intel/soc/common/aarch64/plat_helpers.S
@@ -98,18 +98,6 @@
endfunc plat_my_core_pos
func warm_reset_req
-#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
- bl plat_is_my_cpu_primary
- cbnz x0, warm_reset
-warm_reset:
- mov_imm x1, PLAT_SEC_ENTRY
- str xzr, [x1]
- mrs x1, rmr_el3
- orr x1, x1, #0x02
- msr rmr_el3, x1
- isb
- dsb sy
-#else
str xzr, [x4]
bl plat_is_my_cpu_primary
cbz x0, cpu_in_wfi
@@ -123,22 +111,35 @@
cpu_in_wfi:
wfi
b cpu_in_wfi
-#endif
endfunc warm_reset_req
-/* TODO: Zephyr warm reset test */
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5
func plat_get_my_entrypoint
ldr x4, =L2_RESET_DONE_REG
ldr x5, [x4]
- ldr x1, =PLAT_L2_RESET_REQ
+
+ /* Check for warm reset request */
+ ldr x1, =L2_RESET_DONE_STATUS
+ cmp x1, x5
+ b.eq warm_reset_req
+
+ /* Check for SMP secondary cores boot request */
+ ldr x1, =SMP_SEC_CORE_BOOT_REQ
cmp x1, x5
- b.eq zephyr_reset_req
+ b.eq smp_request
+
+ /* Otherwise it is cold reset */
+ mov x0, #0
+ ret
+smp_request:
+ /*
+ * Return the address 'bl31_warm_entrypoint', which is passed to
+ * 'psci_setup' routine as part of BL31 initialization.
+ */
mov_imm x1, PLAT_SEC_ENTRY
ldr x0, [x1]
- ret
-zephyr_reset_req:
- ldr x0, =0x00
+ /* Clear the mark up before return */
+ str xzr, [x4]
ret
endfunc plat_get_my_entrypoint
#else