Fix MISRA defects in workaround and errata framework
No functional changes.
Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0
Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
diff --git a/include/lib/cpus/aarch64/cortex_a75.h b/include/lib/cpus/aarch64/cortex_a75.h
index 493c7d4..f68f98f 100644
--- a/include/lib/cpus/aarch64/cortex_a75.h
+++ b/include/lib/cpus/aarch64/cortex_a75.h
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CORTEX_A75_H__
-#define __CORTEX_A75_H__
+#ifndef CORTEX_A75_H
+#define CORTEX_A75_H
+
+#include <utils_def.h>
/* Cortex-A75 MIDR */
-#define CORTEX_A75_MIDR 0x410fd0a0
+#define CORTEX_A75_MIDR U(0x410fd0a0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -24,7 +26,7 @@
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35)
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
-#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_A75_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
@@ -50,4 +52,4 @@
void cortex_a75_amu_write_cpuamcntenclr_el0(unsigned int mask);
#endif /* __ASSEMBLY__ */
-#endif /* __CORTEX_A75_H__ */
+#endif /* CORTEX_A75_H */
diff --git a/include/lib/cpus/aarch64/cortex_ares.h b/include/lib/cpus/aarch64/cortex_ares.h
index 84955b1..4f3e812 100644
--- a/include/lib/cpus/aarch64/cortex_ares.h
+++ b/include/lib/cpus/aarch64/cortex_ares.h
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#ifndef __CORTEX_ARES_H__
-#define __CORTEX_ARES_H__
+#ifndef CORTEX_ARES_H
+#define CORTEX_ARES_H
+
+#include <utils_def.h>
/* Cortex-ARES MIDR for revision 0 */
-#define CORTEX_ARES_MIDR 0x410fd0c0
+#define CORTEX_ARES_MIDR U(0x410fd0c0)
/*******************************************************************************
* CPU Extended Control register specific definitions.
@@ -17,7 +19,7 @@
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
-#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
+#define CORTEX_ARES_CORE_PWRDN_EN_MASK U(0x1)
#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
@@ -30,4 +32,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
-#endif /* __CORTEX_ARES_H__ */
+#endif /* CORTEX_ARES_H */