| commit | 9fd242b7b5c0321dd4b71b69cf5083e75eb980b4 | [log] [tgz] |
|---|---|---|
| author | Manish V Badarkhe <manish.badarkhe@arm.com> | Mon Aug 19 11:56:49 2024 +0200 |
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | Mon Aug 19 11:56:49 2024 +0200 |
| tree | dcb5c4a32028ecf0c2aada17b27d6648134dedb1 | |
| parent | 36683362931c5e56bbeee49285dca9bed3c12ab9 [diff] | |
| parent | da8231b6ad93dc20f59bdaeb42bfae449c57de9c [diff] |
Merge changes from topic "ar/asymmetricSupport" into integration * changes: feat(tc): enable trbe errata flags for Cortex-A520 and X4 feat(cm): asymmetric feature support for trbe refactor(errata-abi): move EXTRACT_PARTNUM to arch.h feat(cpus): workaround for Cortex-A520(2938996) and Cortex-X4(2726228) feat(tc): make SPE feature asymmetric feat(cm): handle asymmetry for SPE feature feat(cm): support for asymmetric feature among cores feat(cpufeat): add new feature state for asymmetric features