fix(aarch64): make AArch64 FGT feature detection more robust
The ARMv8 ARM says about the values in the ID register scheme:
==== D17.1.3 Principles of the ID scheme for fields in ID registers ===
The ID fields, which are either signed or unsigned, use increasing
numerical values to indicate increases in functionality. Therefore,
if a value of 0x1 indicates the presence of some instructions, then
the value 0x2 will indicate the presence of those instructions plus
some additional instructions or functionality. This means software
can be written in the form:
if (value >= number) {
// do something that relies on the value of the feature
}
=======================================================================
So to check for the presence of a certain architecture feature, we
should not check against a certain specific value, as it's done right
now in several cases.
Relax the test for Fine Grained Trapping (FGT) to just check against
the field being 0 or not.
This fixes TF-A crashing due to an unhandled exception, when running a
Linux kernel on an FVP enabling ARMv8.9 features. The value of
ID_AA64MMFR0_EL1.FGT went from 0b0001 to 0b0010 there.
Change-Id: Ic3f1625a7650306ed388a0660429ca8823c673c2
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/include/arch/aarch64/arch_features.h b/include/arch/aarch64/arch_features.h
index 9ec114c..932e885 100644
--- a/include/arch/aarch64/arch_features.h
+++ b/include/arch/aarch64/arch_features.h
@@ -100,7 +100,7 @@
static inline bool is_armv8_6_fgt_present(void)
{
return ((read_id_aa64mmfr0_el1() >> ID_AA64MMFR0_EL1_FGT_SHIFT) &
- ID_AA64MMFR0_EL1_FGT_MASK) == ID_AA64MMFR0_EL1_FGT_SUPPORTED;
+ ID_AA64MMFR0_EL1_FGT_MASK) != 0U;
}
static inline unsigned long int get_armv8_6_ecv_support(void)