Tegra: support for native GICv2 drivers
This patch converts Tegra platforms to support native
GICv2 drivers. This involves removes Tegra's GIC driver
port platforms to use interrupt_props
Change-Id: I83d8a690ff276dd97928dc60824a4fd36999bb30
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
diff --git a/plat/nvidia/tegra/include/drivers/tegra_gic.h b/plat/nvidia/tegra/include/drivers/tegra_gic.h
new file mode 100644
index 0000000..2fe316d
--- /dev/null
+++ b/plat/nvidia/tegra/include/drivers/tegra_gic.h
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __TEGRA_GIC_H__
+#define __TEGRA_GIC_H__
+
+#include <interrupt_props.h>
+
+/*******************************************************************************
+ * Per-CPU struct describing FIQ state to be stored
+ ******************************************************************************/
+typedef struct pcpu_fiq_state {
+ uint64_t elr_el3;
+ uint64_t spsr_el3;
+} pcpu_fiq_state_t;
+
+/*******************************************************************************
+ * Fucntion declarations
+ ******************************************************************************/
+void tegra_gic_cpuif_deactivate(void);
+void tegra_gic_init(void);
+void tegra_gic_pcpu_init(void);
+void tegra_gic_setup(const interrupt_prop_t *interrupt_props,
+ unsigned int interrupt_props_num);
+
+#endif /* __TEGRA_GIC_H__ */
diff --git a/plat/nvidia/tegra/include/plat_macros.S b/plat/nvidia/tegra/include/plat_macros.S
index 14e7d8a..01ae821 100644
--- a/plat/nvidia/tegra/include/plat_macros.S
+++ b/plat/nvidia/tegra/include/plat_macros.S
@@ -7,6 +7,7 @@
#ifndef PLAT_MACROS_S
#define PLAT_MACROS_S
+#include <gicv2.h>
#include <tegra_def.h>
.section .rodata.gic_reg_name, "aS"
diff --git a/plat/nvidia/tegra/include/tegra_private.h b/plat/nvidia/tegra/include/tegra_private.h
index c4c277e..7ca32c3 100644
--- a/plat/nvidia/tegra/include/tegra_private.h
+++ b/plat/nvidia/tegra/include/tegra_private.h
@@ -8,8 +8,10 @@
#define TEGRA_PRIVATE_H
#include <arch.h>
+#include <arch_helpers.h>
#include <platform_def.h>
#include <psci.h>
+#include <tegra_gic.h>
#include <xlat_tables_v2.h>
/*******************************************************************************
@@ -31,26 +33,6 @@
} plat_params_from_bl2_t;
/*******************************************************************************
- * Per-CPU struct describing FIQ state to be stored
- ******************************************************************************/
-typedef struct pcpu_fiq_state {
- uint64_t elr_el3;
- uint64_t spsr_el3;
-} pcpu_fiq_state_t;
-
-/*******************************************************************************
- * Struct describing per-FIQ configuration settings
- ******************************************************************************/
-typedef struct irq_sec_cfg {
- /* IRQ number */
- unsigned int irq;
- /* Target CPUs servicing this interrupt */
- unsigned int target_cpus;
- /* type = INTR_TYPE_S_EL1 or INTR_TYPE_EL3 */
- uint32_t type;
-} irq_sec_cfg_t;
-
-/*******************************************************************************
* Struct describing parameters passed to bl31
******************************************************************************/
struct tegra_bl31_params {
@@ -82,10 +64,6 @@
int tegra_fiq_get_intr_context(void);
void tegra_fiq_set_ns_entrypoint(uint64_t entrypoint);
-/* Declarations for tegra_gic.c */
-void tegra_gic_cpuif_deactivate(void);
-void tegra_gic_setup(const irq_sec_cfg_t *irq_sec_ptr, uint32_t num_irqs);
-
/* Declarations for tegra_security.c */
void tegra_security_setup(void);
void tegra_security_setup_videomem(uintptr_t base, uint64_t size);