tree b8781fc14291cb3afd32a49ef8bbe5f60bdf0188
parent 9c60d802024f7892bdbe637097e03439d0ee2f32
author Achin Gupta <achin.gupta@arm.com> 1405705108 +0100
committer Achin Gupta <achin.gupta@arm.com> 1406538622 +0100

Simplify management of SCTLR_EL3 and SCTLR_EL1

This patch reworks the manner in which the M,A, C, SA, I, WXN & EE bits of
SCTLR_EL3 & SCTLR_EL1 are managed. The EE bit is cleared immediately after reset
in EL3. The I, A and SA bits are set next in EL3 and immediately upon entry in
S-EL1. These bits are no longer managed in the blX_arch_setup() functions. They
do not have to be saved and restored either. The M, WXN and optionally the C
bit are set in the enable_mmu_elX() function. This is done during both the warm
and cold boot paths.

Fixes ARM-software/tf-issues#226

Change-Id: Ie894d1a07b8697c116960d858cd138c50bc7a069