feat(nxp-clk): add ARM PLL ODIV enablement
Enable the PLL dividers using their memory-mapped interface. Otherwise,
the clock will not be propagated to downstream clock modules.
Change-Id: I39115cb2cb754cee87d7b6b4aa7502c3f1ef37ce
Signed-off-by: Ghennadi Procopciuc <ghennadi.procopciuc@nxp.com>
diff --git a/drivers/nxp/clk/s32cc/s32cc_early_clks.c b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
index 2a64922..639bbb1 100644
--- a/drivers/nxp/clk/s32cc/s32cc_early_clks.c
+++ b/drivers/nxp/clk/s32cc/s32cc_early_clks.c
@@ -59,5 +59,10 @@
return ret;
}
+ ret = clk_enable(S32CC_CLK_ARM_PLL_PHI0);
+ if (ret != 0) {
+ return ret;
+ }
+
return ret;
}