tree d5167eaea93bf19da9fd7a85bd0fd7471d66db19
parent 5f2e874485f342cb088f7da2b02ba4faaa6db3b7
author Yann Gautier <yann.gautier@st.com> 1557247773 +0200
committer Yann Gautier <yann.gautier@st.com> 1560773031 +0200

clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array

Rework the macro that eases the table definition: the src and msk fields
are now using MASK and SHIFT defines of each source register.
Some macros had then to be modified: _USART1_SEL, _ASS_SEL and _MSS_SEL to
_UART1_SEL, _AXIS_SEL, and _MCUS_SEL to match register fields.

Note: the mask for RCC_ASSCKSELR_AXISSRC is changed from 0x3 to 0x7
to reflect the size of the register field, even if there are only
3 possible clock sources.

The mask value is also corrected for QSPI and FMC clock selection.

Change-Id: I44114e3c1dd37b9fa1be1ba519611abd9a07764c
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>