Modify multithreaded dts file of DynamIQ FVPs
The dts file now contains a CPU map that precisely describes the
topology including thread nodes. The map was also extended to have 16
PEs to be able to test multithreaded FVPs with 8 cores in the same
cluster.
Signed-off-by: Imre Kis <imre.kis@arm.com>
Change-Id: If39559b05d20bfd68d0ecf830ddcbc5233b288a0
diff --git a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
index daa2e66..6e63b43 100644
--- a/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
+++ b/fdts/fvp-base-gicv3-psci-dynamiq-2t.dts
@@ -8,34 +8,181 @@
#include "fvp-base-gicv3-psci-dynamiq-common.dtsi"
-&CPU0 {
- reg = <0x0 0x0>;
-};
+&CPU_MAP {
+ /delete-node/ cluster0;
-&CPU1 {
- reg = <0x0 0x1>;
+ cluster0 {
+ core0 {
+ thread0 {
+ cpu = <&CPU0>;
+ };
+ thread1 {
+ cpu = <&CPU1>;
+ };
+ };
+ core1 {
+ thread0 {
+ cpu = <&CPU2>;
+ };
+ thread1 {
+ cpu = <&CPU3>;
+ };
+ };
+ core2 {
+ thread0 {
+ cpu = <&CPU4>;
+ };
+ thread1 {
+ cpu = <&CPU5>;
+ };
+ };
+ core3 {
+ thread0 {
+ cpu = <&CPU6>;
+ };
+ thread1 {
+ cpu = <&CPU7>;
+ };
+ };
+ core4 {
+ thread0 {
+ cpu = <&CPU8>;
+ };
+ thread1 {
+ cpu = <&CPU9>;
+ };
+ };
+ core5 {
+ thread0 {
+ cpu = <&CPU10>;
+ };
+ thread1 {
+ cpu = <&CPU11>;
+ };
+ };
+ core6 {
+ thread0 {
+ cpu = <&CPU12>;
+ };
+ thread1 {
+ cpu = <&CPU13>;
+ };
+ };
+ core7 {
+ thread0 {
+ cpu = <&CPU14>;
+ };
+ thread1 {
+ cpu = <&CPU15>;
+ };
+ };
+ };
};
-&CPU2 {
- reg = <0x0 0x100>;
-};
+/ {
+ cpus {
+ CPU0:cpu@0 {
+ reg = <0x0 0x0>;
+ };
-&CPU3 {
- reg = <0x0 0x101>;
-};
+ CPU1:cpu@1 {
+ reg = <0x0 0x1>;
+ };
-&CPU4 {
- reg = <0x0 0x200>;
-};
+ CPU2:cpu@2 {
+ reg = <0x0 0x100>;
+ };
-&CPU5 {
- reg = <0x0 0x201>;
-};
+ CPU3:cpu@3 {
+ reg = <0x0 0x101>;
+ };
-&CPU6 {
- reg = <0x0 0x300>;
-};
+ CPU4:cpu@100 {
+ reg = <0x0 0x200>;
+ };
+
+ CPU5:cpu@101 {
+ reg = <0x0 0x201>;
+ };
+
+ CPU6:cpu@102 {
+ reg = <0x0 0x300>;
+ };
+
+ CPU7:cpu@103 {
+ reg = <0x0 0x301>;
+ };
+
+ CPU8:cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x400>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU9:cpu@201 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x401>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU10:cpu@202 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x500>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU11:cpu@203 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x501>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU12:cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x600>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU13:cpu@301 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x601>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+
+ CPU14:cpu@302 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x700>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
-&CPU7 {
- reg = <0x0 0x301>;
+ CPU15:cpu@303 {
+ device_type = "cpu";
+ compatible = "arm,armv8";
+ reg = <0x0 0x701>;
+ enable-method = "psci";
+ cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+ next-level-cache = <&L2_0>;
+ };
+ };
};