diff --git a/plat/amlogic/gxbb/gxbb_bl31_setup.c b/plat/amlogic/gxbb/gxbb_bl31_setup.c
index cff29b3..26419d4 100644
--- a/plat/amlogic/gxbb/gxbb_bl31_setup.c
+++ b/plat/amlogic/gxbb/gxbb_bl31_setup.c
@@ -135,7 +135,7 @@
 
 void bl31_platform_setup(void)
 {
-	mhu_secure_init();
+	aml_mhu_secure_init();
 
 	gicv2_driver_init(&gxbb_gic_data);
 	gicv2_distif_init();
diff --git a/plat/amlogic/gxbb/gxbb_def.h b/plat/amlogic/gxbb/gxbb_def.h
index 1b781d9..b9183a4 100644
--- a/plat/amlogic/gxbb/gxbb_def.h
+++ b/plat/amlogic/gxbb/gxbb_def.h
@@ -42,8 +42,8 @@
 /* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
 
 /* Mailboxes */
-#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
-#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
+#define AML_MHU_SECURE_SCP_TO_AP_PAYLOAD	UL(0xD9013800)
+#define AML_MHU_SECURE_AP_TO_SCP_PAYLOAD	UL(0xD9013A00)
 #define GXBB_PSCI_MAILBOX_BASE			UL(0xD9013F00)
 
 #define GXBB_TZROM_BASE				UL(0xD9040000)
@@ -88,12 +88,12 @@
 
 #define GXBB_AO_RTI_STATUS_REG3			UL(0xDA10001C)
 
-#define GXBB_HIU_MAILBOX_SET_0			UL(0xDA83C404)
-#define GXBB_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
-#define GXBB_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
-#define GXBB_HIU_MAILBOX_SET_3			UL(0xDA83C428)
-#define GXBB_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
-#define GXBB_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
+#define AML_HIU_MAILBOX_SET_0			UL(0xDA83C404)
+#define AML_HIU_MAILBOX_STAT_0			UL(0xDA83C408)
+#define AML_HIU_MAILBOX_CLR_0			UL(0xDA83C40C)
+#define AML_HIU_MAILBOX_SET_3			UL(0xDA83C428)
+#define AML_HIU_MAILBOX_STAT_3			UL(0xDA83C42C)
+#define AML_HIU_MAILBOX_CLR_3			UL(0xDA83C430)
 
 /*******************************************************************************
  * System Monitor Call IDs and arguments