Merge "refactor(fvp_r): remove unused files and clean up makefiles" into integration
diff --git a/include/arch/aarch64/el2_common_macros.S b/include/arch/aarch64/el2_common_macros.S
index c57a1ec..7bf4806 100644
--- a/include/arch/aarch64/el2_common_macros.S
+++ b/include/arch/aarch64/el2_common_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -82,10 +82,6 @@
* Initialise MDCR_EL2, setting all fields rather than relying on
* hw. Some fields are architecturally UNKNOWN on reset.
*
- * MDCR_EL2.SDD: Set to one to disable AArch64 Secure self-hosted
- * debug. Debug exceptions, other than Breakpoint Instruction
- * exceptions, are disabled from all ELs in Secure state.
- *
* MDCR_EL2.TDOSA: Set to zero so that EL2 and EL2 System register
* access to the powerdown debug registers do not trap to EL2.
*
@@ -97,17 +93,7 @@
* register accesses to all Performance Monitors registers do not trap
* to EL2.
*
- * MDCR_EL2.SCCD: Set to one so that cycle counting by PMCCNTR_EL0
- * is prohibited in Secure state. This bit is RES0 in versions of the
- * architecture with FEAT_PMUv3p5 not implemented, setting it to 1
- * doesn't have any effect on them.
- *
- * MDCR_EL2.MCCD: Set to one so that cycle counting by PMCCNTR_EL0
- * is prohibited in EL2. This bit is RES0 in versions of the
- * architecture with FEAT_PMUv3p7 not implemented, setting it to 1
- * doesn't have any effect on them.
- *
- * MDCR_EL2.SPME: Set to zero so that event counting by the program-
+ * MDCR_EL2.HPMD: Set to zero so that event counting by the program-
* mable counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If
* ARMv8.2 Debug is not implemented this bit does not have any effect
* on the counters unless there is support for the implementation
@@ -115,9 +101,9 @@
* ExternalSecureNoninvasiveDebugEnabled().
* ---------------------------------------------------------------------
*/
- mov_imm x0, ((MDCR_EL2_RESET_VAL | MDCR_SDD_BIT | \
- MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT | \
- MDCR_MCCD_BIT) & ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | \
+ mov_imm x0, ((MDCR_EL2_RESET_VAL | \
+ MDCR_SPD32(MDCR_SPD32_DISABLE)) \
+ & ~(MDCR_EL2_HPMD | MDCR_TDOSA_BIT | \
MDCR_TDA_BIT | MDCR_TPM_BIT))
msr mdcr_el2, x0
@@ -126,17 +112,6 @@
* Initialise PMCR_EL0 setting all fields rather than relying
* on hw. Some fields are architecturally UNKNOWN on reset.
*
- * PMCR_EL0.LP: Set to one so that event counter overflow, that
- * is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
- * that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
- * is implemented. This bit is RES0 in versions of the architecture
- * earlier than ARMv8.5, setting it to 1 doesn't have any effect
- * on them.
- *
- * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
- * is recorded in PMOVSCLR_EL0[31], occurs on the increment
- * that changes PMCCNTR_EL0[63] from 1 to 0.
- *
* PMCR_EL0.DP: Set to one so that the cycle counter,
* PMCCNTR_EL0 does not count when event counting is prohibited.
*
@@ -146,8 +121,7 @@
* counts on every clock cycle.
* ---------------------------------------------------------------------
*/
- mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
- PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
+ mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_DP_BIT) & \
~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
msr pmcr_el0, x0
diff --git a/lib/xlat_mpu/xlat_mpu_utils.c b/lib/xlat_mpu/xlat_mpu_utils.c
index f305632..5400875 100644
--- a/lib/xlat_mpu/xlat_mpu_utils.c
+++ b/lib/xlat_mpu/xlat_mpu_utils.c
@@ -22,13 +22,13 @@
#warning "xlat_mpu library is currently experimental and its API may change in future."
-#if LOG_LEVEL < LOG_LEVEL_VERBOSE
-
void xlat_mmap_print(__unused const mmap_region_t *mmap)
{
/* Empty */
}
+#if LOG_LEVEL < LOG_LEVEL_VERBOSE
+
void xlat_tables_print(__unused xlat_ctx_t *ctx)
{
/* Empty */
@@ -36,36 +36,48 @@
#else /* if LOG_LEVEL >= LOG_LEVEL_VERBOSE */
-static const char *invalid_descriptors_ommited =
- "%s(%d invalid descriptors omitted)\n";
-
-void xlat_tables_print(xlat_ctx_t *ctx)
+static void xlat_tables_print_internal(__unused xlat_ctx_t *ctx)
{
- const char *xlat_regime_str;
- int used_page_tables;
+ int region_to_use = 0;
+ uintptr_t region_base;
+ size_t region_size;
+ uint64_t prenr_el2_value = 0U;
- if (ctx->xlat_regime == EL1_EL0_REGIME) {
- xlat_regime_str = "1&0";
- } else if (ctx->xlat_regime == EL2_REGIME) {
- xlat_regime_str = "2";
- } else {
- assert(ctx->xlat_regime == EL3_REGIME);
- xlat_regime_str = "3";
- /* If no EL3 and EL3 tables generated, then need to know. */
- }
- VERBOSE("Translation tables state:\n");
- VERBOSE(" Xlat regime: EL%s\n", xlat_regime_str);
- VERBOSE(" Max allowed PA: 0x%llx\n", ctx->pa_max_address);
- VERBOSE(" Max allowed VA: 0x%lx\n", ctx->va_max_address);
- VERBOSE(" Max mapped PA: 0x%llx\n", ctx->max_pa);
- VERBOSE(" Max mapped VA: 0x%lx\n", ctx->max_va);
+ /*
+ * Keep track of how many invalid descriptors are counted in a row.
+ * Whenever multiple invalid descriptors are found, only the first one
+ * is printed, and a line is added to inform about how many descriptors
+ * have been omitted.
+ */
- VERBOSE(" Initial lookup level: %u\n", ctx->base_level);
- VERBOSE(" Entries @initial lookup level: %u\n",
- ctx->base_table_entries);
+ /*
+ * TODO: Remove this WARN() and comment when these API calls are more
+ * completely implemented and tested!
+ */
+ WARN("%s in this early version of xlat_mpu library may not produce reliable results!",
+ __func__);
- xlat_tables_print_internal(ctx, 0U, ctx->base_table,
- ctx->base_table_entries, ctx->base_level);
+ /*
+ * Sequence through all regions and print those in-use (PRENR has an
+ * enable bit for each MPU region, 1 for in-use or 0 for unused):
+ */
+ prenr_el2_value = read_prenr_el2();
+ for (region_to_use = 0; region_to_use < N_MPU_REGIONS;
+ region_to_use++) {
+ if (((prenr_el2_value >> region_to_use) & 1U) == 0U) {
+ continue;
+ }
+ region_base = read_prbar_el2() & PRBAR_PRLAR_ADDR_MASK;
+ region_size = read_prlar_el2() & PRBAR_PRLAR_ADDR_MASK;
+ printf("Address: 0x%llx, size: 0x%llx ",
+ (long long) region_base,
+ (long long) region_size);
+ }
+}
+
+void xlat_tables_print(__unused xlat_ctx_t *ctx)
+{
+ xlat_tables_print_internal(ctx);
}
#endif /* LOG_LEVEL >= LOG_LEVEL_VERBOSE */
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c b/plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c
deleted file mode 100644
index c6544b4..0000000
--- a/plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <assert.h>
-
-#include "../../../../bl1/bl1_private.h"
-#include <arch_helpers.h>
-#include <common/debug.h>
-#include <context.h>
-#include <lib/el3_runtime/context_mgmt.h>
-
-#include <plat/common/platform.h>
-
-
-void cm_prepare_el2_exit(void);
-
-/* Following contains the cpu context pointers. */
-static void *bl1_cpu_context_ptr[2];
-
-void *cm_get_context(uint32_t security_state)
-{
- assert(sec_state_is_valid(security_state));
- return bl1_cpu_context_ptr[security_state];
-}
-
-void cm_set_context(void *context, uint32_t security_state)
-{
- assert(sec_state_is_valid(security_state));
- bl1_cpu_context_ptr[security_state] = context;
-}
-
-/*******************************************************************************
- * This function prepares the context for Secure/Normal world images.
- * Normal world images are transitioned to EL2(if supported) else EL1.
- ******************************************************************************/
-void bl1_prepare_next_image(unsigned int image_id)
-{
- /*
- * Following array will be used for context management.
- * There are 2 instances, for the Secure and Non-Secure contexts.
- */
- static cpu_context_t bl1_cpu_context[2];
-
- unsigned int security_state, mode = MODE_EL1;
- image_desc_t *desc;
- entry_point_info_t *next_bl_ep;
-
-#if CTX_INCLUDE_AARCH32_REGS
- /*
- * Ensure that the build flag to save AArch32 system registers in CPU
- * context is not set for AArch64-only platforms.
- */
- if (el_implemented(1) == EL_IMPL_A64ONLY) {
- ERROR("EL1 supports AArch64-only. Please set build flag %s",
- "CTX_INCLUDE_AARCH32_REGS = 0\n");
- panic();
- }
-#endif
-
- /* Get the image descriptor. */
- desc = bl1_plat_get_image_desc(image_id);
- assert(desc != NULL);
-
- /* Get the entry point info. */
- next_bl_ep = &desc->ep_info;
-
- /* Get the image security state. */
- security_state = GET_SECURITY_STATE(next_bl_ep->h.attr);
-
- /* Setup the Secure/Non-Secure context if not done already. */
- if (cm_get_context(security_state) == NULL) {
- cm_set_context(&bl1_cpu_context[security_state], security_state);
- }
- /* Prepare the SPSR for the next BL image. */
- next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
- (uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
-
- /* Allow platform to make change */
- bl1_plat_set_ep_info(image_id, next_bl_ep);
-
- /* Prepare context for the next EL */
- cm_prepare_el2_exit();
-
- /* Indicate that image is in execution state. */
- desc->state = IMAGE_STATE_EXECUTED;
-
- print_entry_point_info(next_bl_ep);
-}
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S b/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
index 19a685c..15f4c43 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S
@@ -43,14 +43,6 @@
*/
bl bl1_setup
-#if ENABLE_PAUTH
- /* --------------------------------------------------------------------
- * Program APIAKey_EL1 and enable pointer authentication.
- * --------------------------------------------------------------------
- */
- bl pauth_init_enable_el2
-#endif /* ENABLE_PAUTH */
-
/* --------------------------------------------------------------------
* Initialize platform and jump to our c-entry point
* for this type of reset.
@@ -85,15 +77,6 @@
*/
bl clear_all_mpu_regions
-#if ENABLE_PAUTH
- /* ---------------------------------------------
- * Disable pointer authentication before jumping
- * to next boot image.
- * ---------------------------------------------
- */
- bl pauth_disable_el2
-#endif /* ENABLE_PAUTH */
-
/* --------------------------------------------------
* Do the transition to next boot image.
* --------------------------------------------------
diff --git a/plat/arm/board/fvp_r/fvp_r_bl1_main.c b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
index 2fd0e97..841a176 100644
--- a/plat/arm/board/fvp_r/fvp_r_bl1_main.c
+++ b/plat/arm/board/fvp_r/fvp_r_bl1_main.c
@@ -25,6 +25,8 @@
#include <platform_def.h>
+void cm_prepare_el2_exit(void);
+
void bl1_run_next_image(const struct entry_point_info *bl_ep_info);
/*******************************************************************************
@@ -39,13 +41,6 @@
/* Get the image id of next image to load and run. */
image_id = bl1_plat_get_next_image_id();
-#if ENABLE_PAUTH
- /*
- * Disable pointer authentication before running next boot image
- */
- pauth_disable_el2();
-#endif /* ENABLE_PAUTH */
-
#if !ARM_DISABLE_TRUSTED_WDOG
/* Disable watchdog before leaving BL1 */
plat_arm_secure_wdt_stop();
@@ -96,12 +91,6 @@
NOTICE("BL1: Booting BL33\n");
}
-static void bl1_load_bl2(void);
-
-#if ENABLE_PAUTH
-uint64_t bl1_apiakey[2];
-#endif
-
/*******************************************************************************
* Helper utility to calculate the BL2 memory layout taking into consideration
* the BL1 RW data assuming that it is at the top of the memory layout.
@@ -124,6 +113,53 @@
}
/*******************************************************************************
+ * This function prepares for entry to BL33
+ ******************************************************************************/
+void bl1_prepare_next_image(unsigned int image_id)
+{
+ unsigned int mode = MODE_EL1;
+ image_desc_t *desc;
+ entry_point_info_t *next_bl_ep;
+
+#if CTX_INCLUDE_AARCH32_REGS
+ /*
+ * Ensure that the build flag to save AArch32 system registers in CPU
+ * context is not set for AArch64-only platforms.
+ */
+ if (el_implemented(1) == EL_IMPL_A64ONLY) {
+ ERROR("EL1 supports AArch64-only. Please set build flag %s",
+ "CTX_INCLUDE_AARCH32_REGS = 0\n");
+ panic();
+ }
+#endif
+
+ /* Get the image descriptor. */
+ desc = bl1_plat_get_image_desc(image_id);
+ assert(desc != NULL);
+
+ /* Get the entry point info. */
+ next_bl_ep = &desc->ep_info;
+
+ /* FVP-R is only secure */
+ assert(GET_SECURITY_STATE(next_bl_ep->h.attr) == SECURE);
+
+ /* Prepare the SPSR for the next BL image. */
+ next_bl_ep->spsr = (uint32_t)SPSR_64((uint64_t) mode,
+ (uint64_t)MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
+
+ /* Allow platform to make change */
+ bl1_plat_set_ep_info(image_id, next_bl_ep);
+
+ /* Prepare context for the next EL */
+ cm_prepare_el2_exit();
+
+ /* Indicate that image is in execution state. */
+ desc->state = IMAGE_STATE_EXECUTED;
+
+ print_entry_point_info(next_bl_ep);
+}
+
+/*******************************************************************************
* Setup function for BL1.
******************************************************************************/
void bl1_setup(void)
@@ -133,14 +169,6 @@
/* Perform late platform-specific setup */
bl1_plat_arch_setup();
-
-#if CTX_INCLUDE_PAUTH_REGS
- /*
- * Assert that the ARMv8.3-PAuth registers are present or an access
- * fault will be triggered when they are being saved or restored.
- */
- assert(is_armv8_3_pauth_present());
-#endif /* CTX_INCLUDE_PAUTH_REGS */
}
/*******************************************************************************
@@ -199,12 +227,6 @@
/* Perform platform setup in BL1. */
bl1_platform_setup();
-#if ENABLE_PAUTH
- /* Store APIAKey_EL1 key */
- bl1_apiakey[0] = read_apiakeylo_el1();
- bl1_apiakey[1] = read_apiakeyhi_el1();
-#endif /* ENABLE_PAUTH */
-
/* Get the image id of next image to load and run. */
image_id = bl1_plat_get_next_image_id();
@@ -212,9 +234,7 @@
* We currently interpret any image id other than
* BL2_IMAGE_ID as the start of firmware update.
*/
- if (image_id == BL2_IMAGE_ID) {
- bl1_load_bl2();
- } else if (image_id == BL33_IMAGE_ID) {
+ if (image_id == BL33_IMAGE_ID) {
bl1_load_bl33();
} else {
NOTICE("BL1-FWU: *******FWU Process Started*******\n");
@@ -228,48 +248,6 @@
}
/*******************************************************************************
- * This function locates and loads the BL2 raw binary image in the trusted SRAM.
- * Called by the primary cpu after a cold boot.
- * TODO: Add support for alternative image load mechanism e.g using virtio/elf
- * loader etc.
- ******************************************************************************/
-static void bl1_load_bl2(void)
-{
- image_desc_t *desc;
- image_info_t *info;
- int err;
-
- /* Get the image descriptor */
- desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
- assert(desc != NULL);
-
- /* Get the image info */
- info = &desc->image_info;
- INFO("BL1: Loading BL2\n");
-
- err = bl1_plat_handle_pre_image_load(BL2_IMAGE_ID);
- if (err != 0) {
- ERROR("Failure in pre image load handling of BL2 (%d)\n", err);
- plat_error_handler(err);
- }
-
- err = load_auth_image(BL2_IMAGE_ID, info);
- if (err != 0) {
- ERROR("Failed to load BL2 firmware.\n");
- plat_error_handler(err);
- }
-
- /* Allow platform to handle image information. */
- err = bl1_plat_handle_post_image_load(BL2_IMAGE_ID);
- if (err != 0) {
- ERROR("Failure in post image load handling of BL2 (%d)\n", err);
- plat_error_handler(err);
- }
-
- NOTICE("BL1: Booting BL2\n");
-}
-
-/*******************************************************************************
* Function called just before handing over to the next BL to inform the user
* about the boot progress. In debug mode, also print details about the BL
* image's execution context.
diff --git a/plat/arm/board/fvp_r/fvp_r_common.c b/plat/arm/board/fvp_r/fvp_r_common.c
index bce943d..edcf658 100644
--- a/plat/arm/board/fvp_r/fvp_r_common.c
+++ b/plat/arm/board/fvp_r/fvp_r_common.c
@@ -11,7 +11,6 @@
#include <common/debug.h>
#include <drivers/arm/cci.h>
-#include <drivers/arm/ccn.h>
#include <drivers/arm/gicv2.h>
#include <drivers/arm/sp804_delay_timer.h>
#include <drivers/generic_delay_timer.h>
@@ -80,7 +79,6 @@
ARM_CASSERT_MMAP
-#if FVP_R_INTERCONNECT_DRIVER != FVP_R_CCN
static const int fvp_cci400_map[] = {
PLAT_FVP_R_CCI400_CLUS0_SL_PORT,
PLAT_FVP_R_CCI400_CLUS1_SL_PORT,
@@ -103,7 +101,6 @@
assert(master < FVP_R_CLUSTER_COUNT);
return master;
}
-#endif
/*******************************************************************************
* Initialize the platform config for future decision making
@@ -198,14 +195,6 @@
void __init fvp_interconnect_init(void)
{
-#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
- if (ccn_get_part0_id(PLAT_ARM_CCN_BASE) != CCN_502_PART0_ID) {
- ERROR("Unrecognized CCN variant detected. Only CCN-502 is supported");
- panic();
- }
-
- plat_arm_interconnect_init();
-#else
uintptr_t cci_base = 0U;
const int *cci_map = NULL;
unsigned int map_size = 0U;
@@ -226,14 +215,10 @@
assert(cci_base != 0U);
assert(cci_map != NULL);
cci_init(cci_base, cci_map, map_size);
-#endif
}
void fvp_interconnect_enable(void)
{
-#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
- plat_arm_interconnect_enter_coherency();
-#else
unsigned int master;
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
@@ -241,14 +226,10 @@
master = get_interconnect_master();
cci_enable_snoop_dvm_reqs(master);
}
-#endif
}
void fvp_interconnect_disable(void)
{
-#if FVP_R_INTERCONNECT_DRIVER == FVP_R_CCN
- plat_arm_interconnect_exit_coherency();
-#else
unsigned int master;
if ((arm_config.flags & (ARM_CONFIG_FVP_HAS_CCI400 |
@@ -256,7 +237,6 @@
master = get_interconnect_master();
cci_disable_snoop_dvm_reqs(master);
}
-#endif
}
#if TRUSTED_BOARD_BOOT
diff --git a/plat/arm/board/fvp_r/fvp_r_context.S b/plat/arm/board/fvp_r/fvp_r_context.S
deleted file mode 100644
index 2746c2e..0000000
--- a/plat/arm/board/fvp_r/fvp_r_context.S
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <asm_macros.S>
-
- .global el2_exit
-
-/* ------------------------------------------------------------------
- * The mechanism, from el3_exit, is not used in this v8-R64 implementation.
- * ------------------------------------------------------------------
- */
-func el2_exit
- exception_return
-endfunc el2_exit
diff --git a/plat/arm/board/fvp_r/fvp_r_debug.S b/plat/arm/board/fvp_r/fvp_r_debug.S
index 8db1b09..88f0a29 100644
--- a/plat/arm/board/fvp_r/fvp_r_debug.S
+++ b/plat/arm/board/fvp_r/fvp_r_debug.S
@@ -41,6 +41,7 @@
_panic_handler:
/* Pass to plat_panic_handler the address from where el2_panic was
- * called, not the address of the call from el2_panic. */
+ * called, not the address of the call from el2_panic.
+ */
mov x30, x6
b plat_panic_handler
diff --git a/plat/arm/board/fvp_r/fvp_r_def.h b/plat/arm/board/fvp_r/fvp_r_def.h
index b9f6989..eda39cf 100644
--- a/plat/arm/board/fvp_r/fvp_r_def.h
+++ b/plat/arm/board/fvp_r/fvp_r_def.h
@@ -9,28 +9,18 @@
#include <lib/utils_def.h>
-#ifndef FVP_R_CLUSTER_COUNT
-#error "FVP_R_CLUSTER_COUNT is not set in makefile"
-#endif
-
-#ifndef FVP_R_MAX_CPUS_PER_CLUSTER
-#error "FVP_R_MAX_CPUS_PER_CLUSTER is not set in makefile"
-#endif
-
-#ifndef FVP_R_MAX_PE_PER_CPU
-#error "FVP_R_MAX_PE_PER_CPU is not set in makefile"
-#endif
-
-#define FVP_R_PRIMARY_CPU 0x0
-
-/* Defines for the Interconnect build selection */
-#define FVP_R_CCI 1
-#define FVP_R_CCN 2
+/******************************************************************************
+ * FVP-R topology constants
+ *****************************************************************************/
+#define FVP_R_CLUSTER_COUNT 2
+#define FVP_R_MAX_CPUS_PER_CLUSTER 4
+#define FVP_R_MAX_PE_PER_CPU 1
+#define FVP_R_PRIMARY_CPU 0x0
/******************************************************************************
* Definition of platform soc id
*****************************************************************************/
-#define FVP_R_SOC_ID 0
+#define FVP_R_SOC_ID 0
/*******************************************************************************
* FVP_R memory map related constants
diff --git a/plat/arm/board/fvp_r/fvp_r_helpers.S b/plat/arm/board/fvp_r/fvp_r_helpers.S
index f7a04d8..ba85777 100644
--- a/plat/arm/board/fvp_r/fvp_r_helpers.S
+++ b/plat/arm/board/fvp_r/fvp_r_helpers.S
@@ -16,7 +16,6 @@
.globl plat_secondary_cold_boot_setup
.globl plat_get_my_entrypoint
.globl plat_is_my_cpu_primary
- .globl plat_arm_calc_core_pos
/* -----------------------------------------------------
* void plat_secondary_cold_boot_setup (void);
@@ -127,40 +126,3 @@
cset w0, eq
ret
endfunc plat_is_my_cpu_primary
-
- /* ---------------------------------------------------------------------
- * unsigned int plat_arm_calc_core_pos(u_register_t mpidr)
- *
- * Function to calculate the core position on FVP_R.
- *
- * (ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER * FVP_R_MAX_PE_PER_CPU) +
- * (CPUId * FVP_R_MAX_PE_PER_CPU) +
- * ThreadId
- *
- * which can be simplified as:
- *
- * ((ClusterId * FVP_R_MAX_CPUS_PER_CLUSTER + CPUId) * FVP_R_MAX_PE_PER_CPU)
- * + ThreadId
- * ---------------------------------------------------------------------
- */
-func plat_arm_calc_core_pos
- /*
- * Check for MT bit in MPIDR. If not set, shift MPIDR to left to make it
- * look as if in a multi-threaded implementation.
- */
- tst x0, #MPIDR_MT_MASK
- lsl x3, x0, #MPIDR_AFFINITY_BITS
- csel x3, x3, x0, eq
-
- /* Extract individual affinity fields from MPIDR */
- ubfx x0, x3, #MPIDR_AFF0_SHIFT, #MPIDR_AFFINITY_BITS
- ubfx x1, x3, #MPIDR_AFF1_SHIFT, #MPIDR_AFFINITY_BITS
- ubfx x2, x3, #MPIDR_AFF2_SHIFT, #MPIDR_AFFINITY_BITS
-
- /* Compute linear position */
- mov x4, #FVP_R_MAX_CPUS_PER_CLUSTER
- madd x1, x2, x4, x1
- mov x5, #FVP_R_MAX_PE_PER_CPU
- madd x0, x1, x5, x0
- ret
-endfunc plat_arm_calc_core_pos
diff --git a/plat/arm/board/fvp_r/fvp_r_pauth_helpers.S b/plat/arm/board/fvp_r/fvp_r_pauth_helpers.S
deleted file mode 100644
index 7e6bc3d..0000000
--- a/plat/arm/board/fvp_r/fvp_r_pauth_helpers.S
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2021, Arm Limited. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <arch.h>
-#include <asm_macros.S>
-#include <lib/el3_runtime/cpu_data.h>
-
- .global pauth_init_enable_el2
- .global pauth_disable_el2
-
-/* -------------------------------------------------------------
- * File contains EL2 versions of EL3 funcs in:
- * .../lib/extensions/pauth/pauth_helpers.S
- * -------------------------------------------------------------
- */
-
-/* -------------------------------------------------------------
- * Program APIAKey_EL1 and enable pointer authentication in EL2
- * -------------------------------------------------------------
- */
-func pauth_init_enable_el2
- stp x29, x30, [sp, #-16]!
-
- /* Initialize platform key */
- bl plat_init_apkey
-
- /* Program instruction key A used by the Trusted Firmware */
- msr APIAKeyLo_EL1, x0
- msr APIAKeyHi_EL1, x1
-
- /* Enable pointer authentication */
- mrs x0, sctlr_el2
- orr x0, x0, #SCTLR_EnIA_BIT
-
-#if ENABLE_BTI
- /* Enable PAC branch type compatibility */
- bic x0, x0, #SCTLR_BT_BIT
-#endif
- msr sctlr_el2, x0
- isb
-
- ldp x29, x30, [sp], #16
- ret
-endfunc pauth_init_enable_el2
-
-/* -------------------------------------------------------------
- * Disable pointer authentication in EL2
- * -------------------------------------------------------------
- */
-func pauth_disable_el2
- mrs x0, sctlr_el2
- bic x0, x0, #SCTLR_EnIA_BIT
- msr sctlr_el2, x0
- isb
- ret
-endfunc pauth_disable_el2
diff --git a/plat/arm/board/fvp_r/include/plat.ld.S b/plat/arm/board/fvp_r/include/plat.ld.S
deleted file mode 100644
index e91a5a0..0000000
--- a/plat/arm/board/fvp_r/include/plat.ld.S
+++ /dev/null
@@ -1,11 +0,0 @@
-/*
- * Copyright (c) 2021, ARM Limited and Contributors. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-#ifndef PLAT_LD_S
-#define PLAT_LD_S
-
-#include <plat/arm/common/arm_tzc_dram.ld.S>
-
-#endif /* PLAT_LD_S */
diff --git a/plat/arm/board/fvp_r/include/platform_def.h b/plat/arm/board/fvp_r/include/platform_def.h
index 4a6b441..ea3a258 100644
--- a/plat/arm/board/fvp_r/include/platform_def.h
+++ b/plat/arm/board/fvp_r/include/platform_def.h
@@ -210,10 +210,6 @@
#define PLAT_FVP_R_CCI5XX_CLUS0_SL_PORT 5
#define PLAT_FVP_R_CCI5XX_CLUS1_SL_PORT 6
-/* CCN related constants. Only CCN 502 is currently supported */
-#define PLAT_ARM_CCN_BASE UL(0xae000000)
-#define PLAT_ARM_CLUSTER_TO_CCN_ID_MAP 1, 5, 7, 11
-
/* System timer related constants */
#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
diff --git a/plat/arm/board/fvp_r/platform.mk b/plat/arm/board/fvp_r/platform.mk
index 8f5878f..93b5cf2 100644
--- a/plat/arm/board/fvp_r/platform.mk
+++ b/plat/arm/board/fvp_r/platform.mk
@@ -15,47 +15,12 @@
override CTX_INCLUDE_AARCH32_REGS := 0
-# Default cluster count for FVP_R
-FVP_R_CLUSTER_COUNT := 2
-
-# Default number of CPUs per cluster on FVP_R
-FVP_R_MAX_CPUS_PER_CLUSTER := 4
-
-# Default number of threads per CPU on FVP_R
-FVP_R_MAX_PE_PER_CPU := 1
-
# Use MPU-based memory management:
XLAT_MPU_LIB_V1 := 1
-# Pass FVP_R_CLUSTER_COUNT to the build system.
-$(eval $(call add_define,FVP_R_CLUSTER_COUNT))
-
-# Pass FVP_R_MAX_CPUS_PER_CLUSTER to the build system.
-$(eval $(call add_define,FVP_R_MAX_CPUS_PER_CLUSTER))
-
-# Pass FVP_R_MAX_PE_PER_CPU to the build system.
-$(eval $(call add_define,FVP_R_MAX_PE_PER_CPU))
-
-# Sanity check the cluster count and if FVP_R_CLUSTER_COUNT <= 2,
-# choose the CCI driver , else the CCN driver
-ifeq ($(FVP_R_CLUSTER_COUNT), 0)
-$(error "Incorrect cluster count specified for FVP_R port")
-else ifeq ($(FVP_R_CLUSTER_COUNT),$(filter $(FVP_R_CLUSTER_COUNT),1 2))
-FVP_R_INTERCONNECT_DRIVER := FVP_R_CCI
-else
-FVP_R_INTERCONNECT_DRIVER := FVP_R_CCN
-endif
-
-$(eval $(call add_define,FVP_R_INTERCONNECT_DRIVER))
-
-ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCI)
+# FVP R will not have more than 2 clusters so just use CCI interconnect
FVP_R_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c
-else ifeq (${FVP_R_INTERCONNECT_DRIVER}, FVP_R_CCN)
-FVP_R_INTERCONNECT_SOURCES := drivers/arm/ccn/ccn.c \
- plat/arm/common/arm_ccn.c
-else
-$(error "Incorrect CCN driver chosen on FVP_R port")
-endif
+
include plat/arm/board/common/board_common.mk
include plat/arm/common/arm_common.mk
@@ -64,17 +29,14 @@
FVP_R_BL_COMMON_SOURCES := plat/arm/board/fvp_r/fvp_r_common.c \
plat/arm/board/fvp_r/fvp_r_context_mgmt.c \
- plat/arm/board/fvp_r/fvp_r_context.S \
plat/arm/board/fvp_r/fvp_r_debug.S \
plat/arm/board/fvp_r/fvp_r_err.c \
plat/arm/board/fvp_r/fvp_r_helpers.S \
- plat/arm/board/fvp_r/fvp_r_misc_helpers.S \
- plat/arm/board/fvp_r/fvp_r_pauth_helpers.S
+ plat/arm/board/fvp_r/fvp_r_misc_helpers.S
FVP_R_BL1_SOURCES := plat/arm/board/fvp_r/fvp_r_bl1_arch_setup.c \
plat/arm/board/fvp_r/fvp_r_bl1_setup.c \
plat/arm/board/fvp_r/fvp_r_io_storage.c \
- plat/arm/board/fvp_r/fvp_r_bl1_context_mgmt.c \
plat/arm/board/fvp_r/fvp_r_bl1_entrypoint.S \
plat/arm/board/fvp_r/fvp_r_bl1_exceptions.S \
plat/arm/board/fvp_r/fvp_r_bl1_main.c
@@ -82,17 +44,13 @@
FVP_R_CPU_LIBS := lib/cpus/${ARCH}/aem_generic.S
FVP_R_DYNC_CFG_SOURCES := common/fdt_wrappers.c \
- common/uuid.c \
- plat/arm/common/arm_dyn_cfg.c \
- plat/arm/common/arm_dyn_cfg_helpers.c
+ plat/arm/common/arm_dyn_cfg.c
ifeq (${TRUSTED_BOARD_BOOT},1)
FVP_R_AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
lib/fconf/fconf_tbbr_getter.c \
- bl1/tbbr/tbbr_img_desc.c \
- plat/arm/common/arm_bl1_fwu.c \
plat/common/tbbr/plat_tbbr.c \
drivers/auth/tbbr/tbbr_cot_bl1_r64.c \
drivers/auth/tbbr/tbbr_cot_common.c \
@@ -125,11 +83,6 @@
drivers/io/io_storage.c \
drivers/io/io_semihosting.c \
lib/cpus/aarch64/cpu_helpers.S \
- lib/cpus/errata_report.c \
- lib/cpus/aarch64/dsu_helpers.S \
- lib/el3_runtime/aarch64/context.S \
- lib/el3_runtime/aarch64/context_mgmt.c \
- lib/fconf/fconf.c \
lib/fconf/fconf_dyn_cfg_getter.c \
lib/semihosting/semihosting.c \
lib/semihosting/${ARCH}/semihosting_call.S \