refactor(gic): promote most of the GIC driver to common code
More often than not, Arm based systems include some revision of a GIC.
There are two ways of adding support for them in platform code - calling
the top-level helpers from plat/arm/common/arm_gicvX.c or by using the
driver directly. Both of these methods allow for a high degree of
customisation - most functions are defined to be weak and there are no
calls to any of them in generic code.
As it turns out, requirements around those GICs are largely the same.
Platforms that use arm_gicvX.c use the helpers identically among each
other. Platforms that use the driver directly tend to end up with calls
that look a lot like the arm_gicvX.c helpers and the weakness of the
functions are never exercised.
All of this results in a lot of code duplication to do what is
essentially the same thing. Even though it's not a lot of code, when
multiplied among many platforms it becomes significant and makes
refactoring it quite difficult. It's also bug prone since the steps are
a little convoluted and things are likely to work even with subtle
errors (see 50009f61177421118f42d6a000611ba0e613d54b).
So promote as much of the GIC to be called from common code. Do the
setup in bl31_main() and have every PSCI method do the state management
directly instead of delegating it to the platform hooks. We can base
this implementation on arm_gicvX.c since they already offer logical
names and have worked quite well so far with minimal changes.
The main benefit of doing this is reduced code duplication. If we assume
that, outside of some platform setup, GIC management is identical, then
a platform can add support by telling the build system, regardless of
GIC revision. The other benefit is performance - BL31 and PSCI already
know the core_pos and they can pass it as an argument instead of having
to call plat_my_core_pos(). Now, the only platform specific GIC actions
necessary are the saving and restoring of context on entering and
exiting a power domain. The PSCI library does not keep track of this so
it is unable perform it itself. The routines themselves are also
provided.
For compatibility all of this is hidden behind a build flag. Platforms
are encouraged to adopt this driver, but it would not be practical to
convert and validate every GIC based platform.
This patch renames the functions in question to follow the
gic_<function>() convention. This allows the names to be version
agnostic.
Finally, drop the weak definitions - they are unused, likely to remain
so, and can be added back if the need arises.
Change-Id: I5b5267f4b72f633fb1096400ec8e4b208694135f
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/Makefile b/Makefile
index 4f6afaf..6d5a0c3 100644
--- a/Makefile
+++ b/Makefile
@@ -764,6 +764,10 @@
include lib/libc/libc.mk
endif
+ifneq (${USE_GIC_DRIVER},0)
+include drivers/arm/gic/gic.mk
+endif
+
################################################################################
# Check incompatible options and dependencies
################################################################################
diff --git a/bl31/bl31_main.c b/bl31/bl31_main.c
index 5944b91..a9f89fc 100644
--- a/bl31/bl31_main.c
+++ b/bl31/bl31_main.c
@@ -17,6 +17,7 @@
#include <common/debug.h>
#include <common/feat_detect.h>
#include <common/runtime_svc.h>
+#include <drivers/arm/gic.h>
#include <drivers/console.h>
#include <lib/bootmarker_capture.h>
#include <lib/el3_runtime/context_debug.h>
@@ -145,6 +146,18 @@
/* Perform platform setup in BL31 */
bl31_platform_setup();
+#if USE_GIC_DRIVER
+ /*
+ * Initialize the GIC driver as well as per-cpu and global interfaces.
+ * Platform has had an opportunity to initialise specifics.
+ */
+ unsigned int core_pos = plat_my_core_pos();
+
+ gic_init(core_pos);
+ gic_pcpu_init(core_pos);
+ gic_cpuif_enable(core_pos);
+#endif /* USE_GIC_DRIVER */
+
/* Initialise helper libraries */
bl31_lib_init();
diff --git a/docs/getting_started/build-options.rst b/docs/getting_started/build-options.rst
index 2a42269..e5f7b30 100644
--- a/docs/getting_started/build-options.rst
+++ b/docs/getting_started/build-options.rst
@@ -1288,11 +1288,37 @@
This option should only be enabled on a need basis if there is a use case for
reading characters from the console.
-GICv3 driver options
+GIC driver options
--------------------
+The generic GIC driver can be included with the ``USE_GIC_DRIVER`` option. It is
+a numeric option that can take the following values:
+
+ - ``0``: generic GIC driver not enabled. Any support is entirely in platform
+ code. Strongly discouraged for GIC based interrupt controllers.
+
+ - ``1``: enable the use of the generic GIC driver but do not include any files
+ or function definitions. It is then the platform's responsibility to provide
+ these. This is useful if the platform either has a custom GIC implementation
+ or an alternative interrupt controller design. Use of this option is strongly
+ discouraged for standard GIC implementations.
+
-GICv3 driver files are included using directive:
+ - ``2``: use the GICv2 driver
+
+ - ``3``: use the GICv3 driver. See the next section on how to further configure
+ it. Use this option for GICv4 implementations.
+
+ For GIC driver versions other than ``1``, deciding when to save and restore GIC
+ context on a power domain state transition, as well as any GIC actions outside
+ of the PSCI library's visibility are the platform's responsibility. The driver
+ provides implementations of all necessary subroutines, they only need to be
+ called as appropriate.
+
+GICv3 driver options
+~~~~~~~~~~~~~~~~~~~~
+``USE_GIC_DRIVER=3`` is the preferred way of including GICv3 driver files. The
+old (deprecated) way of included them is using the directive:
``include drivers/arm/gic/v3/gicv3.mk``
The driver can be configured with the following options set in the platform
diff --git a/drivers/arm/gic/gic.mk b/drivers/arm/gic/gic.mk
new file mode 100644
index 0000000..ad30984
--- /dev/null
+++ b/drivers/arm/gic/gic.mk
@@ -0,0 +1,32 @@
+#
+# Copyright (c) 2025, Arm Limited and Contributors. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+GIC_REVISIONS_ := 1 2 3
+ifeq ($(filter $(USE_GIC_DRIVER),$(GIC_REVISIONS_)),)
+$(error USE_GIC_DRIVER can only be one of $(GIC_REVISIONS_))
+endif
+
+ifeq (${USE_GIC_DRIVER},2)
+include drivers/arm/gic/v2/gicv2.mk
+GIC_SOURCES := ${GICV2_SOURCES} \
+ drivers/arm/gic/v2/gicv2_base.c \
+ plat/common/plat_gicv2.c
+else ifeq (${USE_GIC_DRIVER},3)
+include drivers/arm/gic/v3/gicv3.mk
+GIC_SOURCES := ${GICV3_SOURCES} \
+ drivers/arm/gic/v3/gicv3_base.c \
+ plat/common/plat_gicv3.c
+endif
+
+ifeq ($(ARCH),aarch64)
+BL31_SOURCES += ${GIC_SOURCES}
+else
+BL32_SOURCES += ${GIC_SOURCES}
+endif
+
+$(eval $(call add_defines,\
+ USE_GIC_DRIVER \
+))
diff --git a/plat/arm/common/arm_gicv2.c b/drivers/arm/gic/v2/gicv2_base.c
similarity index 74%
rename from plat/arm/common/arm_gicv2.c
rename to drivers/arm/gic/v2/gicv2_base.c
index 80a845f..317375f 100644
--- a/plat/arm/common/arm_gicv2.c
+++ b/drivers/arm/gic/v2/gicv2_base.c
@@ -1,24 +1,19 @@
/*
- * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/gicv2.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv2 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
+#if USE_GIC_DRIVER != 2
+#error "This file should only be used with GENERIC_GIC_DRIVER=2"
+#endif
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
@@ -43,23 +38,16 @@
/******************************************************************************
* ARM common helper to initialize the GICv2 only driver.
*****************************************************************************/
-void plat_arm_gic_driver_init(void)
+void __init gic_init(unsigned int cpu_idx)
{
gicv2_driver_init(&arm_gic_data);
-}
-
-void plat_arm_gic_init(void)
-{
gicv2_distif_init();
- gicv2_pcpu_distif_init();
- gicv2_set_pe_target_mask(plat_my_core_pos());
- gicv2_cpuif_enable();
}
/******************************************************************************
* ARM common helper to enable the GICv2 CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
{
gicv2_cpuif_enable();
}
@@ -67,7 +55,7 @@
/******************************************************************************
* ARM common helper to disable the GICv2 CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
{
gicv2_cpuif_disable();
}
@@ -75,7 +63,7 @@
/******************************************************************************
* ARM common helper to initialize the per cpu distributor interface in GICv2
*****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
{
gicv2_pcpu_distif_init();
gicv2_set_pe_target_mask(plat_my_core_pos());
@@ -85,29 +73,23 @@
* Stubs for Redistributor power management. Although GICv2 doesn't have
* Redistributor interface, these are provided for the sake of uniform GIC API
*****************************************************************************/
-void plat_arm_gic_redistif_on(void)
-{
- return;
-}
-
-void plat_arm_gic_redistif_off(void)
+void gic_pcpu_off(unsigned int cpu_idx)
{
return;
}
-
/******************************************************************************
* ARM common helper to save & restore the GICv3 on resume from system suspend.
* The normal world currently takes care of saving and restoring the GICv2
* registers due to legacy reasons. Hence we just initialize the Distributor
* on resume from system suspend.
*****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
{
return;
}
-void plat_arm_gic_resume(void)
+void gic_resume(void)
{
gicv2_distif_init();
gicv2_pcpu_distif_init();
diff --git a/plat/arm/common/arm_gicv3.c b/drivers/arm/gic/v3/gicv3_base.c
similarity index 81%
rename from plat/arm/common/arm_gicv3.c
rename to drivers/arm/gic/v3/gicv3_base.c
index 180da2f..f6f4acf 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/drivers/arm/gic/v3/gicv3_base.c
@@ -9,25 +9,18 @@
#include <common/debug.h>
#include <common/interrupt_props.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/gicv3.h>
#include <lib/utils.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
-/******************************************************************************
- * The following functions are defined as weak to allow a platform to override
- * the way the GICv3 driver is initialised and used.
- *****************************************************************************/
-#pragma weak plat_arm_gic_driver_init
-#pragma weak plat_arm_gic_init
-#pragma weak plat_arm_gic_cpuif_enable
-#pragma weak plat_arm_gic_cpuif_disable
-#pragma weak plat_arm_gic_pcpu_init
-#pragma weak plat_arm_gic_redistif_on
-#pragma weak plat_arm_gic_redistif_off
+#if USE_GIC_DRIVER != 3
+#error "This file should only be used with GENERIC_GIC_DRIVER=3"
+#endif
/* The GICv3 driver only needs to be initialized in EL3 */
-static uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
+uintptr_t rdistif_base_addrs[PLATFORM_CORE_COUNT];
/* Default GICR base address to be used for GICR probe. */
static const uintptr_t gicr_base_addrs[2] = {
@@ -79,7 +72,7 @@
return plat_arm_calc_core_pos(mpidr);
}
-gicv3_driver_data_t arm_gic_data __unused = {
+gicv3_driver_data_t gic_data __unused = {
.gicd_base = PLAT_ARM_GICD_BASE,
.gicr_base = 0U,
.interrupt_props = arm_interrupt_props,
@@ -101,7 +94,10 @@
gicr_frames = plat_gicr_frames;
}
-void __init plat_arm_gic_driver_init(void)
+/******************************************************************************
+ * ARM common helper to initialize the GIC. Only invoked by BL31
+ *****************************************************************************/
+void __init gic_init(unsigned int cpu_idx)
{
/*
* The GICv3 driver is initialized in EL3 and does not need
@@ -111,39 +107,25 @@
*/
#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
(defined(__aarch64__) && defined(IMAGE_BL31))
- gicv3_driver_init(&arm_gic_data);
-
- if (gicv3_rdistif_probe(gicr_base_addrs[0]) == -1) {
- ERROR("No GICR base frame found for Primary CPU\n");
- panic();
- }
+ gicv3_driver_init(&gic_data);
#endif
-}
-
-/******************************************************************************
- * ARM common helper to initialize the GIC. Only invoked by BL31
- *****************************************************************************/
-void __init plat_arm_gic_init(void)
-{
gicv3_distif_init();
- gicv3_rdistif_init(plat_my_core_pos());
- gicv3_cpuif_enable(plat_my_core_pos());
}
/******************************************************************************
* ARM common helper to enable the GIC CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_enable(void)
+void gic_cpuif_enable(unsigned int cpu_idx)
{
- gicv3_cpuif_enable(plat_my_core_pos());
+ gicv3_cpuif_enable(cpu_idx);
}
/******************************************************************************
* ARM common helper to disable the GIC CPU interface
*****************************************************************************/
-void plat_arm_gic_cpuif_disable(void)
+void gic_cpuif_disable(unsigned int cpu_idx)
{
- gicv3_cpuif_disable(plat_my_core_pos());
+ gicv3_cpuif_disable(cpu_idx);
}
/******************************************************************************
@@ -151,7 +133,7 @@
* corresponding per-cpu redistributor frame as well as initialize the
* corresponding interface in GICv3.
*****************************************************************************/
-void plat_arm_gic_pcpu_init(void)
+void gic_pcpu_init(unsigned int cpu_idx)
{
int result;
const uintptr_t *plat_gicr_frames = gicr_frames;
@@ -170,26 +152,22 @@
ERROR("No GICR base frame found for CPU 0x%lx\n", read_mpidr());
panic();
}
- gicv3_rdistif_init(plat_my_core_pos());
+ gicv3_rdistif_init(cpu_idx);
}
/******************************************************************************
* ARM common helpers to power GIC redistributor interface
*****************************************************************************/
-void plat_arm_gic_redistif_on(void)
-{
- gicv3_rdistif_on(plat_my_core_pos());
-}
-
-void plat_arm_gic_redistif_off(void)
+void gic_pcpu_off(unsigned int cpu_idx)
{
- gicv3_rdistif_off(plat_my_core_pos());
+ gicv3_rdistif_off(cpu_idx);
}
/******************************************************************************
- * ARM common helper to save & restore the GICv3 on resume from system suspend
+ * Common helper to save & restore the GICv3 on resume from system suspend. It
+ * is the platform's responsibility to call these.
*****************************************************************************/
-void plat_arm_gic_save(void)
+void gic_save(void)
{
gicv3_redist_ctx_t * const rdist_context =
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
@@ -222,7 +200,7 @@
*/
}
-void plat_arm_gic_resume(void)
+void gic_resume(void)
{
const gicv3_redist_ctx_t *rdist_context =
(gicv3_redist_ctx_t *)LOAD_ADDR_OF(rdist_ctx);
diff --git a/include/drivers/arm/gic.h b/include/drivers/arm/gic.h
new file mode 100644
index 0000000..e98737a
--- /dev/null
+++ b/include/drivers/arm/gic.h
@@ -0,0 +1,18 @@
+/*
+ * Copyright (c) 2024-2025, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef GIC_H
+#define GIC_H
+/* the function names conflict with some platform implementations. */
+#if USE_GIC_DRIVER
+void gic_init(unsigned int cpu_idx);
+void gic_cpuif_enable(unsigned int cpu_idx);
+void gic_cpuif_disable(unsigned int cpu_idx);
+void gic_pcpu_off(unsigned int cpu_idx);
+void gic_pcpu_init(unsigned int cpu_idx);
+void gic_save(void);
+void gic_resume(void);
+#endif
+#endif /* GIC_H */
diff --git a/include/plat/arm/common/plat_arm.h b/include/plat/arm/common/plat_arm.h
index ae2e96f..4a856a7 100644
--- a/include/plat/arm/common/plat_arm.h
+++ b/include/plat/arm/common/plat_arm.h
@@ -10,6 +10,7 @@
#include <stdint.h>
#include <common/desc_image_load.h>
+#include <drivers/arm/gic.h>
#include <drivers/arm/tzc_common.h>
#include <lib/bakery_lock.h>
#include <lib/cassert.h>
@@ -358,6 +359,9 @@
* Mandatory functions required in ARM standard platforms
*/
unsigned int plat_arm_get_cluster_core_count(u_register_t mpidr);
+
+/* should not be used, but keep for compatibility */
+#if USE_GIC_DRIVER == 0
void plat_arm_gic_driver_init(void);
void plat_arm_gic_init(void);
void plat_arm_gic_cpuif_enable(void);
@@ -367,6 +371,7 @@
void plat_arm_gic_pcpu_init(void);
void plat_arm_gic_save(void);
void plat_arm_gic_resume(void);
+#endif
void plat_arm_security_setup(void);
void plat_arm_pwrc_setup(void);
void plat_arm_interconnect_init(void);
diff --git a/lib/psci/psci_off.c b/lib/psci/psci_off.c
index 932a039..2485601 100644
--- a/lib/psci/psci_off.c
+++ b/lib/psci/psci_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2023, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -11,6 +11,7 @@
#include <arch.h>
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <lib/pmf/pmf.h>
#include <lib/runtime_instr.h>
#include <plat/common/platform.h>
@@ -117,6 +118,13 @@
*/
psci_pwrdown_cpu_start(psci_find_max_off_lvl(&state_info));
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(idx);
+ /* we don't want any wakeups until explicitly turned on */
+ gic_pcpu_off(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Plat. management: Perform platform specific actions to turn this
* cpu off e.g. exit cpu coherency, program the power controller etc.
diff --git a/lib/psci/psci_on.c b/lib/psci/psci_on.c
index 1bbea7a..4ae07e1 100644
--- a/lib/psci/psci_on.c
+++ b/lib/psci/psci_on.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -11,6 +11,7 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/pubsub_events.h>
#include <plat/common/platform.h>
@@ -183,6 +184,13 @@
if (psci_plat_pm_ops->pwr_domain_on_finish_late != NULL) {
psci_plat_pm_ops->pwr_domain_on_finish_late(state_info);
}
+
+#if USE_GIC_DRIVER
+ /* GIC init after platform has had a say with MMU on */
+ gic_pcpu_init(cpu_idx);
+ gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* All the platform specific actions for turning this cpu
* on have completed. Perform enough arch.initialization
diff --git a/lib/psci/psci_suspend.c b/lib/psci/psci_suspend.c
index a7b53cb..73b9a67 100644
--- a/lib/psci/psci_suspend.c
+++ b/lib/psci/psci_suspend.c
@@ -12,6 +12,7 @@
#include <common/bl_common.h>
#include <common/debug.h>
#include <context.h>
+#include <drivers/arm/gic.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/el3_runtime/cpu_data.h>
#include <lib/el3_runtime/pubsub_events.h>
@@ -198,13 +199,17 @@
psci_suspend_to_pwrdown_start(idx, end_pwrlvl, end_pwrlvl, state_info);
}
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Plat. management: Allow the platform to perform the
* necessary actions to turn off this cpu e.g. set the
* platform defined mailbox with the psci entrypoint,
* program the power controller etc.
*/
-
psci_plat_pm_ops->pwr_domain_suspend(state_info);
#if ENABLE_PSCI_STAT
@@ -280,6 +285,11 @@
psci_cpu_suspend_to_standby_finish(end_pwrlvl, state_info);
}
+#if USE_GIC_DRIVER
+ /* Turn GIC on after platform has had a chance to do state management */
+ gic_cpuif_enable(idx);
+#endif /* USE_GIC_DRIVER */
+
/*
* Set the requested and target state of this CPU and all the higher
* power domain levels for this CPU to run.
@@ -320,6 +330,11 @@
psci_do_pwrup_cache_maintenance();
#endif
+#if USE_GIC_DRIVER
+ /* GIC on after platform has had its say and MMU is on */
+ gic_cpuif_enable(cpu_idx);
+#endif /* USE_GIC_DRIVER */
+
/* Re-init the cntfrq_el0 register */
counter_freq = plat_get_syscnt_freq2();
write_cntfrq_el0(counter_freq);
diff --git a/lib/psci/psci_system_off.c b/lib/psci/psci_system_off.c
index 1dcaa23..19f2476 100644
--- a/lib/psci/psci_system_off.c
+++ b/lib/psci/psci_system_off.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2025, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -9,6 +9,7 @@
#include <arch_helpers.h>
#include <common/debug.h>
+#include <drivers/arm/gic.h>
#include <drivers/console.h>
#include <plat/common/platform.h>
@@ -27,6 +28,11 @@
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
/* Call the platform specific hook */
psci_plat_pm_ops->system_off();
@@ -46,6 +52,11 @@
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
/* Call the platform specific hook */
psci_plat_pm_ops->system_reset();
@@ -80,6 +91,11 @@
}
console_flush();
+#if USE_GIC_DRIVER
+ /* turn the GIC off before we hand off to the platform */
+ gic_cpuif_disable(plat_my_core_pos());
+#endif /* USE_GIC_DRIVER */
+
u_register_t ret =
(u_register_t) psci_plat_pm_ops->system_reset2((int) is_vendor, reset_type, cookie);
if (ret != PSCI_E_SUCCESS)
diff --git a/make_helpers/defaults.mk b/make_helpers/defaults.mk
index 965698b..f438a9d 100644
--- a/make_helpers/defaults.mk
+++ b/make_helpers/defaults.mk
@@ -156,6 +156,9 @@
# default, they are for Secure EL1.
GICV2_G0_FOR_EL3 := 0
+# Generic implementation of a GICvX driver
+USE_GIC_DRIVER := 0
+
# Route NS External Aborts to EL3. Disabled by default; External Aborts are handled
# by lower ELs.
HANDLE_EA_EL3_FIRST_NS := 0
diff --git a/plat/arm/board/fvp/fvp_gicv3.c b/plat/arm/board/fvp/fvp_gicv3.c
index fe64bec..aa99d7d 100644
--- a/plat/arm/board/fvp/fvp_gicv3.c
+++ b/plat/arm/board/fvp/fvp_gicv3.c
@@ -69,7 +69,7 @@
void fvp_gic_driver_pre_init(void)
{
/* FCONF won't be used in these cases, so we couldn't do this */
-#if !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN)
+#if !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2)
/*
* Get GICD and GICR base addressed through FCONF APIs.
* FCONF is not supported in BL32 for FVP.
@@ -97,5 +97,5 @@
arm_gic_data.interrupt_props_num = ARRAY_SIZE(fvp_interrupt_props);
#endif
plat_arm_override_gicr_frames(fvp_gicr_base_addrs);
-#endif /* !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN) */
+#endif /* !(BL2_AT_EL3 || RESET_TO_BL31 || RESET_TO_SP_MIN || RESET_TO_BL2) */
}
diff --git a/plat/arm/common/sp_min/arm_sp_min_setup.c b/plat/arm/common/sp_min/arm_sp_min_setup.c
index cc4ae59..6b15b73 100644
--- a/plat/arm/common/sp_min/arm_sp_min_setup.c
+++ b/plat/arm/common/sp_min/arm_sp_min_setup.c
@@ -207,8 +207,11 @@
struct transfer_list_entry *te __unused;
/* Initialize the GIC driver, cpu and distributor interfaces */
- plat_arm_gic_driver_init();
- plat_arm_gic_init();
+ unsigned int core_pos = plat_my_core_pos();
+
+ gic_init(core_pos);
+ gic_pcpu_init(core_pos);
+ gic_cpuif_enable(core_pos);
#if TRANSFER_LIST
ns_tl = transfer_list_ensure((void *)FW_NS_HANDOFF_BASE,