tree 9bb050fb8c602739acfec3e3f3955ccbf2020dfe
parent 0f164bb45189f482ad67c2853ccfcbe5cf622d94
author Andre Przywara <andre.przywara@arm.com> 1539513941 +0100
committer Andre Przywara <andre.przywara@arm.com> 1540049039 +0100

allwinner: Prepare for executing code on the management processor

The more recent Allwinner SoCs contain an OpenRISC management
controller (called arisc or CPUS), which shares the bus with the ARM cores,
but runs on a separate power domain. This is meant to handle power
management with the ARM cores off.
There are efforts to run sophisticated firmware on that core
(communicating via SCPI with the ARM world), but for now can use it for
the rather simple task of helping to turn the ARM cores off. As this
cannot be done by ARM code itself (because execution stops at the
first of the three required steps), we can offload some instructions to
this management processor.
This introduces a helper function to hand over a bunch of instructions
and triggers execution. We introduce a bakery lock to avoid two cores
trying to use that (single) arisc core. The arisc code is expected to
put itself into reset after is has finished execution.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>