stm32mp1: Add clock and reset support
The clock driver is under dual license, BSD and GPLv2.
The clock driver uses device tree, so a minimal support for this is added.
The required files for driver and DTS files are in include/dt-bindings/.
Signed-off-by: Yann Gautier <yann.gautier@st.com>
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Lionel Debieve <lionel.debieve@st.com>
diff --git a/drivers/st/reset/stm32mp1_reset.c b/drivers/st/reset/stm32mp1_reset.c
new file mode 100644
index 0000000..106bbfe
--- /dev/null
+++ b/drivers/st/reset/stm32mp1_reset.c
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <bl_common.h>
+#include <debug.h>
+#include <limits.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <stm32mp1_rcc.h>
+#include <stm32mp1_reset.h>
+#include <utils_def.h>
+
+#define RST_CLR_OFFSET 4U
+
+void stm32mp1_reset_assert(uint32_t id)
+{
+ uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
+ uint32_t bit = id % (uint32_t)__LONG_BIT;
+
+ mmio_write_32(RCC_BASE + offset, BIT(bit));
+ while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) {
+ ;
+ }
+}
+
+void stm32mp1_reset_deassert(uint32_t id)
+{
+ uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
+ RST_CLR_OFFSET;
+ uint32_t bit = id % (uint32_t)__LONG_BIT;
+
+ mmio_write_32(RCC_BASE + offset, BIT(bit));
+ while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) {
+ ;
+ }
+}