Merge changes from topic "mb/mb-signer-id" into integration
* changes:
feat(qemu): add dummy plat_mboot_measure_key() function
docs(rss): update RSS doc for signer-ID
feat(imx): add dummy 'plat_mboot_measure_key' function
feat(tc): implement platform function to measure and publish Public Key
feat(auth): measure and publicise the Public Key
feat(fvp): implement platform function to measure and publish Public Key
feat(fvp): add public key-OID information in RSS metadata structure
feat(auth): add explicit entries for key OIDs
feat(rss): set the signer-ID in the RSS metadata
feat(auth): create a zero-OID for Subject Public Key
docs: add details about plat_mboot_measure_key function
feat(measured-boot): introduce platform function to measure and publish Public Key
diff --git a/.readthedocs.yaml b/.readthedocs.yaml
index 6207066..e3a7ebf 100644
--- a/.readthedocs.yaml
+++ b/.readthedocs.yaml
@@ -24,3 +24,8 @@
sphinx:
configuration: docs/conf.py
+
+# Auxiliary formats to export to (in addition to the default HTML output).
+formats:
+ - pdf
+
diff --git a/changelog.yaml b/changelog.yaml
index 47cfc1e..3534cb0 100644
--- a/changelog.yaml
+++ b/changelog.yaml
@@ -628,6 +628,13 @@
- plat/zynqmp
- plat/xilinx/zynqmp
+ - title: Nuvoton
+ scope: nuvoton
+
+ subsections:
+ - title: npcm845x
+ scope: npcm845x
+
- title: Bootloader Images
scope: bl
diff --git a/docs/about/maintainers.rst b/docs/about/maintainers.rst
index 3de09c7..20c56fd 100644
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -585,6 +585,20 @@
:|F|: drivers/marvell/
:|F|: tools/marvell/
+Nuvoton npcm845x platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:|M|: Hila Miranda-Kuzi <hila.miranda.kuzi1@gmail.com>
+:|G|: `hilamirandakuzi1`_
+:|M|: Margarita Glushkin <rutigl@gmail.com>
+:|G|: `rutigl`_
+:|M|: Avi Fishman <avi.fishman@nuvoton.com>
+:|G|: `avifishman`_
+:|F|: docs/plat/npcm845x.rst
+:|F|: drivers/nuvoton/
+:|F|: include/drivers/nuvoton/
+:|F|: include/plat/nuvoton/
+:|F|: plat/nuvoton/
+
NVidia platform ports
^^^^^^^^^^^^^^^^^^^^^
:|M|: Varun Wadekar <vwadekar@nvidia.com>
@@ -1002,3 +1016,6 @@
.. _Neal-liu: https://github.com/neal-liu
.. _amit-nagal: https://github.com/amit-nagal
.. _Akshay-Belsare: https://github.com/Akshay-Belsare
+.. _hilamirandakuzi1: https://github.com/hilamirandakuzi1
+.. _rutigl: https://github.com/rutigl
+.. _avifishman: https://github.com/avifishman
diff --git a/docs/components/realm-management-extension.rst b/docs/components/realm-management-extension.rst
index 919eea5..f228e6b 100644
--- a/docs/components/realm-management-extension.rst
+++ b/docs/components/realm-management-extension.rst
@@ -157,7 +157,7 @@
git clone https://git.trustedfirmware.org/TF-A/tf-a-tests.git
cd tf-a-tests
- make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 all pack_realm
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=fvp DEBUG=1 ENABLE_REALM_PAYLOAD_TESTS=1 all
This produces a TF-A Tests binary (**tftf.bin**) with Realm payload packaged
and **sp_layout.json** in the **build/fvp/debug** directory.
diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst
index df0cfc0..bb12d7d 100644
--- a/docs/design/cpu-specific-build-macros.rst
+++ b/docs/design/cpu-specific-build-macros.rst
@@ -601,47 +601,50 @@
For Neoverse N2, the following errata build flags are defined :
- ``ERRATA_N2_2002655``: This applies errata 2002655 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2067956``: This applies errata 2067956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2025414``: This applies errata 2025414 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2189731``: This applies errata 2189731 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138956``: This applies errata 2138956 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138953``: This applies errata 2138953 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revisions r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2242415``: This applies errata 2242415 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2138958``: This applies errata 2138958 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2242400``: This applies errata 2242400 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2280757``: This applies errata 2280757 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU and is still open.
+ CPU. This needs to be enabled for revision r0p0 of the CPU and is fixed in r0p1.
- ``ERRATA_N2_2326639``: This applies errata 2326639 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
- ``ERRATA_N2_2376738``: This applies errata 2376738 workaround to Neoverse-N2
- CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
- r0p1.
+ CPU. This needs to be enabled for revision r0p0, r0p1, r0p2, r0p3 and is still open.
- ``ERRATA_N2_2388450``: This applies errata 2388450 workaround to Neoverse-N2
CPU. This needs to be enabled for revision r0p0 of the CPU, it is fixed in
r0p1.
+- ``ERRATA_N2_2743014``: This applies errata 2743014 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
- ``ERRATA_N2_2743089``: This applies errata 2743089 workaround to Neoverse-N2
CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
in r0p3.
@@ -651,6 +654,10 @@
interconnect IP. This needs to be enabled for revisions r0p0, r0p1 and r0p2.
It is fixed in r0p3.
+- ``ERRATA_N2_2779511``: This applies errata 2779511 workaround to Neoverse-N2
+ CPU. This needs to be enabled for revisions r0p0, r0p1 and r0p2. It is fixed
+ in r0p3.
+
For Cortex-X2, the following errata build flags are defined :
- ``ERRATA_X2_2002765``: This applies errata 2002765 workaround to Cortex-X2
diff --git a/docs/plat/index.rst b/docs/plat/index.rst
index fe2cc44..2eec68c 100644
--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -28,6 +28,7 @@
imx8
imx8m
imx9
+ npcm845x
nxp/index
poplar
qemu
diff --git a/docs/plat/npcm845x.rst b/docs/plat/npcm845x.rst
new file mode 100644
index 0000000..91dbfd9
--- /dev/null
+++ b/docs/plat/npcm845x.rst
@@ -0,0 +1,21 @@
+Nuvoton NPCM845X
+================
+
+Nuvoton NPCM845X is the Nuvoton Arbel NPCM8XX Board Management controller (BMC) SoC.
+
+The Nuvoton Arbel NPCM845X SoC is a fourth-generation BMC.
+The NPCM845X computing subsystem comprises a quadcore Arm Cortex-A35 CPU.
+
+This SoC includes secured components, i.e., bootblock stored in ROM,
+u-boot, OPTEE-OS, trusted-firmware-a and Linux.
+Every stage is measured and validated by the bootblock.
+This SoC was tested on the Arbel NPCM845X evaluation board.
+
+
+How to Build
+------------
+
+.. code:: shell
+
+ make CROSS_COMPILE=aarch64-none-elf- PLAT=npcm845x all SPD=opteed
+
diff --git a/drivers/arm/ethosn/ethosn_big_fw.c b/drivers/arm/ethosn/ethosn_big_fw.c
index 628f5d9..ea48a24 100644
--- a/drivers/arm/ethosn/ethosn_big_fw.c
+++ b/drivers/arm/ethosn/ethosn_big_fw.c
@@ -12,7 +12,7 @@
#define ETHOSN_BIG_FW_MAGIC ('E' | ('N' << 8) | ('F' << 16) | ('W' << 24))
/* Supported big firmware version */
-#define ETHOSN_BIG_FW_VERSION_MAJOR 11
+#define ETHOSN_BIG_FW_VERSION_MAJOR 12
#define ETHOSN_ARCH_VER_MAJOR_MASK U(0xF000)
#define ETHOSN_ARCH_VER_MAJOR_SHIFT U(0xC)
diff --git a/fdts/morello-soc.dts b/fdts/morello-soc.dts
index 61b5763..9f996bd 100644
--- a/fdts/morello-soc.dts
+++ b/fdts/morello-soc.dts
@@ -194,10 +194,12 @@
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dpu_aclk>;
- hdmi-transmitter@70 {
+ hdmi_tx: hdmi-transmitter@70 {
compatible = "nxp,tda998x";
reg = <0x70>;
video-ports = <0x234501>;
+ #sound-dai-cells = <0>;
+ audio-ports = <2 0x03>;
port {
tda998x_0_input: endpoint {
remote-endpoint = <&dp_pl0_out0>;
@@ -255,6 +257,52 @@
};
};
};
+
+ iofpga_i2s: xlnx-i2s@1c150000 {
+ #sound-dai-cells = <0>;
+ compatible = "xlnx,i2s-transmitter-1.0";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x1c150000 0x0 0x10000>;
+ xlnx,dwidth = <0x18>;
+ xlnx,num-channels = <1>;
+ };
+
+ audio_formatter: audio-formatter@1c100000 {
+ compatible = "xlnx,audio-formatter-1.0";
+ reg = <0x0 0x1c000000 0x0 0x10000>;
+ #sound-dai-cells = <0>;
+ interrupt-names = "irq_mm2s";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "s_axi_lite_aclk", "aud_mclk", "m_axis_mm2s_aclk";
+ clocks = <&soc_refclk85mhz>, <&i2s_audclk>, <&soc_refclk85mhz>;
+ };
+
+ sound {
+ compatible = "simple-audio-card";
+ simple-audio-card,format = "i2s";
+ simple-audio-card,bitclock-master = <&audio_master>;
+ simple-audio-card,frame-master = <&audio_master>;
+ audio_master: simple-audio-card,cpu {
+ sound-dai = <&iofpga_i2s>;
+ clocks = <&i2s_audclk>;
+ };
+
+ simple-audio-card,codec {
+ sound-dai = <&hdmi_tx>;
+ };
+
+ simple-audio-card,plat {
+ sound-dai = <&audio_formatter>;
+ };
+ };
+
+ i2s_audclk: i2s_audclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <12288000>;
+ clock-output-names = "iofpga:i2s_audclk";
+ };
};
&gic {
diff --git a/fdts/morello.dtsi b/fdts/morello.dtsi
index 20640c5..7f39d75 100644
--- a/fdts/morello.dtsi
+++ b/fdts/morello.dtsi
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -88,6 +88,13 @@
clock-output-names = "apb_pclk";
};
+ soc_refclk85mhz: refclk85mhz {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <85000000>;
+ clock-output-names = "iofpga:aclk";
+ };
+
soc_uartclk: uartclk {
compatible = "fixed-clock";
#clock-cells = <0>;
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_clock.h b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h
new file mode 100644
index 0000000..3c457d7
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_clock.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ARBEL_CLOCK_H_
+#define __ARBEL_CLOCK_H_
+
+struct clk_ctl {
+ unsigned int clken1;
+ unsigned int clksel;
+ unsigned int clkdiv1;
+ unsigned int pllcon0;
+ unsigned int pllcon1;
+ unsigned int swrstr;
+ unsigned char res1[0x8];
+ unsigned int ipsrst1;
+ unsigned int ipsrst2;
+ unsigned int clken2;
+ unsigned int clkdiv2;
+ unsigned int clken3;
+ unsigned int ipsrst3;
+ unsigned int wd0rcr;
+ unsigned int wd1rcr;
+ unsigned int wd2rcr;
+ unsigned int swrstc1;
+ unsigned int swrstc2;
+ unsigned int swrstc3;
+ unsigned int tiprstc;
+ unsigned int pllcon2;
+ unsigned int clkdiv3;
+ unsigned int corstc;
+ unsigned int pllcong;
+ unsigned int ahbckfi;
+ unsigned int seccnt;
+ unsigned int cntr25m;
+ unsigned int clken4;
+ unsigned int ipsrst4;
+ unsigned int busto;
+ unsigned int clkdiv4;
+ unsigned int wd0rcrb;
+ unsigned int wd1rcrb;
+ unsigned int wd2rcrb;
+ unsigned int swrstc1b;
+ unsigned int swrstc2b;
+ unsigned int swrstc3b;
+ unsigned int tiprstcb;
+ unsigned int corstcb;
+ unsigned int ipsrstdis1;
+ unsigned int ipsrstdis2;
+ unsigned int ipsrstdis3;
+ unsigned int ipsrstdis4;
+ unsigned char res2[0x10];
+ unsigned int thrtl_cnt;
+};
+
+#endif /* __ARBEL_CLOCK_H_ */
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h
new file mode 100644
index 0000000..b9f3048
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_gcr.h
@@ -0,0 +1,127 @@
+/*
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __NPCM845x_GCR_H_
+#define __NPCM845x_GCR_H_
+
+struct npcm845x_gcr {
+ unsigned int pdid;
+ unsigned int pwron;
+ unsigned int swstrps;
+ unsigned int rsvd1[2];
+ unsigned int miscpe;
+ unsigned int spldcnt;
+ unsigned int rsvd2[1];
+ unsigned int flockr2;
+ unsigned int flockr3;
+ unsigned int rsvd3[3];
+ unsigned int a35_mode;
+ unsigned int spswc;
+ unsigned int intcr;
+ unsigned int intsr;
+ unsigned int obscr1;
+ unsigned int obsdr1;
+ unsigned int rsvd4[1];
+ unsigned int hifcr;
+ unsigned int rsvd5[3];
+ unsigned int intcr2;
+ unsigned int rsvd6[1];
+ unsigned int srcnt;
+ unsigned int ressr;
+ unsigned int rlockr1;
+ unsigned int flockr1;
+ unsigned int dscnt;
+ unsigned int mdlr;
+ unsigned int scrpad_c;
+ unsigned int scrpad_b;
+ unsigned int rsvd7[4];
+ unsigned int daclvlr;
+ unsigned int intcr3;
+ unsigned int pcirctl;
+ unsigned int rsvd8[2];
+ unsigned int vsintr;
+ unsigned int rsvd9[1];
+ unsigned int sd2sur1;
+ unsigned int sd2sur2;
+ unsigned int sd2irv3;
+ unsigned int intcr4;
+ unsigned int obscr2;
+ unsigned int obsdr2;
+ unsigned int rsvd10[5];
+ unsigned int i2csegsel;
+ unsigned int i2csegctl;
+ unsigned int vsrcr;
+ unsigned int mlockr;
+ unsigned int rsvd11[8];
+ unsigned int etsr;
+ unsigned int dft1r;
+ unsigned int dft2r;
+ unsigned int dft3r;
+ unsigned int edffsr;
+ unsigned int rsvd12[1];
+ unsigned int intcrpce3;
+ unsigned int intcrpce2;
+ unsigned int intcrpce0;
+ unsigned int intcrpce1;
+ unsigned int dactest;
+ unsigned int scrpad;
+ unsigned int usb1phyctl;
+ unsigned int usb2phyctl;
+ unsigned int usb3phyctl;
+ unsigned int intsr2;
+ unsigned int intcrpce2b;
+ unsigned int intcrpce0b;
+ unsigned int intcrpce1b;
+ unsigned int intcrpce3b;
+ unsigned int rsvd13[4];
+ unsigned int intcrpce2c;
+ unsigned int intcrpce0c;
+ unsigned int intcrpce1c;
+ unsigned int intcrpce3c;
+ unsigned int rsvd14[40];
+ unsigned int sd2irv4;
+ unsigned int sd2irv5;
+ unsigned int sd2irv6;
+ unsigned int sd2irv7;
+ unsigned int sd2irv8;
+ unsigned int sd2irv9;
+ unsigned int sd2irv10;
+ unsigned int sd2irv11;
+ unsigned int rsvd15[8];
+ unsigned int mfsel1;
+ unsigned int mfsel2;
+ unsigned int mfsel3;
+ unsigned int mfsel4;
+ unsigned int mfsel5;
+ unsigned int mfsel6;
+ unsigned int mfsel7;
+ unsigned int rsvd16[1];
+ unsigned int mfsel_lk1;
+ unsigned int mfsel_lk2;
+ unsigned int mfsel_lk3;
+ unsigned int mfsel_lk4;
+ unsigned int mfsel_lk5;
+ unsigned int mfsel_lk6;
+ unsigned int mfsel_lk7;
+ unsigned int rsvd17[1];
+ unsigned int mfsel_set1;
+ unsigned int mfsel_set2;
+ unsigned int mfsel_set3;
+ unsigned int mfsel_set4;
+ unsigned int mfsel_set5;
+ unsigned int mfsel_set6;
+ unsigned int mfsel_set7;
+ unsigned int rsvd18[1];
+ unsigned int mfsel_clr1;
+ unsigned int mfsel_clr2;
+ unsigned int mfsel_clr3;
+ unsigned int mfsel_clr4;
+ unsigned int mfsel_clr5;
+ unsigned int mfsel_clr6;
+ unsigned int mfsel_clr7;
+};
+
+#endif
diff --git a/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h
new file mode 100644
index 0000000..8962b90
--- /dev/null
+++ b/include/drivers/nuvoton/npcm845x/npcm845x_lpuart.h
@@ -0,0 +1,230 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __ASM_ARCH_UART_H_
+#define __ASM_ARCH_UART_H_
+
+#ifndef __ASSEMBLY__
+
+struct npcmX50_uart {
+ union {
+ unsigned int rbr;
+ unsigned int thr;
+ unsigned int dll;
+ };
+ union {
+ unsigned int ier;
+ unsigned int dlm;
+ };
+ union {
+ unsigned int iir;
+ unsigned int fcr;
+ };
+ unsigned int lcr;
+ unsigned int mcr;
+ unsigned int lsr;
+ unsigned int msr;
+ unsigned int tor;
+};
+
+typedef enum {
+ /*
+ * UART0 is a general UART block without modem-I/O-control
+ * connection to external signals.
+ */
+ UART0_DEV = 0,
+ /*
+ * UART1-3 are each a general UART with modem-I/O-control
+ * connection to external signals.
+ */
+ UART1_DEV,
+ UART2_DEV,
+ UART3_DEV,
+} UART_DEV_T;
+
+typedef enum {
+ /*
+ * 0 0 0: Mode 1:
+ * HSP1 connected to SI2,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 snoops SI2
+ */
+ UART_MUX_MODE1 = 0,
+ /*
+ * 0 0 1: Mode 2:
+ * HSP1 connected to UART1,
+ * HSP2 connected to SI2,
+ * UART2 snoops HSP2,
+ * UART3 snoops SI2
+ */
+ UART_MUX_MODE2,
+ /*
+ * 0 1 0: Mode 3:
+ * HSP1 connected to UART1,
+ * HSP2 connected to UART2,
+ * UART3 connected to SI2
+ */
+ UART_MUX_MODE3,
+ /*
+ * 0 1 1: Mode 4:
+ * HSP1 connected to SI1,
+ * HSP2 connected to SI2,
+ * UART1 snoops SI1,
+ * UART3 snoops SI2,
+ * UART2 snoops HSP1 (default)
+ */
+ UART_MUX_MODE4,
+ /*
+ * 1 0 0: Mode 5:
+ * HSP1 connected to SI1,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 snoops SI1
+ */
+ UART_MUX_MODE5,
+ /*
+ * 1 0 1: Mode 6:
+ * HSP1 connected to SI1,
+ * HSP2 connected to SI2,
+ * UART1 snoops SI1,
+ * UART3 snoops SI2,
+ * UART2 snoops HSP2
+ */
+ UART_MUX_MODE6,
+ /*
+ * 1 1 0: Mode 7:
+ * HSP1 connected to SI1,
+ * HSP2 connected to UART2,
+ * UART1 snoops HSP1,
+ * UART3 connected to SI2
+ */
+ UART_MUX_MODE7,
+ /* Skip UART mode configuration. */
+ UART_MUX_RESERVED,
+ /*
+ * A SW option to allow config of UART
+ * without touching the UART mux.
+ */
+ UART_MUX_SKIP_CONFIG
+} UART_MUX_T;
+
+/*---------------------------------------------------------------------------*/
+/* Common baudrate definitions */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_BAUDRATE_110 = 110,
+ UART_BAUDRATE_300 = 300,
+ UART_BAUDRATE_600 = 600,
+ UART_BAUDRATE_1200 = 1200,
+ UART_BAUDRATE_2400 = 2400,
+ UART_BAUDRATE_4800 = 4800,
+ UART_BAUDRATE_9600 = 9600,
+ UART_BAUDRATE_14400 = 14400,
+ UART_BAUDRATE_19200 = 19200,
+ UART_BAUDRATE_38400 = 38400,
+ UART_BAUDRATE_57600 = 57600,
+ UART_BAUDRATE_115200 = 115200,
+ UART_BAUDRATE_230400 = 230400,
+ UART_BAUDRATE_380400 = 380400,
+ UART_BAUDRATE_460800 = 460800,
+} UART_BAUDRATE_T;
+
+/*---------------------------------------------------------------------------*/
+/* UART parity types */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_PARITY_NONE = 0,
+ UART_PARITY_EVEN,
+ UART_PARITY_ODD,
+} UART_PARITY_T;
+
+/*---------------------------------------------------------------------------*/
+/* Uart stop bits */
+/*---------------------------------------------------------------------------*/
+typedef enum {
+ UART_STOPBIT_1 = 0x00,
+ UART_STOPBIT_DYNAMIC,
+} UART_STOPBIT_T;
+
+enum FCR_RFITL_TYPE {
+ FCR_RFITL_1B = 0x0,
+ FCR_RFITL_4B = 0x4,
+ FCR_RFITL_8B = 0x8,
+ FCR_RFITL_14B = 0xC,
+};
+
+enum LCR_WLS_TYPE {
+ LCR_WLS_5bit = 0x0,
+ LCR_WLS_6bit = 0x1,
+ LCR_WLS_7bit = 0x2,
+ LCR_WLS_8bit = 0x3,
+};
+
+#define IER_DBGACK (1 << 4)
+#define IER_MSIE (1 << 3)
+#define IER_RLSE (1 << 2)
+#define IER_THREIE (1 << 1)
+#define IER_RDAIE (1 << 0)
+
+#define IIR_FMES (1 << 7)
+#define IIR_RFTLS (1 << 5)
+#define IIR_DMS (1 << 4)
+#define IIR_IID (1 << 1)
+#define IIR_NIP (1 << 0)
+
+#define FCR_RFITL_1B (0 << 4)
+#define FCR_RFITL_4B (4 << 4)
+#define FCR_RFITL_8B (8 << 4)
+#define FCR_RFITL_14B (12 << 4)
+#define FCR_DMS (1 << 3)
+#define FCR_TFR (1 << 2)
+#define FCR_RFR (1 << 1)
+#define FCR_FME (1 << 0)
+
+#define LCR_DLAB (1 << 7)
+#define LCR_BCB (1 << 6)
+#define LCR_SPE (1 << 5)
+#define LCR_EPS (1 << 4)
+#define LCR_PBE (1 << 3)
+#define LCR_NSB (1 << 2)
+#define LCR_WLS_8b (3 << 0)
+#define LCR_WLS_7b (2 << 0)
+#define LCR_WLS_6b (1 << 0)
+#define LCR_WLS_5b (0 << 0)
+
+#define MCR_LBME (1 << 4)
+#define MCR_OUT2 (1 << 3)
+#define MCR_RTS (1 << 1)
+#define MCR_DTR (1 << 0)
+
+#define LSR_ERR_RX (1 << 7)
+#define LSR_TE (1 << 6)
+#define LSR_THRE (1 << 5)
+#define LSR_BII (1 << 4)
+#define LSR_FEI (1 << 3)
+#define LSR_PEI (1 << 2)
+#define LSR_OEI (1 << 1)
+#define LSR_RFDR (1 << 0)
+
+#define MSR_DCD (1 << 7)
+#define MSR_RI (1 << 6)
+#define MSR_DSR (1 << 5)
+#define MSR_CTS (1 << 4)
+#define MSR_DDCD (1 << 3)
+#define MSR_DRI (1 << 2)
+#define MSR_DDSR (1 << 1)
+#define MSR_DCTS (1 << 0)
+
+#endif /* __ASSEMBLY__ */
+
+uintptr_t npcm845x_get_base_uart(UART_DEV_T dev);
+void CLK_ResetUART(void);
+int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate);
+
+#endif /* __ASM_ARCH_UART_H_ */
diff --git a/include/lib/cpus/aarch64/cortex_a510.h b/include/lib/cpus/aarch64/cortex_a510.h
index 6af85a8..337aac3 100644
--- a/include/lib/cpus/aarch64/cortex_a510.h
+++ b/include/lib/cpus/aarch64/cortex_a510.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2022-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -14,11 +14,13 @@
******************************************************************************/
#define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19)
+#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1)
#define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1)
#define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23)
#define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46)
#define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2)
-#define CORTEX_A510_CPUECTLR_EL1_ATOM U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38)
+#define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3)
/*******************************************************************************
* CPU Power Control register specific definitions
@@ -30,6 +32,12 @@
* Complex auxiliary control register specific definitions
******************************************************************************/
#define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25)
+#define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10)
+#define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2)
/*******************************************************************************
* Auxiliary control register specific definitions
@@ -37,5 +45,11 @@
#define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0
#define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17)
#define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18)
+#define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1)
-#endif /* CORTEX_A510_H */
\ No newline at end of file
+#endif /* CORTEX_A510_H */
diff --git a/include/lib/cpus/aarch64/cortex_a76.h b/include/lib/cpus/aarch64/cortex_a76.h
index 74fb6e9..b2ec8aa 100644
--- a/include/lib/cpus/aarch64/cortex_a76.h
+++ b/include/lib/cpus/aarch64/cortex_a76.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -36,6 +36,7 @@
#define CORTEX_A76_CPUACTLR2_EL1 S3_0_C15_C1_1
#define CORTEX_A76_CPUACTLR2_EL1_BIT_2 (ULL(1) << 2)
+#define CORTEX_A76_CPUACTLR2_EL1_BIT_59 (ULL(1) << 59)
#define CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE (ULL(1) << 16)
diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
index 404b7f9..d945d7c 100644
--- a/include/lib/cpus/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -444,6 +444,19 @@
.endm
/*
+ * BFI : Inserts bitfield into a system register.
+ *
+ * BFI{cond} Rd, Rn, #lsb, #width
+ */
+.macro sysreg_bitfield_insert _reg:req, _src:req, _lsb:req, _width:req
+ /* Source value for BFI */
+ mov x1, #\_src
+ mrs x0, \_reg
+ bfi x0, x1, #\_lsb, #\_width
+ msr \_reg, x0
+.endm
+
+/*
* Apply erratum
*
* _cpu:
diff --git a/include/lib/cpus/aarch64/neoverse_n2.h b/include/lib/cpus/aarch64/neoverse_n2.h
index cb1be5b..0d50854 100644
--- a/include/lib/cpus/aarch64/neoverse_n2.h
+++ b/include/lib/cpus/aarch64/neoverse_n2.h
@@ -43,9 +43,17 @@
#define NEOVERSE_N2_CPUACTLR2_EL1_BIT_40 (ULL(1) << 40)
/*******************************************************************************
+ * CPU Auxiliary Control register 3 specific definitions.
+ ******************************************************************************/
+#define NEOVERSE_N2_CPUACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_N2_CPUACTLR3_EL1_BIT_47 (ULL(1) << 47)
+
+/*******************************************************************************
* CPU Auxiliary Control register 5 specific definitions.
******************************************************************************/
#define NEOVERSE_N2_CPUACTLR5_EL1 S3_0_C15_C8_0
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_56 (ULL(1) << 56)
+#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_55 (ULL(1) << 55)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_44 (ULL(1) << 44)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_13 (ULL(1) << 13)
#define NEOVERSE_N2_CPUACTLR5_EL1_BIT_17 (ULL(1) << 17)
diff --git a/include/lib/cpus/aarch64/neoverse_v1.h b/include/lib/cpus/aarch64/neoverse_v1.h
index 3d48623..1bb6243 100644
--- a/include/lib/cpus/aarch64/neoverse_v1.h
+++ b/include/lib/cpus/aarch64/neoverse_v1.h
@@ -42,7 +42,10 @@
#define NEOVERSE_V1_ACTLR2_EL1_BIT_40 (ULL(1) << 40)
#define NEOVERSE_V1_ACTLR3_EL1 S3_0_C15_C1_2
+#define NEOVERSE_V1_ACTLR3_EL1_BIT_47 (ULL(1) << 47)
#define NEOVERSE_V1_ACTLR5_EL1 S3_0_C15_C9_0
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_55 (ULL(1) << 55)
+#define NEOVERSE_V1_ACTLR5_EL1_BIT_56 (ULL(1) << 56)
#endif /* NEOVERSE_V1_H */
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index bf1f93a..9426ac7 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -782,6 +782,9 @@
#define PLAT_SDEI_CRITICAL_PRI 0x60
#define PLAT_SDEI_NORMAL_PRI 0x70
+/* CPU Fault Handling Interrupt(FHI) PPI interrupt ID */
+#define PLAT_CORE_FAULT_IRQ 17
+
/* ARM platforms use 3 upper bits of secure interrupt priority */
#define PLAT_PRI_BITS 3
diff --git a/include/plat/nuvoton/common/npcm845x_arm_def.h b/include/plat/nuvoton/common/npcm845x_arm_def.h
new file mode 100644
index 0000000..faddb88
--- /dev/null
+++ b/include/plat/nuvoton/common/npcm845x_arm_def.h
@@ -0,0 +1,576 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NPCM845x_ARM_DEF_H
+#define NPCM845x_ARM_DEF_H
+
+#include <arch.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+
+/* This flag will add zones to the MMU so that it will be possible to debug */
+#ifdef NPCM845X_DEBUG
+#define ALLOW_DEBUG_MMU
+#undef ALLOW_DEBUG_MMU
+#endif /* NPCM845X_DEBUG */
+
+#undef CONFIG_TARGET_ARBEL_PALLADIUM
+/******************************************************************************
+ * Definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/*
+ * Root of trust key hash lengths
+ */
+#define ARM_ROTPK_HEADER_LEN 19
+#define ARM_ROTPK_HASH_LEN 32
+
+/* Special value used to verify platform parameters from BL2 to BL31 */
+#define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978)
+
+/* No need for system because we have only one cluster */
+#define ARM_SYSTEM_COUNT U(0)
+
+#define ARM_CACHE_WRITEBACK_SHIFT 6
+
+/*
+ * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels.
+ * The power levels have a 1:1 mapping with the MPIDR affinity levels.
+ */
+/* In NPCM845x - refers to cores */
+#define ARM_PWR_LVL0 MPIDR_AFFLVL0
+
+/* In NPCM845x - refers to cluster */
+#define ARM_PWR_LVL1 MPIDR_AFFLVL1
+
+/* No need for additional settings because the platform doesn't have system */
+
+/*
+ * Macros for local power states in ARM platforms encoded by State-ID field
+ * within the power-state parameter.
+ */
+#define NPCM845x_PLAT_PRIMARY_CPU U(0x0)
+#define NPCM845x_CLUSTER_COUNT U(1)
+
+#ifdef SECONDARY_BRINGUP
+#define NPCM845x_MAX_CPU_PER_CLUSTER U(2)
+#define NPCM845x_PLATFORM_CORE_COUNT U(2)
+#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(2)
+#else
+#define NPCM845x_MAX_CPU_PER_CLUSTER U(4)
+#define NPCM845x_PLATFORM_CORE_COUNT U(4)
+#define NPCM845x_PLATFORM_CLUSTER0_CORE_COUNT U(4)
+#endif /* SECONDARY_BRINGUP */
+
+#define NPCM845x_SYSTEM_COUNT U(0)
+
+/* Memory mapping for NPCM845x */
+#define NPCM845x_REG_BASE 0xf0000000
+#define NPCM845x_REG_SIZE 0x0ff16000
+
+/*
+ * DRAM
+ * 0x3fffffff +-------------+
+ * | BL33 | (non-secure)
+ * 0x06200000 +-------------+
+ * | BL32 SHARED | (non-secure)
+ * 0x06000000 +-------------+
+ * | BL32 | (secure)
+ * 0x02100000 +-------------+
+ * | BL31 | (secure)
+ * 0x02000000 +-------------+
+ * | | (non-secure)
+ * 0x00000000 +-------------+
+ *
+ * Trusted ROM
+ * 0xfff50000 +-------------+
+ * | BL1 (ro) |
+ * 0xfff40000 +-------------+
+ */
+
+#define ARM_DRAM1_BASE ULL(0x00000000)
+#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
+/*
+ * Although npcm845x is 4G,
+ * consider only 2G Trusted Firmware memory allocation
+ */
+#define ARM_DRAM1_SIZE ULL(0x37000000)
+#else
+#define ARM_DRAM1_SIZE ULL(0x10000000)
+#define ARM_DRAM1_END (ARM_DRAM1_BASE + ARM_DRAM1_SIZE - 1U)
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+/*
+ * The top 16MB of DRAM1 is configured as secure access only using the TZC
+ * - SCP TZC DRAM: If present, DRAM reserved for SCP use
+ * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use
+ */
+
+/* Check for redundancy */
+#ifdef NPCM845X_DEBUG
+#define PLAT_ARM_NS_IMAGE_BASE 0x0
+#endif /* NPCM845X_DEBUG */
+
+#define ARM_TZC_DRAM1_SIZE UL(0x01000000)
+#define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE
+#define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \
+ ARM_SCP_TZC_DRAM1_SIZE - 1U)
+
+/*
+ * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime
+ * firmware. This region is meant to be NOLOAD and will not be zero
+ * initialized. Data sections with the attribute `arm_el3_tzc_dram`
+ * will be placed here.
+ *
+ * NPCM845x - Currently the platform doesn't have EL3 implementation
+ * on secured DRAM.
+ */
+#define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - \
+ ARM_EL3_TZC_DRAM1_SIZE)
+#define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */
+#define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \
+ ARM_EL3_TZC_DRAM1_SIZE - 1U)
+
+#define ARM_AP_TZC_DRAM1_BASE 0x02100000
+#define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \
+ (ARM_SCP_TZC_DRAM1_SIZE + \
+ ARM_EL3_TZC_DRAM1_SIZE))
+#define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE - 1U)
+
+/* Define the Access permissions for Secure peripherals to NS_DRAM */
+#if ARM_CRYPTOCELL_INTEG
+/*
+ * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell.
+ * This is required by CryptoCell to authenticate BL33 which is loaded
+ * into the Non Secure DDR.
+ */
+#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD
+#else
+#define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE
+#endif /* ARM_CRYPTOCELL_INTEG */
+
+#ifdef SPD_opteed
+/*
+ * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to
+ * load/authenticate the trusted os extra image. The first 512KB of
+ * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading
+ * for OPTEE is paged image which only include the paging part using
+ * virtual memory but without "init" data. OPTEE will copy the "init" data
+ * (from pager image) to the first 512KB of TZC_DRAM, and then copy the
+ * extra image behind the "init" data.
+ */
+#define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE
+#define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE
+#define BL32_BASE ARM_AP_TZC_DRAM1_BASE
+#define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
+ ARM_AP_TZC_DRAM1_SIZE)
+
+#define ARM_OPTEE_PAGEABLE_LOAD_BASE ( \
+ ARM_AP_TZC_DRAM1_BASE + ARM_AP_TZC_DRAM1_SIZE - \
+ ARM_OPTEE_PAGEABLE_LOAD_SIZE)
+#define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000)
+#define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \
+ ARM_OPTEE_PAGEABLE_LOAD_BASE, \
+ ARM_OPTEE_PAGEABLE_LOAD_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
+ * Map the memory for the OP-TEE core (also known as OP-TEE pager
+ * when paging support is enabled).
+ */
+#define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \
+ BL32_BASE, BL32_LIMIT - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* SPD_opteed */
+
+#define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE
+#define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
+ ARM_TZC_DRAM1_SIZE)
+#define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \
+ ARM_NS_DRAM1_SIZE - 1U)
+
+/* The platform doesn't use DRAM2 but it has to have a value for calculation */
+#define ARM_DRAM2_BASE 0 /* PLAT_ARM_DRAM_BASE */
+#define ARM_DRAM2_SIZE 1 /* PLAT_ARM_DRAM_SIZE */
+#define ARM_DRAM2_END (ARM_DRAM2_BASE + ARM_DRAM2_SIZE - 1U)
+
+#define FIRST_EXT_INTERRUPT_NUM U(32)
+#define ARM_IRQ_SEC_PHY_TIMER (U(29) + FIRST_EXT_INTERRUPT_NUM)
+
+#define ARM_IRQ_SEC_SGI_0 8
+#define ARM_IRQ_SEC_SGI_1 9
+#define ARM_IRQ_SEC_SGI_2 10
+#define ARM_IRQ_SEC_SGI_3 11
+#define ARM_IRQ_SEC_SGI_4 12
+#define ARM_IRQ_SEC_SGI_5 13
+#define ARM_IRQ_SEC_SGI_6 14
+#define ARM_IRQ_SEC_SGI_7 15
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties
+ * as per GICv3 terminology. On a GICv2 system or mode,
+ * the lists will be merged and treated as Group 0 interrupts.
+ */
+#define ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_G0_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, \
+ PLAT_SDEI_NORMAL_PRI, (grp), GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, \
+ GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_EDGE)
+
+#define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \
+ ARM_SHARED_RAM_BASE, ARM_SHARED_RAM_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#ifdef ALLOW_DEBUG_MMU
+/* In order to be able to debug,
+ * the platform needs to add BL33 and BL32 to MMU as well.
+ */
+#define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \
+ ARM_NS_DRAM1_BASE, ARM_NS_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#ifdef BL32_BASE
+#define ARM_MAP_BL32_CORE_MEM MAP_REGION_FLAT( \
+ BL32_BASE, BL32_LIMIT - BL32_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* BL32_BASE */
+
+#ifdef NPCM845X_DEBUG
+#define ARM_MAP_SEC_BB_MEM MAP_REGION_FLAT( \
+ 0xFFFB0000, 0x20000, \
+ MT_MEMORY | MT_RW | MT_NS)
+#endif /* NPCM845X_DEBUG */
+#endif /* BL32_BASE */
+
+#define ARM_MAP_DRAM2 MAP_REGION_FLAT( \
+ ARM_DRAM2_BASE, ARM_DRAM2_SIZE, \
+ MT_MEMORY | MT_RW | MT_NS)
+
+#define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \
+ TSP_SEC_MEM_BASE, TSP_SEC_MEM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#if ARM_BL31_IN_DRAM
+#define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \
+ BL31_BASE, PLAT_ARM_MAX_BL31_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* ARM_BL31_IN_DRAM */
+
+/* Currently the platform doesn't have EL3 implementation on secured DRAM. */
+#define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \
+ ARM_EL3_TZC_DRAM1_BASE, \
+ ARM_EL3_TZC_DRAM1_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+#if defined(SPD_spmd)
+#define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \
+ PLAT_ARM_TRUSTED_DRAM_BASE, \
+ PLAT_ARM_TRUSTED_DRAM_SIZE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* SPD_spmd */
+
+/*
+ * Mapping for the BL1 RW region. This mapping is needed by BL2
+ * in order to share the Mbed TLS heap. Since the heap is allocated
+ * inside BL1, it resides in the BL1 RW region. Hence, BL2 needs access
+ * to the BL1 RW region in order to be able to access the heap.
+ */
+#define ARM_MAP_BL1_RW MAP_REGION_FLAT( \
+ BL1_RW_BASE, BL1_RW_LIMIT - BL1_RW_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+/*
+ * If SEPARATE_CODE_AND_RODATA=1 the platform will define a region
+ * for each section, otherwise one region containing both sections
+ * is defined.
+ */
+#if SEPARATE_CODE_AND_RODATA
+#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
+ BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
+ MT_CODE | EL3_PAS), \
+ MAP_REGION_FLAT(BL_RO_DATA_BASE, \
+ BL_RO_DATA_END - BL_RO_DATA_BASE, \
+ MT_RO_DATA | EL3_PAS)
+#else
+#define ARM_MAP_BL_RO MAP_REGION_FLAT( \
+ BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, \
+ MT_CODE | EL3_PAS)
+#endif /* SEPARATE_CODE_AND_RODATA */
+
+#if USE_COHERENT_MEM
+#define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \
+ BL_COHERENT_RAM_BASE, \
+ BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
+ MT_DEVICE | MT_RW | EL3_PAS)
+#endif /* USE_COHERENT_MEM */
+
+#if USE_ROMLIB
+#define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \
+ ROMLIB_RO_BASE, \
+ ROMLIB_RO_LIMIT - ROMLIB_RO_BASE, \
+ MT_CODE | MT_SECURE)
+
+#define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \
+ ROMLIB_RW_BASE, \
+ ROMLIB_RW_END - ROMLIB_RW_BASE, \
+ MT_MEMORY | MT_RW | MT_SECURE)
+#endif /* USE_ROMLIB */
+
+/*
+ * Map mem_protect flash region with read and write permissions
+ */
+#define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT( \
+ PLAT_ARM_MEM_PROT_ADDR, \
+ V2M_FLASH_BLOCK_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+/*
+ * Map the region for device tree configuration with read and write permissions
+ */
+#define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT( \
+ ARM_BL_RAM_BASE, \
+ (ARM_FW_CONFIGS_LIMIT - ARM_BL_RAM_BASE), \
+ MT_MEMORY | MT_RW | MT_SECURE)
+
+/*
+ * The max number of regions like RO(code), coherent and data required by
+ * different BL stages which need to be mapped in the MMU.
+ */
+#define ARM_BL_REGIONS 10
+
+#define MAX_MMAP_REGIONS ( \
+ PLAT_ARM_MMAP_ENTRIES + ARM_BL_REGIONS)
+
+/* Memory mapped Generic timer interfaces */
+#define ARM_SYS_CNTCTL_BASE UL(0XF07FC000)
+
+#define ARM_CONSOLE_BAUDRATE 115200
+
+/*
+ * The TBBR document specifies a watchdog timeout of 256 seconds. SP805
+ * asserts reset after two consecutive countdowns (2 x 128 = 256 sec)
+ */
+#define ARM_TWDG_TIMEOUT_SEC 128
+#define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \
+ ARM_TWDG_TIMEOUT_SEC)
+
+/******************************************************************************
+ * Required platform porting definitions common to all ARM standard platforms
+ *****************************************************************************/
+
+/*
+ * Some data must be aligned on the biggest cache line size in the platform.
+ * This is known only to the platform as it might have a combination of
+ * integrated and external caches (64 on Arbel).
+ */
+#define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT)
+
+/*
+ * To enable FW_CONFIG to be loaded by BL1, define the corresponding base
+ * and limit. Leave enough space of BL2 meminfo.
+ */
+#define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t))
+#define ARM_FW_CONFIG_LIMIT ( \
+ (ARM_BL_RAM_BASE + PAGE_SIZE) + (PAGE_SIZE / 2U))
+
+/*
+ * Boot parameters passed from BL2 to BL31/BL32 are stored here
+ */
+#define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT)
+#define ARM_BL2_MEM_DESC_LIMIT ( \
+ ARM_BL2_MEM_DESC_BASE + (PAGE_SIZE / 2U))
+
+/*
+ * Define limit of firmware configuration memory:
+ * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory
+ */
+#define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2))
+
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need
+ * two sets of addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE
+#define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + \
+ (PLAT_ARM_TRUSTED_ROM_SIZE - PLAT_ARM_MAX_ROMLIB_RO_SIZE))
+/*
+ * Put BL1 RW at the top of the Trusted SRAM.
+ */
+#define BL1_RW_BASE (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE - \
+ (PLAT_ARM_MAX_BL1_RW_SIZE + PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+#define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \
+ (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE))
+
+#define ROMLIB_RO_BASE BL1_RO_LIMIT
+#define ROMLIB_RO_LIMIT ( \
+ PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE)
+
+#define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE)
+#define ROMLIB_RW_END ( \
+ ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE)
+
+/******************************************************************************
+ * BL2 specific defines.
+ *****************************************************************************/
+#if BL2_AT_EL3
+/* Put BL2 towards the middle of the Trusted SRAM */
+#define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \
+ PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000)
+#define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#else
+/*
+ * Put BL2 just below BL1.
+ */
+#define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE)
+#define BL2_LIMIT BL1_RW_BASE
+#endif /* BL2_AT_EL3 */
+
+/*******************************************************************************
+ * BL31 specific defines.
+ ******************************************************************************/
+#if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION
+/*
+ * Put BL31 at the bottom of TZC secured DRAM
+ */
+#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
+#define BL31_LIMIT ( \
+ ARM_AP_TZC_DRAM1_BASE + PLAT_ARM_MAX_BL31_SIZE)
+
+/*
+ * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM.
+ * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten.
+ */
+#if SEPARATE_NOBITS_REGION
+#define BL31_NOBITS_BASE BL2_BASE
+#define BL31_NOBITS_LIMIT BL2_LIMIT
+#endif /* SEPARATE_NOBITS_REGION */
+#elif (RESET_TO_BL31)
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+#if !ENABLE_PIE
+#error "BL31 must be a PIE if RESET_TO_BL31=1."
+#endif /* !ENABLE_PIE */
+/*
+ * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
+ * used for building BL31 and not used for loading BL31.
+ */
+#define NEW_SRAM_ALLOCATION
+
+#ifdef NEW_SRAM_ALLOCATION
+ #define BL31_BASE 0x20001000
+#else
+ #define BL31_BASE 0x20001000
+#endif /* NEW_SRAM_ALLOCATION */
+
+#define BL31_LIMIT BL2_BASE /* PLAT_ARM_MAX_BL31_SIZE */
+#else
+/* Put BL31 below BL2 in the Trusted SRAM.*/
+#define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) - \
+ PLAT_ARM_MAX_BL31_SIZE)
+#define BL31_PROGBITS_LIMIT BL2_BASE
+
+/*
+ * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE.
+ * This is because in the BL2_AT_EL3 configuration, BL2 is always resident.
+ */
+#if BL2_AT_EL3
+#define BL31_LIMIT BL2_BASE
+#else
+#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#endif /* BL2_AT_EL3 */
+#endif /* ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION */
+
+/*
+ * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is
+ * no SPD and no SPM-MM, as they are the only ones that can be used as BL32.
+ */
+#if defined(SPD_none) && !SPM_MM
+#undef BL32_BASE
+#endif /* SPD_none && !SPM_MM */
+
+/******************************************************************************
+ * FWU Images: NS_BL1U, BL2U & NS_BL2U defines.
+ *****************************************************************************/
+#define BL2U_BASE BL2_BASE
+#define BL2U_LIMIT BL2_LIMIT
+
+#define NS_BL2U_BASE ARM_NS_DRAM1_BASE
+#define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000))
+
+/*
+ * ID of the secure physical generic timer interrupt used by the TSP.
+ */
+#define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER
+
+/*
+ * One cache line needed for bakery locks on ARM platforms
+ */
+#define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE)
+
+/* Priority levels for ARM platforms */
+#define PLAT_RAS_PRI 0x10
+#define PLAT_SDEI_CRITICAL_PRI 0x60
+#define PLAT_SDEI_NORMAL_PRI 0x70
+
+/* ARM platforms use 3 upper bits of secure interrupt priority */
+#define ARM_PRI_BITS 3
+
+/* SGI used for SDEI signalling */
+#define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0
+
+#if SDEI_IN_FCONF
+/* ARM SDEI dynamic private event max count */
+#define ARM_SDEI_DP_EVENT_MAX_CNT 3
+
+/* ARM SDEI dynamic shared event max count */
+#define ARM_SDEI_DS_EVENT_MAX_CNT 3
+#else
+/* ARM SDEI dynamic private event numbers */
+#define ARM_SDEI_DP_EVENT_0 1000
+#define ARM_SDEI_DP_EVENT_1 1001
+#define ARM_SDEI_DP_EVENT_2 1002
+
+/* ARM SDEI dynamic shared event numbers */
+#define ARM_SDEI_DS_EVENT_0 2000
+#define ARM_SDEI_DS_EVENT_1 2001
+#define ARM_SDEI_DS_EVENT_2 2002
+
+#define ARM_SDEI_PRIVATE_EVENTS \
+ SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+
+#define ARM_SDEI_SHARED_EVENTS \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \
+ SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC)
+#endif /* SDEI_IN_FCONF */
+
+#endif /* ARM_DEF_H */
diff --git a/include/plat/nuvoton/common/plat_macros.S b/include/plat/nuvoton/common/plat_macros.S
new file mode 100644
index 0000000..08f9feb
--- /dev/null
+++ b/include/plat/nuvoton/common/plat_macros.S
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_MACROS_S
+#define PLAT_MACROS_S
+
+#include <arm_macros.S>
+#include <cci_macros.S>
+#include <platform_def.h>
+
+/*
+ * The below macro prints out relevant GIC
+ * registers whenever an unhandled exception is
+ * taken in BL3-1.
+ * Clobbers: x0 - x10, x16, x17, sp
+ */
+.macro plat_print_gic_regs
+mov_imm x17, BASE_GICC_BASE
+mov_imm x16, BASE_GICD_BASE
+arm_print_gic_regs
+.endm
+
+/*
+ * the below macros print out relevant interconnect
+ * registers whenever an unhandled exception is
+ * taken in BL3-1
+ */
+.macro plat_print_interconnect_regs
+ /* TODO */
+.endm
+
+/*
+ * The below required platform porting macro
+ * prints out relevant platform registers
+ * whenever an unhandled exception is taken in
+ * BL31.
+ */
+.macro plat_crash_print_regs
+ /* TODO */
+.endm
+
+#endif /* PLAT_MACROS_S */
diff --git a/include/plat/nuvoton/common/plat_npcm845x.h b/include/plat/nuvoton/common/plat_npcm845x.h
new file mode 100644
index 0000000..d90952a
--- /dev/null
+++ b/include/plat/nuvoton/common/plat_npcm845x.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLAT_NPCM845X_H
+#define PLAT_NPCM845X_H
+
+#include <drivers/arm/gicv2.h>
+#include <lib/psci/psci.h>
+
+unsigned int plat_calc_core_pos(uint64_t mpidr);
+void npcm845x_mailbox_init(uintptr_t base_addr);
+void plat_gic_driver_init(void);
+void plat_gic_init(void);
+void plat_gic_cpuif_enable(void);
+void plat_gic_cpuif_disable(void);
+void plat_gic_pcpu_init(void);
+
+void __dead2 npcm845x_system_off(void);
+void __dead2 npcm845x_system_reset(void);
+void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state);
+bool npcm845x_is_wakeup_src_irqsteer(void);
+void __dead2 npcm845x_pwr_down_wfi(const psci_power_state_t *target_state);
+void npcm845x_cpu_standby(plat_local_state_t cpu_state);
+int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint);
+int npcm845x_pwr_domain_on(u_register_t mpidr);
+int npcm845x_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state);
+
+#if !ARM_BL31_IN_DRAM
+void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state);
+#endif
+
+void __dead2 npcm845x_pwr_domain_pwr_down_wfi(
+ const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state);
+void npcm845x_pwr_domain_off(const psci_power_state_t *target_state);
+void __init npcm845x_bl31_plat_arch_setup(void);
+
+#endif /* PLAT_NPCM845X_H */
diff --git a/include/plat/nuvoton/npcm845x/platform_def.h b/include/plat/nuvoton/npcm845x/platform_def.h
new file mode 100644
index 0000000..09da36b
--- /dev/null
+++ b/include/plat/nuvoton/npcm845x/platform_def.h
@@ -0,0 +1,303 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (c) 2017-2023 Nuvoton Technology Corp.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <arch.h>
+#include <common/interrupt_props.h>
+#include <common/tbbr/tbbr_img_def.h>
+#include <drivers/arm/gic_common.h>
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <npcm845x_arm_def.h>
+#include <plat/arm/common/smccc_def.h>
+#include <plat/common/common_def.h>
+
+#define VALUE_TO_STRING(x) #x
+#define VALUE(x) VALUE_TO_STRING(x)
+#define VAR_NAME_VALUE(var) #var "=" VALUE(var)
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define PLATFORM_STACK_SIZE 0x400
+
+#define PLATFORM_CORE_COUNT NPCM845x_PLATFORM_CORE_COUNT
+#define PLATFORM_CLUSTER_COUNT NPCM845x_CLUSTER_COUNT
+#define PLATFORM_MAX_CPU_PER_CLUSTER NPCM845x_MAX_CPU_PER_CLUSTER
+#define PLAT_PRIMARY_CPU NPCM845x_PLAT_PRIMARY_CPU
+#define PLATFORM_SYSTEM_COUNT NPCM845x_SYSTEM_COUNT
+
+/* Local power state for power domains in Run state. */
+#define PLAT_LOCAL_STATE_RUN U(0)
+/* Local power state for retention. Valid only for CPU power domains */
+#define PLAT_LOCAL_STATE_RET U(1)
+/*
+ * Local power state for OFF/power-down. Valid for CPU and cluster power
+ * domains.
+ */
+#define PLAT_LOCAL_STATE_OFF U(2)
+
+/*
+ * This macro defines the deepest power down states possible. Any state ID
+ * higher than this is invalid.
+ */
+#define PLAT_MAX_OFF_STATE PLAT_LOCAL_STATE_OFF
+#define PLAT_MAX_RET_STATE PLAT_LOCAL_STATE_RET
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define NPCM845x_MAX_PWR_LVL ARM_PWR_LVL1
+
+/*
+ * Macros used to parse state information from State-ID if it is using the
+ * recommended encoding for State-ID.
+ */
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+/*
+ * Required ARM standard platform porting definitions
+ */
+#define PLAT_ARM_CLUSTER_COUNT PLATFORM_CLUSTER_COUNT
+
+#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + PLATFORM_CORE_COUNT)
+#define PLAT_MAX_PWR_LVL NPCM845x_MAX_PWR_LVL
+
+#define PLAT_LOCAL_PSTATE_WIDTH 4
+#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
+
+#ifdef BL32_BASE
+
+#ifndef CONFIG_TARGET_ARBEL_PALLADIUM
+#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
+#else
+#define PLAT_ARM_TRUSTED_DRAM_BASE BL32_BASE
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+#define PLAT_ARM_TRUSTED_DRAM_SIZE UL(0x02000000) /* 32 MB */
+#endif /* BL32_BASE */
+
+#define PWR_DOMAIN_AT_MAX_LVL U(1)
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 32)
+#define MAX_XLAT_TABLES 16
+#define PLAT_ARM_MMAP_ENTRIES 17
+
+#ifdef NPCM845X_DEBUG
+#define MAX_MMAP_REGIONS 8
+#define NPCM845X_TZ1_BASE 0xFFFB0000
+#endif /* NPCM845X_DEBUG */
+
+#define FIQ_SMP_CALL_SGI 10
+
+/* (0x00040000) 128 KB, the rest 128K if it is non secured */
+#define PLAT_ARM_TRUSTED_SRAM_SIZE UL(0x00020000)
+
+#define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */
+
+/* UL(0xfffCE000) add calc ARM_TRUSTED_SRAM_BASE */
+#define ARM_SHARED_RAM_BASE (BL31_BASE + 0x00020000 - ARM_SHARED_RAM_SIZE)
+
+/* The remaining Trusted SRAM is used to load the BL images */
+#define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + ARM_SHARED_RAM_SIZE)
+
+/*
+ * PLAT_ARM_TRUSTED_SRAM_SIZE is taken from platform_def.h 0x20000
+ * because only half is secured in this specific implementation
+ */
+#define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+
+#if RESET_TO_BL31
+/* Size of Trusted SRAM - the first 4KB of shared memory */
+#define PLAT_ARM_MAX_BL31_SIZE \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+#else
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE
+ * is calculated using the current BL31 PROGBITS debug size plus the sizes
+ * of BL2 and BL1-RW
+ */
+#define PLAT_ARM_MAX_BL31_SIZE \
+ (PLAT_ARM_TRUSTED_SRAM_SIZE - ARM_SHARED_RAM_SIZE)
+#endif /* RESET_TO_BL31 */
+/*
+ * Load address of BL33 for this platform port
+ */
+#define PLAT_ARM_NS_IMAGE_BASE (ARM_DRAM1_BASE + UL(0x6208000))
+
+#ifdef NPCM845X_DEBUG
+#define COUNTER_FREQUENCY 0x07735940 /* f/4 = 125MHz */
+#endif /* NPCM845X_DEBUG */
+
+#define COUNTER_FREQUENCY 0x0EE6B280 /* f/2 = 250MHz */
+#define PLAT_ARM_NSTIMER_FRAME_ID U(1)
+
+/* GIC parameters */
+
+/* Base compatible GIC memory map */
+#define NT_GIC_BASE (0xDFFF8000)
+#define BASE_GICD_BASE (NT_GIC_BASE + 0x1000)
+#define BASE_GICC_BASE (NT_GIC_BASE + 0x2000)
+#define BASE_GICR_BASE (NT_GIC_BASE + 0x200000)
+#define BASE_GICH_BASE (NT_GIC_BASE + 0x4000)
+#define BASE_GICV_BASE (NT_GIC_BASE + 0x6000)
+
+#define DEVICE1_BASE BASE_GICD_BASE
+#define DEVICE1_SIZE 0x7000
+
+#ifdef NPCM845X_DEBUG
+/* ((BASE_GICR_BASE - BASE_GICD_BASE) + (PLATFORM_CORE_COUNT * 0x20000)) */
+#define ARM_CPU_START_ADDRESS(m) UL(0xf0800e00 + 0x10 + m * 4)
+#endif /* NPCM845X_DEBUG */
+
+#define PLAT_REG_BASE NPCM845x_REG_BASE
+#define PLAT_REG_SIZE NPCM845x_REG_SIZE
+
+/* MMU entry for internal (register) space access */
+#define MAP_DEVICE0 \
+ MAP_REGION_FLAT(PLAT_REG_BASE, PLAT_REG_SIZE, MT_DEVICE | MT_RW | MT_NS)
+
+#define MAP_DEVICE1 \
+ MAP_REGION_FLAT(DEVICE1_BASE, DEVICE1_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*
+ * Define a list of Group 1 Secure and Group 0 interrupt properties
+ * as per GICv3 terminology. On a GICv2 system or mode,
+ * the lists will be merged and treated as Group 0 interrupts.
+ */
+#define PLAT_ARM_GICD_BASE BASE_GICD_BASE
+#define PLAT_ARM_GICC_BASE BASE_GICC_BASE
+
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) \
+ INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \
+ GIC_INTR_CFG_LEVEL), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE), \
+ INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, \
+ grp, GIC_INTR_CFG_EDGE)
+
+#define PLAT_ARM_G0_IRQ_PROPS(grp)
+
+/* Required for compilation: */
+
+/*
+ * PLAT_ARM_MAX_BL1_RW_SIZE is calculated using the current BL1 RW debug size
+ * plus a little space for growth.
+ */
+#define PLAT_ARM_MAX_BL1_RW_SIZE 0 /* UL(0xB000) */
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0xe000)
+#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0x6000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE UL(0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE UL(0)
+#define FVP_BL2_ROMLIB_OPTIMIZATION UL(0)
+#endif /* USE_ROMLIB */
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size
+ * plus a little space for growth.
+ */
+#if TRUSTED_BOARD_BOOT
+#define PLAT_ARM_MAX_BL2_SIZE (UL(0x1D000) * FVP_BL2_ROMLIB_OPTIMIZATION)
+#else
+/* (UL(0x13000) - FVP_BL2_ROMLIB_OPTIMIZATION) */
+#define PLAT_ARM_MAX_BL2_SIZE 0
+#endif /* TRUSTED_BOARD_BOOT */
+
+#undef NPCM_PRINT_ONCE
+#ifdef NPCM_PRINT_ONCE
+#define PRINT_ONLY_ONCE
+#pragma message(VAR_NAME_VALUE(ARM_AP_TZC_DRAM1_BASE))
+#pragma message(VAR_NAME_VALUE(BL31_BASE))
+#pragma message(VAR_NAME_VALUE(BL31_LIMIT))
+#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL31_SIZE))
+#pragma message(VAR_NAME_VALUE(BL32_BASE))
+#pragma message(VAR_NAME_VALUE(BL32_LIMIT))
+#pragma message(VAR_NAME_VALUE(PLAT_ARM_MAX_BL32_SIZE)
+#pragma message(VAR_NAME_VALUE(SPMD_SPM_AT_SEL2_KKO))
+#endif /* NPCM_PRINT_ONCE */
+
+#define MAX_IO_DEVICES 4
+#define MAX_IO_HANDLES 4
+
+#define PLAT_ARM_FIP_BASE 0x0
+#define PLAT_ARM_FIP_MAX_SIZE PLAT_ARM_MAX_BL31_SIZE
+
+#define PLAT_ARM_BOOT_UART_BASE 0xF0000000
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ 115200
+#define PLAT_ARM_RUN_UART_BASE 0xF0000000
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ 115200
+#define PLAT_ARM_CRASH_UART_BASE 0xF0000000
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ 115200
+
+/*
+ * Mailbox to control the secondary cores.All secondary cores are held in a wait
+ * loop in cold boot. To release them perform the following steps (plus any
+ * additional barriers that may be needed):
+ *
+ * uint64_t *entrypoint = (uint64_t *)PLAT_NPCM_TM_ENTRYPOINT;
+ * *entrypoint = ADDRESS_TO_JUMP_TO;
+ *
+ * uint64_t *mbox_entry = (uint64_t *)PLAT_NPCM_TM_HOLD_BASE;
+ * mbox_entry[cpu_id] = PLAT_NPCM_TM_HOLD_BASE;
+ *
+ * sev();
+ */
+#define PLAT_NPCM_TRUSTED_MAILBOX_BASE ARM_SHARED_RAM_BASE
+
+/* The secure entry point to be used on warm reset by all CPUs. */
+#define PLAT_NPCM_TM_ENTRYPOINT PLAT_NPCM_TRUSTED_MAILBOX_BASE
+#define PLAT_NPCM_TM_ENTRYPOINT_SIZE ULL(8)
+
+/* Hold entries for each CPU. */
+#define PLAT_NPCM_TM_HOLD_BASE \
+ (PLAT_NPCM_TM_ENTRYPOINT + PLAT_NPCM_TM_ENTRYPOINT_SIZE)
+#define PLAT_NPCM_TM_HOLD_ENTRY_SIZE ULL(8)
+#define PLAT_NPCM_TM_HOLD_SIZE \
+ (PLAT_NPCM_TM_HOLD_ENTRY_SIZE * PLATFORM_CORE_COUNT)
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_BASE \
+ (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE)
+
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE ULL(8)
+
+#define PLAT_NPCM_TRUSTED_NOTIFICATION_SIZE \
+ (PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE * PLATFORM_CORE_COUNT)
+
+#define PLAT_NPCM_TRUSTED_MAILBOX_SIZE \
+ (PLAT_NPCM_TM_ENTRYPOINT_SIZE + PLAT_NPCM_TM_HOLD_SIZE + \
+ PLAT_NPCM_TRUSTED_NOTIFICATION_ENTRY_SIZE)
+
+#define PLAT_NPCM_TM_HOLD_STATE_WAIT ULL(0)
+#define PLAT_NPCM_TM_HOLD_STATE_GO ULL(1)
+#define PLAT_NPCM_TM_HOLD_STATE_BSP_OFF ULL(2)
+
+#define PLAT_NPCM_TM_NOTIFICATION_START ULL(0xAA)
+#define PLAT_NPCM_TM_NOTIFICATION_BR ULL(0xCC)
+
+#ifdef NPCM845X_DEBUG
+#define PLAT_ARM_TRUSTED_MAILBOX_BASE 0xfffB0000
+#endif /* NPCM845X_DEBUG */
+
+#endif /* PLATFORM_DEF_H */
diff --git a/lib/cpus/aarch32/cortex_a12.S b/lib/cpus/aarch32/cortex_a12.S
index 5300fe0..089c089 100644
--- a/lib/cpus/aarch32/cortex_a12.S
+++ b/lib/cpus/aarch32/cortex_a12.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,14 +69,7 @@
b cortex_a12_disable_smp
endfunc cortex_a12_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A12. Must follow AAPCS.
- */
-func cortex_a12_errata_report
- bx lr
-endfunc cortex_a12_errata_report
-#endif
+errata_report_shim cortex_a12
declare_cpu_ops cortex_a12, CORTEX_A12_MIDR, \
cortex_a12_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a15.S b/lib/cpus/aarch32/cortex_a15.S
index 1143e9b..01323f5 100644
--- a/lib/cpus/aarch32/cortex_a15.S
+++ b/lib/cpus/aarch32/cortex_a15.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -62,6 +62,7 @@
bx lr
endfunc check_errata_816470
+add_erratum_entry cortex_a15, ERRATUM(816470), ERRATA_A15_816470
/* ----------------------------------------------------
* Errata Workaround for Cortex A15 Errata #827671.
* This applies only to revision >= r3p0 of Cortex A15.
@@ -91,6 +92,8 @@
b cpu_rev_var_hs
endfunc check_errata_827671
+add_erratum_entry cortex_a15, ERRATUM(827671), ERRATA_A15_827671
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -100,6 +103,8 @@
bx lr
endfunc check_errata_cve_2017_5715
+add_erratum_entry cortex_a15, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+
func check_errata_cve_2022_23960
#if WORKAROUND_CVE_2022_23960
mov r0, #ERRATA_APPLIES
@@ -109,29 +114,7 @@
bx lr
endfunc check_errata_cve_2022_23960
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A15. Must follow AAPCS.
- */
-func cortex_a15_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A15_816470, cortex_a15, 816470
- report_errata ERRATA_A15_827671, cortex_a15, 827671
- report_errata WORKAROUND_CVE_2017_5715, cortex_a15, cve_2017_5715
- report_errata WORKAROUND_CVE_2022_23960, cortex_a15, cve_2022_23960
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a15_errata_report
-#endif
+add_erratum_entry cortex_a15, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
func cortex_a15_reset_func
mov r5, lr
@@ -185,6 +168,8 @@
b cortex_a15_disable_smp
endfunc cortex_a15_cluster_pwr_dwn
+errata_report_shim cortex_a15
+
declare_cpu_ops cortex_a15, CORTEX_A15_MIDR, \
cortex_a15_reset_func, \
cortex_a15_core_pwr_dwn, \
diff --git a/lib/cpus/aarch32/cortex_a17.S b/lib/cpus/aarch32/cortex_a17.S
index b8abd33..8d76ab2 100644
--- a/lib/cpus/aarch32/cortex_a17.S
+++ b/lib/cpus/aarch32/cortex_a17.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -63,6 +63,8 @@
b cpu_rev_var_ls
endfunc check_errata_852421
+add_erratum_entry cortex_a17, ERRATUM(852421), ERRATA_A17_852421
+
/* ----------------------------------------------------
* Errata Workaround for Cortex A17 Errata #852423.
* This applies only to revision <= r1p2 of Cortex A17.
@@ -91,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_852423
+add_erratum_entry cortex_a17, ERRATUM(852423), ERRATA_A17_852423
+
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
mov r0, #ERRATA_APPLIES
@@ -100,28 +104,9 @@
bx lr
endfunc check_errata_cve_2017_5715
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A17. Must follow AAPCS.
- */
-func cortex_a17_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
+add_erratum_entry cortex_a17, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A17_852421, cortex_a17, 852421
- report_errata ERRATA_A17_852423, cortex_a17, 852423
- report_errata WORKAROUND_CVE_2017_5715, cortex_a17, cve_2017_5715
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a17_errata_report
-#endif
+errata_report_shim cortex_a17
func cortex_a17_reset_func
mov r5, lr
@@ -139,7 +124,7 @@
#endif
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
- ldr r0, =workaround_bpiall_runtime_exceptions
+ ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR
stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */
diff --git a/lib/cpus/aarch32/cortex_a5.S b/lib/cpus/aarch32/cortex_a5.S
index 8abb66f..625ea7b 100644
--- a/lib/cpus/aarch32/cortex_a5.S
+++ b/lib/cpus/aarch32/cortex_a5.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,14 +69,7 @@
b cortex_a5_disable_smp
endfunc cortex_a5_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A5. Must follow AAPCS.
- */
-func cortex_a5_errata_report
- bx lr
-endfunc cortex_a5_errata_report
-#endif
+errata_report_shim cortex_a5
declare_cpu_ops cortex_a5, CORTEX_A5_MIDR, \
cortex_a5_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a53.S b/lib/cpus/aarch32/cortex_a53.S
index 6e3ff81..89b238a 100644
--- a/lib/cpus/aarch32/cortex_a53.S
+++ b/lib/cpus/aarch32/cortex_a53.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -44,6 +44,8 @@
bx lr
endfunc check_errata_819472
+add_erratum_entry cortex_a53, ERRATUM(819472), ERRATA_A53_819472
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #824069.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -59,6 +61,8 @@
bx lr
endfunc check_errata_824069
+add_erratum_entry cortex_a53, ERRATUM(824069), ERRATA_A53_824069
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #826319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -89,6 +93,8 @@
b cpu_rev_var_ls
endfunc check_errata_826319
+add_erratum_entry cortex_a53, ERRATUM(826319), ERRATA_A53_826319
+
/* ---------------------------------------------------
* Errata Workaround for Cortex A53 Errata #827319.
* This applies only to revision <= r0p2 of Cortex A53.
@@ -104,6 +110,8 @@
bx lr
endfunc check_errata_827319
+add_erratum_entry cortex_a53, ERRATUM(827319), ERRATA_A53_827319
+
/* ---------------------------------------------------------------------
* Disable the cache non-temporal hint.
*
@@ -142,6 +150,9 @@
b cpu_rev_var_ls
endfunc check_errata_disable_non_temporal_hint
+add_erratum_entry cortex_a53, ERRATUM(836870), ERRATA_A53_836870 | A53_DISABLE_NON_TEMPORAL_HINT, \
+ disable_non_temporal_hint
+
/* --------------------------------------------------
* Errata Workaround for Cortex A53 Errata #855873.
*
@@ -176,6 +187,8 @@
b cpu_rev_var_hs
endfunc check_errata_855873
+add_erratum_entry cortex_a53, ERRATUM(855873), ERRATA_A53_855873
+
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A53.
* Shall clobber: r0-r6
@@ -284,31 +297,7 @@
b cortex_a53_disable_smp
endfunc cortex_a53_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A53. Must follow AAPCS.
- */
-func cortex_a53_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A53_819472, cortex_a53, 819472
- report_errata ERRATA_A53_824069, cortex_a53, 824069
- report_errata ERRATA_A53_826319, cortex_a53, 826319
- report_errata ERRATA_A53_827319, cortex_a53, 827319
- report_errata ERRATA_A53_836870, cortex_a53, disable_non_temporal_hint
- report_errata ERRATA_A53_855873, cortex_a53, 855873
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a53_errata_report
-#endif
+errata_report_shim cortex_a53
declare_cpu_ops cortex_a53, CORTEX_A53_MIDR, \
cortex_a53_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a7.S b/lib/cpus/aarch32/cortex_a7.S
index 4d4bb77..71542d5 100644
--- a/lib/cpus/aarch32/cortex_a7.S
+++ b/lib/cpus/aarch32/cortex_a7.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -69,14 +69,7 @@
b cortex_a7_disable_smp
endfunc cortex_a7_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A7. Must follow AAPCS.
- */
-func cortex_a7_errata_report
- bx lr
-endfunc cortex_a7_errata_report
-#endif
+errata_report_shim cortex_a7
declare_cpu_ops cortex_a7, CORTEX_A7_MIDR, \
cortex_a7_reset_func, \
diff --git a/lib/cpus/aarch32/cortex_a9.S b/lib/cpus/aarch32/cortex_a9.S
index 7200343..1e9757a 100644
--- a/lib/cpus/aarch32/cortex_a9.S
+++ b/lib/cpus/aarch32/cortex_a9.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -35,14 +35,16 @@
bx lr
endfunc cortex_a9_enable_smp
-func check_errata_a9_794073
+func check_errata_794073
#if ERRATA_A9_794073
mov r0, #ERRATA_APPLIES
#else
mov r0, #ERRATA_MISSING
#endif
bx lr
-endfunc check_errata_cve_2017_5715
+endfunc check_errata_794073
+
+add_erratum_entry cortex_a9, ERRATUM(794073), ERRATA_A9_794073
func check_errata_cve_2017_5715
#if WORKAROUND_CVE_2017_5715
@@ -53,31 +55,13 @@
bx lr
endfunc check_errata_cve_2017_5715
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A9. Must follow AAPCS.
- */
-func cortex_a9_errata_report
- push {r12, lr}
-
- bl cpu_get_rev_var
- mov r4, r0
+add_erratum_entry cortex_a9, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, cortex_a9, cve_2017_5715
- report_errata ERRATA_A9_794073, cortex_a9, a9_79407
-
- pop {r12, lr}
- bx lr
-endfunc cortex_a9_errata_report
-#endif
+errata_report_shim cortex_a9
func cortex_a9_reset_func
#if IMAGE_BL32 && WORKAROUND_CVE_2017_5715
- ldr r0, =workaround_bpiall_runtime_exceptions
+ ldr r0, =wa_cve_2017_5715_bpiall_vbar
stcopr r0, VBAR
stcopr r0, MVBAR
/* isb will be applied in the course of the reset func */
diff --git a/lib/cpus/aarch64/cortex_a35.S b/lib/cpus/aarch64/cortex_a35.S
index be3c652..6ffb944 100644
--- a/lib/cpus/aarch64/cortex_a35.S
+++ b/lib/cpus/aarch64/cortex_a35.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,9 +16,7 @@
* ---------------------------------------------
*/
func cortex_a35_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a35_disable_dcache
@@ -28,65 +26,29 @@
* ---------------------------------------------
*/
func cortex_a35_disable_smp
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
isb
dsb sy
ret
endfunc cortex_a35_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A35 Errata #855472.
- * This applies to revisions r0p0 of Cortex A35.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a35_855472_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_855472
- cbz x0, 1f
- mrs x1, CORTEX_A35_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
- msr CORTEX_A35_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a35_855472_wa
+workaround_reset_start cortex_a35, ERRATUM(855472), ERRATA_A35_855472
+ sysreg_bit_set CORTEX_A35_CPUACTLR_EL1, CORTEX_A35_CPUACTLR_EL1_ENDCCASCI
+workaround_reset_end cortex_a35, ERRATUM(855472)
-func check_errata_855472
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_855472
+check_erratum_ls cortex_a35, ERRATUM(855472), CPU_REV(0, 0)
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A35.
- * Clobbers: x0
* -------------------------------------------------
*/
-func cortex_a35_reset_func
- mov x19, x30
- bl cpu_get_rev_var
-
-#if ERRATA_A35_855472
- bl errata_a35_855472_wa
-#endif
-
+cpu_reset_func_start cortex_a35
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CORTEX_A35_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A35_CPUECTLR_SMPEN_BIT
- msr CORTEX_A35_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a35_reset_func
+ sysreg_bit_set CORTEX_A35_CPUECTLR_EL1, CORTEX_A35_CPUECTLR_SMPEN_BIT
+cpu_reset_func_end cortex_a35
func cortex_a35_core_pwr_dwn
mov x18, x30
@@ -149,27 +111,7 @@
b cortex_a35_disable_smp
endfunc cortex_a35_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A35. Must follow AAPCS.
- */
-func cortex_a35_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A35_855472, cortex_a35, 855472
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a35_errata_report
-#endif
-
+errata_report_shim cortex_a35
/* ---------------------------------------------
* This function provides cortex_a35 specific
diff --git a/lib/cpus/aarch64/cortex_a510.S b/lib/cpus/aarch64/cortex_a510.S
index e10ebb0..6fce24e 100644
--- a/lib/cpus/aarch64/cortex_a510.S
+++ b/lib/cpus/aarch64/cortex_a510.S
@@ -21,110 +21,15 @@
#error "Cortex-A510 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #1922240.
- * This applies only to revision r0p0 (fixed in r0p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_1922240_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1922240
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(1922240), ERRATA_A510_1922240
/* Apply the workaround by setting IMP_CMPXACTLR_EL1[11:10] = 0b11. */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- mov x1, #3
- bfi x0, x1, #10, #2
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_1922240_wa
-
-func check_errata_1922240
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1922240
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2288014.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0. (fixed in r1p1)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2288014_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2288014
- cbz x0, 1f
-
- /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- mov x1, #1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2288014_wa
-
-func check_errata_2288014
- /* Applies to r1p0 and below */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2288014
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2042739.
- * This applies only to revisions r0p0, r0p1 and r0p2.
- * (fixed in r0p3)
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2042739_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2042739
- cbz x0, 1f
-
- /* Apply the workaround by disabling ReadPreferUnique. */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, #1
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2042739_wa
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(1922240)
-func check_errata_2042739
- /* Applies to revisions r0p0 - r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2042739
+check_erratum_ls cortex_a510, ERRATUM(1922240), CPU_REV(0, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2041909.
- * This applies only to revision r0p2 and it is fixed in
- * r0p3. The issue is also present in r0p0 and r0p1 but
- * there is no workaround in those revisions.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2041909_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2041909
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2041909), ERRATA_A510_2041909
/* Apply workaround */
mov x0, xzr
msr S3_6_C15_C4_0, x0
@@ -140,39 +45,55 @@
mov x0, #0x3F1
movk x0, #0x110, lsl #16
msr S3_6_C15_C4_1, x0
- isb
+workaround_reset_end cortex_a510, ERRATUM(2041909)
+
+check_erratum_range cortex_a510, ERRATUM(2041909), CPU_REV(0, 2), CPU_REV(0, 2)
+
+workaround_reset_start cortex_a510, ERRATUM(2042739), ERRATA_A510_2042739
+ /* Apply the workaround by disabling ReadPreferUnique. */
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE, \
+ CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT, CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2042739)
-1:
- ret x17
-endfunc errata_cortex_a510_2041909_wa
+check_erratum_ls cortex_a510, ERRATUM(2042739), CPU_REV(0, 2)
-func check_errata_2041909
- /* Applies only to revision r0p2 */
- mov x1, #0x02
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2041909
+workaround_reset_start cortex_a510, ERRATUM(2172148), ERRATA_A510_2172148
+ /*
+ * Force L2 allocation of transient lines by setting
+ * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
+ */
+ mrs x0, CORTEX_A510_CPUECTLR_EL1
+ mov x1, #1
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
+ bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
+ msr CORTEX_A510_CPUECTLR_EL1, x0
+workaround_reset_end cortex_a510, ERRATUM(2172148)
+
+check_erratum_ls cortex_a510, ERRATUM(2172148), CPU_REV(1, 0)
+
+workaround_reset_start cortex_a510, ERRATUM(2218950), ERRATA_A510_2218950
+ /* Set bit 18 in CPUACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+ /* Set bit 25 in CMPXACTLR_EL1 */
+ sysreg_bitfield_insert CORTEX_A510_CMPXACTLR_EL1, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE, \
+ CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT, CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH
+
+workaround_reset_end cortex_a510, ERRATUM(2218950)
+
+check_erratum_ls cortex_a510, ERRATUM(2218950), CPU_REV(1, 0)
/* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2250311.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
* This workaround is not a typical errata fix. MPMM
* is disabled here, but this conflicts with the BL31
* MPMM support. So in addition to simply disabling
* the feature, a flag is set in the MPMM library
* indicating that it should not be enabled even if
* ENABLE_MPMM=1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
* --------------------------------------------------
*/
-func errata_cortex_a510_2250311_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2250311
- cbz x0, 1f
-
+workaround_reset_start cortex_a510, ERRATUM(2250311), ERRATA_A510_2250311
/* Disable MPMM */
mrs x0, CPUMPMMCR_EL3
bfm x0, xzr, #0, #0 /* bfc instruction does not work in GCC */
@@ -182,227 +103,68 @@
/* If ENABLE_MPMM is set, tell the runtime lib to skip enabling it. */
bl mpmm_errata_disable
#endif
-
-1:
- ret x17
-endfunc errata_cortex_a510_2250311_wa
-
-func check_errata_2250311
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2250311
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2218950.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2218950_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2218950
- cbz x0, 1f
-
- /* Source register for BFI */
- mov x1, #1
-
- /* Set bit 18 in CPUACTLR_EL1 */
- mrs x0, CORTEX_A510_CPUACTLR_EL1
- bfi x0, x1, #18, #1
- msr CORTEX_A510_CPUACTLR_EL1, x0
-
- /* Set bit 25 in CMPXACTLR_EL1 */
- mrs x0, CORTEX_A510_CMPXACTLR_EL1
- bfi x0, x1, #25, #1
- msr CORTEX_A510_CMPXACTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2218950_wa
+workaround_reset_end cortex_a510, ERRATUM(2250311)
-func check_errata_2218950
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2218950
+check_erratum_ls cortex_a510, ERRATUM(2250311), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2172148.
- * This applies only to revisions r0p0, r0p1, r0p2,
- * r0p3 and r1p0, and is fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_a510_2172148_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2172148
- cbz x0, 1f
-
- /*
- * Force L2 allocation of transient lines by setting
- * CPUECTLR_EL1.RSCTL=0b01 and CPUECTLR_EL1.NTCTL=0b01.
- */
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, #1
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT, #2
- bfi x0, x1, #CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT, #2
- msr CORTEX_A510_CPUECTLR_EL1, x0
-
-1:
- ret x17
-endfunc errata_cortex_a510_2172148_wa
-
-func check_errata_2172148
- /* Applies to r1p0 and lower */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2172148
+workaround_reset_start cortex_a510, ERRATUM(2288014), ERRATA_A510_2288014
+ /* Apply the workaround by setting IMP_CPUACTLR_EL1[18] = 0b1. */
+ sysreg_bitfield_insert CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE, \
+ CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT, CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2288014)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2347730.
- * This applies to revisions r0p0 - r0p3, r1p0, r1p1.
- * It is fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_cortex_a510_2347730_wa
- mov x17, x30
- bl check_errata_2347730
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2288014), CPU_REV(1, 0)
+workaround_reset_start cortex_a510, ERRATUM(2347730), ERRATA_A510_2347730
/*
* Set CPUACTLR_EL1[17] to 1'b1, which disables
* specific microarchitectural clock gating
* behaviour.
*/
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_17
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2347730_wa
-
-func check_errata_2347730
- /* Applies to revisions r1p1 and lower. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2347730
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_17
+workaround_reset_end cortex_a510, ERRATUM(2347730)
- /*---------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2371937.
- * This applies to revisions r1p1 and lower, and is
- * fixed in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- *---------------------------------------------------
- */
-func errata_cortex_a510_2371937_wa
- mov x17, x30
- bl check_errata_2371937
- cbz x0, 1f
+check_erratum_ls cortex_a510, ERRATUM(2347730), CPU_REV(1, 1)
+workaround_reset_start cortex_a510, ERRATUM(2371937), ERRATA_A510_2371937
/*
* Cacheable atomic operations can be forced
* to be executed near by setting
* IMP_CPUECTLR_EL1.ATOM=0b010. ATOM is found
* in [40:38] of CPUECTLR_EL1.
*/
- mrs x0, CORTEX_A510_CPUECTLR_EL1
- mov x1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR
- bfi x0, x1, CORTEX_A510_CPUECTLR_EL1_ATOM, #3
- msr CORTEX_A510_CPUECTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_a510_2371937_wa
-
-func check_errata_2371937
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2371937
-
- /* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Errata #2666669
- * This applies to revisions r1p1 and lower, and is fixed
- * in r1p2.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ------------------------------------------------------
- */
-func errata_cortex_a510_2666669_wa
- mov x17, x30
- bl check_errata_2666669
- cbz x0, 1f
-
- /*
- * Workaround will set IMP_CPUACTLR_EL1[38]
- * to 0b1.
- */
- mrs x1, CORTEX_A510_CPUACTLR_EL1
- orr x1, x1, CORTEX_A510_CPUACTLR_EL1_BIT_38
- msr CORTEX_A510_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_a510_2666669_wa
+ sysreg_bitfield_insert CORTEX_A510_CPUECTLR_EL1, CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR, \
+ CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT, CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH
+workaround_reset_end cortex_a510, ERRATUM(2371937)
-func check_errata_2666669
- /* Applies to r1p1 and lower */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2666669
+check_erratum_ls cortex_a510, ERRATUM(2371937), CPU_REV(1, 1)
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
- */
- .globl errata_cortex_a510_2684597_wa
-func errata_cortex_a510_2684597_wa
- mov x17, x30
- /* Ensure this errata is only applied to Cortex-A510 cores */
- jump_if_cpu_midr CORTEX_A510_MIDR, 1f
- b 2f
+workaround_reset_start cortex_a510, ERRATUM(2666669), ERRATA_A510_2666669
+ sysreg_bit_set CORTEX_A510_CPUACTLR_EL1, CORTEX_A510_CPUACTLR_EL1_BIT_38
+workaround_reset_end cortex_a510, ERRATUM(2666669)
-1:
- /* Check workaround compatibility. */
- mov x0, x18
- bl check_errata_2684597
- cbz x0, 2f
+check_erratum_ls cortex_a510, ERRATUM(2666669), CPU_REV(1, 1)
+.global erratum_cortex_a510_2684597_wa
+workaround_runtime_start cortex_a510, ERRATUM(2684597), ERRATA_A510_2684597, CORTEX_A510_MIDR
/*
* Many assemblers do not yet understand the "tsb csync" mnemonic,
* so use the equivalent hint instruction.
*/
hint #18 /* tsb csync */
-2:
- ret x17
-endfunc errata_cortex_a510_2684597_wa
-/* ------------------------------------------------------
- * Errata Workaround for Cortex-A510 Erratum 2684597.
- * This erratum applies to revision r0p0, r0p1, r0p2,
- * r0p3, r1p0, r1p1 and r1p2 of the Cortex-A510 cpu and
- * is fixed in r1p3.
- * Shall clobber: x0-x17
- * ------------------------------------------------------
+workaround_runtime_end cortex_a510, ERRATUM(2684597)
+
+check_erratum_ls cortex_a510, ERRATUM(2684597), CPU_REV(1, 2)
+
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a510
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func check_errata_2684597
- /* Applies to revision < r1p3 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2684597
+.equ check_erratum_cortex_a510_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_a510_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_a510, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -413,112 +175,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A510_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A510_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A510_CPUPWRCTLR_EL1, CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a510_core_pwr_dwn
- /*
- * Errata printing function for Cortex-A510. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a510_errata_report
- stp x8, x30, [sp, #-16]!
+errata_report_shim cortex_a510
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A510_1922240, cortex_a510, 1922240
- report_errata ERRATA_A510_2041909, cortex_a510, 2041909
- report_errata ERRATA_A510_2042739, cortex_a510, 2042739
- report_errata ERRATA_A510_2172148, cortex_a510, 2172148
- report_errata ERRATA_A510_2218950, cortex_a510, 2218950
- report_errata ERRATA_A510_2250311, cortex_a510, 2250311
- report_errata ERRATA_A510_2288014, cortex_a510, 2288014
- report_errata ERRATA_A510_2347730, cortex_a510, 2347730
- report_errata ERRATA_A510_2371937, cortex_a510, 2371937
- report_errata ERRATA_A510_2666669, cortex_a510, 2666669
- report_errata ERRATA_A510_2684597, cortex_a510, 2684597
- report_errata ERRATA_DSU_2313941, cortex_a510, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a510_errata_report
-#endif
-
-func cortex_a510_reset_func
- mov x19, x30
-
+cpu_reset_func_start cortex_a510
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_A510_1922240
- mov x0, x18
- bl errata_cortex_a510_1922240_wa
-#endif
-
-#if ERRATA_A510_2288014
- mov x0, x18
- bl errata_cortex_a510_2288014_wa
-#endif
-
-#if ERRATA_A510_2042739
- mov x0, x18
- bl errata_cortex_a510_2042739_wa
-#endif
-
-#if ERRATA_A510_2041909
- mov x0, x18
- bl errata_cortex_a510_2041909_wa
-#endif
-
-#if ERRATA_A510_2250311
- mov x0, x18
- bl errata_cortex_a510_2250311_wa
-#endif
-
-#if ERRATA_A510_2218950
- mov x0, x18
- bl errata_cortex_a510_2218950_wa
-#endif
-
-#if ERRATA_A510_2371937
- mov x0, x18
- bl errata_cortex_a510_2371937_wa
-#endif
-
-#if ERRATA_A510_2172148
- mov x0, x18
- bl errata_cortex_a510_2172148_wa
-#endif
-
-#if ERRATA_A510_2347730
- mov x0, x18
- bl errata_cortex_a510_2347730_wa
-#endif
-
-#if ERRATA_A510_2666669
- mov x0, x18
- bl errata_cortex_a510_2666669_wa
-#endif
-
- isb
- ret x19
-endfunc cortex_a510_reset_func
+cpu_reset_func_end cortex_a510
/* ---------------------------------------------
* This function provides Cortex-A510 specific
diff --git a/lib/cpus/aarch64/cortex_a520.S b/lib/cpus/aarch64/cortex_a520.S
index 5bbe862..6c2f33e 100644
--- a/lib/cpus/aarch64/cortex_a520.S
+++ b/lib/cpus/aarch64/cortex_a520.S
@@ -30,28 +30,17 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A520_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A520_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A520_CPUPWRCTLR_EL1, CORTEX_A520_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a520_core_pwr_dwn
- /*
- * Errata printing function for Cortex A520. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a520_errata_report
- ret
-endfunc cortex_a520_errata_report
-#endif
+errata_report_shim cortex_a520
-func cortex_a520_reset_func
+cpu_reset_func_start cortex_a520
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_a520_reset_func
+cpu_reset_func_end cortex_a520
/* ---------------------------------------------
* This function provides Cortex A520 specific
diff --git a/lib/cpus/aarch64/cortex_a55.S b/lib/cpus/aarch64/cortex_a55.S
index 0e0388b..712b6e0 100644
--- a/lib/cpus/aarch64/cortex_a55.S
+++ b/lib/cpus/aarch64/cortex_a55.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -18,63 +18,37 @@
.globl cortex_a55_reset_func
.globl cortex_a55_core_pwr_dwn
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #768277.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_768277_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_768277
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_768277_wa
-func check_errata_768277
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_768277
+/* ERRATA_DSU_798953:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_798953, check_errata_dsu_798953
+.equ erratum_cortex_a55_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a55, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
- /* ------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #778703.
- * This applies only to revision r0p0 of Cortex A55 where L2 cache is
- * not configured.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ------------------------------------------------------------------
- */
-func errata_a55_778703_wa
- /*
- * Compare x0 against revision r0p0 and check that no private L2 cache
- * is configured
- */
- mov x17, x30
- bl check_errata_778703
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUECTLR_EL1_L1WSCTL
- msr CORTEX_A55_CPUECTLR_EL1, x1
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_778703_wa
+/* ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S but applies to cortex_a55
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a55_936184, check_errata_dsu_936184
+.equ erratum_cortex_a55_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a55, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+
+workaround_reset_start cortex_a55, ERRATUM(768277), ERRATA_A55_768277
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(768277)
-func check_errata_778703
+check_erratum_ls cortex_a55, ERRATUM(768277), CPU_REV(0, 0)
+
+workaround_reset_start cortex_a55, ERRATUM(778703), ERRATA_A55_778703
+ sysreg_bit_set CORTEX_A55_CPUECTLR_EL1, CORTEX_A55_CPUECTLR_EL1_L1WSCTL
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_WRITE_STREAMING
+workaround_reset_end cortex_a55, ERRATUM(778703)
+
+check_erratum_custom_start cortex_a55, ERRATUM(778703)
mov x16, x30
mov x1, #0x00
bl cpu_rev_var_ls
@@ -87,111 +61,27 @@
mov x2, #ERRATA_NOT_APPLIES
csel x0, x0, x2, eq
ret x16
-endfunc check_errata_778703
+check_erratum_custom_end cortex_a55, ERRATUM(778703)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #798797.
- * This applies only to revision r0p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a55_798797_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_798797
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_798797_wa
+workaround_reset_start cortex_a55, ERRATUM(798797), ERRATA_A55_798797
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(798797)
-func check_errata_798797
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_798797
+check_erratum_ls cortex_a55, ERRATUM(798797), CPU_REV(0, 0)
- /* --------------------------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #846532.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Disabling dual-issue has a small impact on performance. Disabling a
- * power optimization feature is an alternate workaround with no impact
- * on performance but with an increase in power consumption (see errata
- * notice).
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a55_846532_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_846532
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_846532_wa
+workaround_reset_start cortex_a55, ERRATUM(846532), ERRATA_A55_846532
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_DUAL_ISSUE
+workaround_reset_end cortex_a55, ERRATUM(846532)
-func check_errata_846532
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_846532
+check_erratum_ls cortex_a55, ERRATUM(846532), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #903758.
- * This applies only to revisions <= r0p1 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_903758_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_903758
- cbz x0, 1f
- mrs x1, CORTEX_A55_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
- msr CORTEX_A55_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a55_903758_wa
+workaround_reset_start cortex_a55, ERRATUM(903758), ERRATA_A55_903758
+ sysreg_bit_set CORTEX_A55_CPUACTLR_EL1, CORTEX_A55_CPUACTLR_EL1_DISABLE_L1_PAGEWALKS
+workaround_reset_end cortex_a55, ERRATUM(903758)
-func check_errata_903758
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_903758
+check_erratum_ls cortex_a55, ERRATUM(903758), CPU_REV(0, 1)
- /* -----------------------------------------------------
- * Errata Workaround for Cortex A55 Errata #1221012.
- * This applies only to revisions <= r1p0 of Cortex A55.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------
- */
-func errata_a55_1221012_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1221012
- cbz x0, 1f
+workaround_reset_start cortex_a55, ERRATUM(1221012), ERRATA_A55_1221012
mov x0, #0x0020
movk x0, #0x0850, lsl #16
msr CPUPOR_EL3, x0
@@ -214,121 +104,30 @@
mov x0, #0x03fd
movk x0, #0x0110, lsl #16
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_a55_1221012_wa
+workaround_reset_end cortex_a55, ERRATUM(1221012)
-func check_errata_1221012
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1221012
+check_erratum_ls cortex_a55, ERRATUM(1221012), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata workaround for Cortex A55 Errata #1530923.
- * This applies to all revisions of Cortex A55.
- * --------------------------------------------------
- */
-func check_errata_1530923
-#if ERRATA_A55_1530923
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_1530923
-
-func cortex_a55_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A55_768277
- mov x0, x18
- bl errata_a55_768277_wa
-#endif
-
-#if ERRATA_A55_778703
- mov x0, x18
- bl errata_a55_778703_wa
-#endif
-
-#if ERRATA_A55_798797
- mov x0, x18
- bl errata_a55_798797_wa
-#endif
+check_erratum_chosen cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923
-#if ERRATA_A55_846532
- mov x0, x18
- bl errata_a55_846532_wa
-#endif
-
-#if ERRATA_A55_903758
- mov x0, x18
- bl errata_a55_903758_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a55, ERRATUM(1530923), ERRATA_A55_1530923, NO_APPLY_AT_RESET
-#if ERRATA_A55_1221012
- mov x0, x18
- bl errata_a55_1221012_wa
-#endif
+cpu_reset_func_start cortex_a55
+cpu_reset_func_end cortex_a55
- ret x19
-endfunc cortex_a55_reset_func
+errata_report_shim cortex_a55
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a55_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A55_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A55_CORE_PWRDN_EN_MASK
- msr CORTEX_A55_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A55_CPUPWRCTLR_EL1, CORTEX_A55_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a55_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A55. Must follow AAPCS & can use stack.
- */
-func cortex_a55_errata_report
- stp x8, x30, [sp, #-16]!
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision variant information is at x8, where
- * "report_errata" is expecting it and it doesn't corrupt it.
- */
- report_errata ERRATA_DSU_798953, cortex_a55, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a55, dsu_936184
- report_errata ERRATA_A55_768277, cortex_a55, 768277
- report_errata ERRATA_A55_778703, cortex_a55, 778703
- report_errata ERRATA_A55_798797, cortex_a55, 798797
- report_errata ERRATA_A55_846532, cortex_a55, 846532
- report_errata ERRATA_A55_903758, cortex_a55, 903758
- report_errata ERRATA_A55_1221012, cortex_a55, 1221012
- report_errata ERRATA_A55_1530923, cortex_a55, 1530923
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a55_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a55 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a65ae.S b/lib/cpus/aarch64/cortex_a65ae.S
index ac6583e..85d1894 100644
--- a/lib/cpus/aarch64/cortex_a65ae.S
+++ b/lib/cpus/aarch64/cortex_a65ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -22,49 +22,26 @@
#error "Cortex-A65AE supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-/* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A65.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a65ae_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+ /*
+ * ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a65ae
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a65ae_936184, check_errata_dsu_936184
+.equ erratum_cortex_a65ae_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a65ae, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc cortex_a65ae_reset_func
+cpu_reset_func_start cortex_a65ae
+cpu_reset_func_end cortex_a65ae
func cortex_a65ae_cpu_pwr_dwn
- mrs x0, CORTEX_A65AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A65AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A65AE_CPUPWRCTLR_EL1, CORTEX_A65AE_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_a65ae_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A65AE. Must follow AAPCS.
- */
-func cortex_a65ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, cortex_a65ae, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a65ae_errata_report
-#endif
+errata_report_shim cortex_a65ae
.section .rodata.cortex_a65ae_regs, "aS"
cortex_a65ae_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/cortex_a715.S b/lib/cpus/aarch64/cortex_a715.S
index 12d969f..dd4c307 100644
--- a/lib/cpus/aarch64/cortex_a715.S
+++ b/lib/cpus/aarch64/cortex_a715.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A715_BHB_LOOP_COUNT, cortex_a715
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_a715_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A715 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a715
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a715
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a715, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_a715_reset_func
+check_erratum_chosen cortex_a715, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_a715
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_a715
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -68,26 +59,7 @@
ret
endfunc cortex_a715_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A715. Must follow AAPCS.
- */
-func cortex_a715_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a715, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a715_errata_report
-#endif
+errata_report_shim cortex_a715
/* ---------------------------------------------
* This function provides Cortex-A715 specific
diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S
index de2d36e..997f261 100644
--- a/lib/cpus/aarch64/cortex_a72.S
+++ b/lib/cpus/aarch64/cortex_a72.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -47,9 +47,7 @@
* ---------------------------------------------
*/
func cortex_a72_disable_hw_prefetcher
- mrs x0, CORTEX_A72_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
- msr CORTEX_A72_CPUACTLR_EL1, x0
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DISABLE_L1_DCACHE_HW_PFTCH
isb
dsb ish
ret
@@ -60,9 +58,7 @@
* ---------------------------------------------
*/
func cortex_a72_disable_smp
- mrs x0, CORTEX_A72_ECTLR_EL1
- bic x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
- msr CORTEX_A72_ECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
ret
endfunc cortex_a72_disable_smp
@@ -78,139 +74,95 @@
ret
endfunc cortex_a72_disable_ext_debug
- /* --------------------------------------------------
- * Errata Workaround for Cortex A72 Errata #859971.
- * This applies only to revision <= r0p3 of Cortex A72.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber:
- * --------------------------------------------------
- */
-func errata_a72_859971_wa
- mov x17,x30
- bl check_errata_859971
- cbz x0, 1f
- mrs x1, CORTEX_A72_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
- msr CORTEX_A72_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a72_859971_wa
-
-func check_errata_859971
- mov x1, #0x03
- b cpu_rev_var_ls
-endfunc check_errata_859971
-
-func check_errata_cve_2017_5715
+func check_smccc_arch_workaround_3
cpu_check_csv2 x0, 1f
-#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_errata_cve_2017_5715
+endfunc check_smccc_arch_workaround_3
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+workaround_reset_start cortex_a72, ERRATUM(859971), ERRATA_A72_859971
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_INSTR_PREFETCH
+workaround_reset_end cortex_a72, ERRATUM(859971)
- /* --------------------------------------------------
- * Errata workaround for Cortex A72 Errata #1319367.
- * This applies to all revisions of Cortex A72.
- * --------------------------------------------------
- */
-func check_errata_1319367
-#if ERRATA_A72_1319367
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
+check_erratum_ls cortex_a72, ERRATUM(859971), CPU_REV(0, 3)
+
+/* Due to the nature of the errata it is applied unconditionally when chosen */
+check_erratum_chosen cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367
+/* erratum workaround is interleaved with generic code */
+add_erratum_entry cortex_a72, ERRATUM(1319367), ERRATA_A72_1319367, NO_APPLY_AT_RESET
+
+workaround_reset_start cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_mmu_vbar
#endif
- ret
-endfunc check_errata_1319367
+workaround_reset_end cortex_a72, CVE(2017, 5715)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
+check_erratum_custom_start cortex_a72, CVE(2017, 5715)
+ cpu_check_csv2 x0, 1f
+#if WORKAROUND_CVE_2017_5715
mov x0, #ERRATA_APPLIES
#else
mov x0, #ERRATA_MISSING
#endif
ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
- cpu_check_csv2 x0, 1f
- mov x0, #ERRATA_APPLIES
- ret
1:
mov x0, #ERRATA_NOT_APPLIES
ret
-endfunc check_smccc_arch_workaround_3
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A72.
- * -------------------------------------------------
- */
-func cortex_a72_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A72_859971
- mov x0, x18
- bl errata_a72_859971_wa
-#endif
+check_erratum_custom_end cortex_a72, CVE(2017, 5715)
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
- cpu_check_csv2 x0, 1f
- adr x0, wa_cve_2017_5715_mmu_vbar
- msr vbar_el3, x0
- /* isb will be performed before returning from this function */
+workaround_reset_start cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A72_CPUACTLR_EL1, CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
+ isb
+ dsb sy
+workaround_reset_end cortex_a72, CVE(2018, 3639)
+check_erratum_chosen cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
- /* Skip CVE_2022_23960 mitigation if cve_2017_5715 mitigation applied */
- b 2f
-1:
-#if WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /* Skip installing vector table again if already done for CVE(2017, 5715) */
/*
* The Cortex-A72 generic vectors are overridden to apply the
- * mitigation on exception entry from lower ELs for revisions >= r1p0
+ * mitigation on exception entry from lower ELs for revisions >= r1p0
* which has CSV2 implemented.
*/
adr x0, wa_cve_vbar_cortex_a72
+ mrs x1, vbar_el3
+ cmp x0, x1
+ b.eq 1f
msr vbar_el3, x0
+1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a72, CVE(2022, 23960)
- /* isb will be performed before returning from this function */
+check_erratum_custom_start cortex_a72, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+ cpu_check_csv2 x0, 1f
+ mov x0, #ERRATA_APPLIES
+ ret
+1:
+#if WORKAROUND_CVE_2022_23960
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
#endif /* WORKAROUND_CVE_2022_23960 */
-2:
-#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+ ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+ mov x0, #ERRATA_MISSING
+ ret
+check_erratum_custom_end cortex_a72, CVE(2022, 23960)
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A72_CPUACTLR_EL1
- orr x0, x0, #CORTEX_A72_CPUACTLR_EL1_DIS_LOAD_PASS_STORE
- msr CORTEX_A72_CPUACTLR_EL1, x0
- isb
- dsb sy
-#endif
+cpu_reset_func_start cortex_a72
/* ---------------------------------------------
* Enable the SMP bit.
* ---------------------------------------------
*/
- mrs x0, CORTEX_A72_ECTLR_EL1
- orr x0, x0, #CORTEX_A72_ECTLR_SMP_BIT
- msr CORTEX_A72_ECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a72_reset_func
+ sysreg_bit_set CORTEX_A72_ECTLR_EL1, CORTEX_A72_ECTLR_SMP_BIT
+
+cpu_reset_func_end cortex_a72
/* ----------------------------------------------------
* The CPU Ops core power down function for Cortex-A72.
@@ -319,30 +271,7 @@
b cortex_a72_disable_ext_debug
endfunc cortex_a72_cluster_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A72. Must follow AAPCS.
- */
-func cortex_a72_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A72_859971, cortex_a72, 859971
- report_errata ERRATA_A72_1319367, cortex_a72, 1319367
- report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a72_errata_report
-#endif
+errata_report_shim cortex_a72
/* ---------------------------------------------
* This function provides cortex_a72 specific
@@ -367,7 +296,7 @@
declare_cpu_ops_wa cortex_a72, CORTEX_A72_MIDR, \
cortex_a72_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a72_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a72_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S
index 529ab50..4b28fdb 100644
--- a/lib/cpus/aarch64/cortex_a720.S
+++ b/lib/cpus/aarch64/cortex_a720.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_a720_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex A720 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a720
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a720
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a720, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_a720_reset_func
+check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_a720
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_a720
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -61,33 +52,13 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A720_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A720_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A720_CPUPWRCTLR_EL1, CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
isb
ret
endfunc cortex_a720_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A720. Must follow AAPCS.
- */
-func cortex_a720_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a720, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a720_errata_report
-#endif
+errata_report_shim cortex_a720
/* ---------------------------------------------
* This function provides Cortex A720-specific
diff --git a/lib/cpus/aarch64/cortex_a73.S b/lib/cpus/aarch64/cortex_a73.S
index edcd1f5..a7435c7 100644
--- a/lib/cpus/aarch64/cortex_a73.S
+++ b/lib/cpus/aarch64/cortex_a73.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2016-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -15,9 +15,7 @@
* ---------------------------------------------
*/
func cortex_a73_disable_dcache
- mrs x1, sctlr_el3
- bic x1, x1, #SCTLR_C_BIT
- msr sctlr_el3, x1
+ sysreg_bit_clear sctlr_el3, SCTLR_C_BIT
isb
ret
endfunc cortex_a73_disable_dcache
@@ -27,124 +25,95 @@
* ---------------------------------------------
*/
func cortex_a73_disable_smp
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
+ sysreg_bit_clear CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
isb
dsb sy
ret
endfunc cortex_a73_disable_smp
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #852427.
- * This applies only to revision r0p0 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_852427_wa
- /*
- * Compare x0 against revision r0p0
- */
- mov x17, x30
- bl check_errata_852427
- cbz x0, 1f
- mrs x1, CORTEX_A73_DIAGNOSTIC_REGISTER
- orr x1, x1, #(1 << 12)
- msr CORTEX_A73_DIAGNOSTIC_REGISTER, x1
- isb
-1:
- ret x17
-endfunc errata_a73_852427_wa
+func check_smccc_arch_workaround_3
+ mov x0, #ERRATA_APPLIES
+ ret
+endfunc check_smccc_arch_workaround_3
-func check_errata_852427
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_852427
+workaround_reset_start cortex_a73, ERRATUM(852427), ERRATA_A73_852427
+ sysreg_bit_set CORTEX_A73_DIAGNOSTIC_REGISTER, BIT(12)
+workaround_reset_end cortex_a73, ERRATUM(852427)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A73 Errata #855423.
- * This applies only to revision <= r0p1 of Cortex A73.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------
- */
-func errata_a73_855423_wa
- /*
- * Compare x0 against revision r0p1
- */
- mov x17, x30
- bl check_errata_855423
- cbz x0, 1f
- mrs x1, CORTEX_A73_IMP_DEF_REG2
- orr x1, x1, #(1 << 7)
- msr CORTEX_A73_IMP_DEF_REG2, x1
- isb
-1:
- ret x17
-endfunc errata_a73_855423_wa
+check_erratum_ls cortex_a73, ERRATUM(852427), CPU_REV(0, 0)
-func check_errata_855423
- mov x1, #0x01
- b cpu_rev_var_ls
-endfunc check_errata_855423
+workaround_reset_start cortex_a73, ERRATUM(855423), ERRATA_A73_855423
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG2, BIT(7)
+workaround_reset_end cortex_a73, ERRATUM(855423)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A73.
- * -------------------------------------------------
- */
+check_erratum_ls cortex_a73, ERRATUM(855423), CPU_REV(0, 1)
-func cortex_a73_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+workaround_reset_start cortex_a73, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ override_vector_table wa_cve_2017_5715_bpiall_vbar
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_852427
- mov x0, x18
- bl errata_a73_852427_wa
+check_erratum_custom_start cortex_a73, CVE(2017, 5715)
+ cpu_check_csv2 x0, 1f
+#if WORKAROUND_CVE_2017_5715
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
#endif
+ ret
+1:
+ mov x0, #ERRATA_NOT_APPLIES
+ ret
+check_erratum_custom_end cortex_a73, CVE(2017, 5715)
-#if ERRATA_A73_855423
- mov x0, x18
- bl errata_a73_855423_wa
-#endif
+workaround_reset_start cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+ sysreg_bit_set CORTEX_A73_IMP_DEF_REG1, CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
+workaround_reset_end cortex_a73, CVE(2018, 3639)
-#if IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960)
- cpu_check_csv2 x0, 1f
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
+check_erratum_chosen cortex_a73, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+
+workaround_reset_start cortex_a73, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/* Skip installing vector table again for CVE_2022_23960 */
- b 2f
+ override_vector_table wa_cve_2017_5715_bpiall_vbar
+ cmp x0, x1
+ b.eq 1f
+ msr vbar_el3, x0
1:
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a73, CVE(2022, 23960)
+
+check_erratum_custom_start cortex_a73, CVE(2022, 23960)
+#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
+ cpu_check_csv2 x0, 1f
+ mov x0, #ERRATA_APPLIES
+ ret
+ 1:
#if WORKAROUND_CVE_2022_23960
- adr x0, wa_cve_2017_5715_bpiall_vbar
- msr vbar_el3, x0
- isb
-#endif
-2:
-#endif /* IMAGE_BL31 && (WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960) */
+ mov x0, #ERRATA_APPLIES
+#else
+ mov x0, #ERRATA_MISSING
+#endif /* WORKAROUND_CVE_2022_23960 */
+ ret
+#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
+ mov x0, #ERRATA_MISSING
+ ret
+check_erratum_custom_end cortex_a73, CVE(2022, 23960)
-#if WORKAROUND_CVE_2018_3639
- mrs x0, CORTEX_A73_IMP_DEF_REG1
- orr x0, x0, #CORTEX_A73_IMP_DEF_REG1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A73_IMP_DEF_REG1, x0
- isb
-#endif
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A73.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a73
/* ---------------------------------------------
* Enable the SMP bit.
* Clobbers : x0
* ---------------------------------------------
*/
- mrs x0, CORTEX_A73_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A73_CPUECTLR_SMP_BIT
- msr CORTEX_A73_CPUECTLR_EL1, x0
- isb
- ret x19
-endfunc cortex_a73_reset_func
+ sysreg_bit_set CORTEX_A73_CPUECTLR_EL1, CORTEX_A73_CPUECTLR_SMP_BIT
+cpu_reset_func_end cortex_a73
func cortex_a73_core_pwr_dwn
mov x18, x30
@@ -207,74 +176,8 @@
b cortex_a73_disable_smp
endfunc cortex_a73_cluster_pwr_dwn
-func check_errata_cve_2017_5715
- cpu_check_csv2 x0, 1f
-#if WORKAROUND_CVE_2017_5715
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-1:
- mov x0, #ERRATA_NOT_APPLIES
- ret
-endfunc check_errata_cve_2017_5715
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960
- cpu_check_csv2 x0, 1f
- mov x0, #ERRATA_APPLIES
- ret
- 1:
-# if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-# else
- mov x0, #ERRATA_MISSING
-# endif /* WORKAROUND_CVE_2022_23960 */
- ret
-#endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */
- mov x0, #ERRATA_MISSING
- ret
-endfunc check_errata_cve_2022_23960
-
-func check_smccc_arch_workaround_3
- mov x0, #ERRATA_APPLIES
- ret
-endfunc check_smccc_arch_workaround_3
-
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A75. Must follow AAPCS.
- */
-func cortex_a73_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A73_852427, cortex_a73, 852427
- report_errata ERRATA_A73_855423, cortex_a73, 855423
- report_errata WORKAROUND_CVE_2017_5715, cortex_a73, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, cortex_a73, cve_2018_3639
- report_errata WORKAROUND_CVE_2022_23960, cortex_a73, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a73_errata_report
-#endif
+errata_report_shim cortex_a73
/* ---------------------------------------------
* This function provides cortex_a73 specific
@@ -298,7 +201,7 @@
declare_cpu_ops_wa cortex_a73, CORTEX_A73_MIDR, \
cortex_a73_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_cortex_a73_5715, \
CPU_NO_EXTRA2_FUNC, \
check_smccc_arch_workaround_3, \
cortex_a73_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/cortex_a76.S b/lib/cpus/aarch64/cortex_a76.S
index 36507de..8b3d730 100644
--- a/lib/cpus/aarch64/cortex_a76.S
+++ b/lib/cpus/aarch64/cortex_a76.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -298,154 +298,50 @@
endfunc apply_cve_2018_3639_sync_wa
#endif /* DYNAMIC_WORKAROUND_CVE_2018_3639 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1073348.
- * This applies only to revision <= r1p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1073348_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1 ,#CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1073348_wa
+workaround_reset_start cortex_a76, ERRATUM(1073348), ERRATA_A76_1073348
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1 ,CORTEX_A76_CPUACTLR_EL1_DISABLE_STATIC_PREDICTION
+workaround_reset_end cortex_a76, ERRATUM(1073348)
-func check_errata_1073348
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
+check_erratum_ls cortex_a76, ERRATUM(1073348), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1130799.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1130799_wa
- /*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1 ,#(1 << 59)
+workaround_reset_start cortex_a76, ERRATUM(1130799), ERRATA_A76_1130799
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_59
msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1130799_wa
+workaround_reset_end cortex_a76, ERRATUM(1130799)
-func check_errata_1130799
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
+check_erratum_ls cortex_a76, ERRATUM(1130799), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1220197.
- * This applies only to revision <= r2p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1220197_wa
-/*
- * Compare x0 against revision r2p0
- */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1220197_wa
+workaround_reset_start cortex_a76, ERRATUM(1220197), ERRATA_A76_1220197
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
+workaround_reset_end cortex_a76, ERRATUM(1220197)
-func check_errata_1220197
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+check_erratum_ls cortex_a76, ERRATUM(1220197), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1257314.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1257314_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR3_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
- msr CORTEX_A76_CPUACTLR3_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1257314_wa
+workaround_reset_start cortex_a76, ERRATUM(1257314), ERRATA_A76_1257314
+ sysreg_bit_set CORTEX_A76_CPUACTLR3_EL1, CORTEX_A76_CPUACTLR3_EL1_BIT_10
+workaround_reset_end cortex_a76, ERRATUM(1257314)
-func check_errata_1257314
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+check_erratum_ls cortex_a76, ERRATUM(1257314), CPU_REV(3, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262888.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1262888_wa
- /*
- * Compare x0 against revision r3p0
- */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUECTLR_EL1
- orr x1, x1, CORTEX_A76_CPUECTLR_EL1_BIT_51
- msr CORTEX_A76_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1262888_wa
+workaround_reset_start cortex_a76, ERRATUM(1262606), ERRATA_A76_1262606
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1262606)
-func check_errata_1262888
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+check_erratum_ls cortex_a76, ERRATUM(1262606), CPU_REV(3, 0)
- /* ---------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1286807.
- * This applies only to revision <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * ---------------------------------------------------
- */
-func check_errata_1286807
+workaround_reset_start cortex_a76, ERRATUM(1262888), ERRATA_A76_1262888
+ sysreg_bit_set CORTEX_A76_CPUECTLR_EL1, CORTEX_A76_CPUECTLR_EL1_BIT_51
+workaround_reset_end cortex_a76, ERRATUM(1262888)
+
+check_erratum_ls cortex_a76, ERRATUM(1262888), CPU_REV(3, 0)
+
+workaround_reset_start cortex_a76, ERRATUM(1275112), ERRATA_A76_1275112
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1275112)
+
+check_erratum_ls cortex_a76, ERRATUM(1275112), CPU_REV(3, 0)
+
+check_erratum_custom_start cortex_a76, ERRATUM(1286807)
#if ERRATA_A76_1286807
mov x0, #ERRATA_APPLIES
ret
@@ -453,100 +349,21 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1286807
-
- /* --------------------------------------------------
- * Errata workaround for Cortex A76 Errata #1791580.
- * This applies to revisions <= r4p0 of Cortex A76.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1791580_wa
- /* Compare x0 against revision r4p0 */
- mov x17, x30
- bl check_errata_1791580
- cbz x0, 1f
- mrs x1, CORTEX_A76_CPUACTLR2_EL1
- orr x1, x1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
- msr CORTEX_A76_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a76_1791580_wa
-
-func check_errata_1791580
- /* Applies to everything <=r4p0. */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1791580
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1262606,
- * #1275112, and #1868343. #1262606 and #1275112
- * apply to revisions <= r3p0 and #1868343 applies to
- * revisions <= r4p0.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
+check_erratum_custom_end cortex_a76, ERRATUM(1286807)
-func errata_a76_1262606_1275112_1868343_wa
- mov x17, x30
+workaround_reset_start cortex_a76, ERRATUM(1791580), ERRATA_A76_1791580
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a76, ERRATUM(1791580)
-/* Check for <= r3p0 cases and branch if check passes. */
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112
- bl check_errata_1262606
- cbnz x0, 1f
-#endif
-
-/* Check for <= r4p0 cases and branch if check fails. */
-#if ERRATA_A76_1868343
- bl check_errata_1868343
- cbz x0, 2f
-#endif
-1:
- mrs x1, CORTEX_A76_CPUACTLR_EL1
- orr x1, x1, #CORTEX_A76_CPUACTLR_EL1_BIT_13
- msr CORTEX_A76_CPUACTLR_EL1, x1
- isb
-2:
- ret x17
-endfunc errata_a76_1262606_1275112_1868343_wa
+check_erratum_ls cortex_a76, ERRATUM(1791580), CPU_REV(4, 0)
-func check_errata_1262606
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start cortex_a76, ERRATUM(1868343), ERRATA_A76_1868343
+ sysreg_bit_set CORTEX_A76_CPUACTLR_EL1, CORTEX_A76_CPUACTLR_EL1_BIT_13
+workaround_reset_end cortex_a76, ERRATUM(1868343)
-func check_errata_1275112
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+check_erratum_ls cortex_a76, ERRATUM(1868343), CPU_REV(4, 0)
-func check_errata_1868343
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
-
-/* --------------------------------------------------
- * Errata Workaround for A76 Erratum 1946160.
- * This applies to revisions r3p0 - r4p1 of A76.
- * It also exists in r0p0 - r2p0 but there is no fix
- * in those revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a76_1946160_wa
- /* Compare x0 against revisions r3p0 - r4p1 */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start cortex_a76, ERRATUM(1946160), ERRATA_A76_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -573,68 +390,33 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a76_1946160_wa
+workaround_reset_end cortex_a76, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to revisions r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
-
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-A76 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a76_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
+check_erratum_range cortex_a76, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
+workaround_runtime_start cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a76_2743102_wa
+workaround_runtime_end cortex_a76, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
+check_erratum_ls cortex_a76, ERRATUM(2743102), CPU_REV(4, 1)
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
+check_erratum_chosen cortex_a76, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
func cortex_a76_disable_wa_cve_2018_3639
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- bic x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_clear CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
ret
endfunc cortex_a76_disable_wa_cve_2018_3639
- /* --------------------------------------------------------------
- * Errata Workaround for Cortex A76 Errata #1165522.
- * This applies only to revisions <= r3p0 of Cortex A76.
- * Due to the nature of the errata it is applied unconditionally
- * when built in, report it as applicable in this case
- * --------------------------------------------------------------
- */
-func check_errata_1165522
+/* --------------------------------------------------------------
+ * Errata Workaround for Cortex A76 Errata #1165522.
+ * This applies only to revisions <= r3p0 of Cortex A76.
+ * Due to the nature of the errata it is applied unconditionally
+ * when built in, report it as applicable in this case
+ * --------------------------------------------------------------
+ */
+check_erratum_custom_start cortex_a76, ERRATUM(1165522)
#if ERRATA_A76_1165522
mov x0, #ERRATA_APPLIES
ret
@@ -642,66 +424,32 @@
mov x1, #0x30
b cpu_rev_var_ls
#endif
-endfunc check_errata_1165522
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_custom_end cortex_a76, ERRATUM(1165522)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A76.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a76_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_chosen cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A76_1073348
- mov x0, x18
- bl errata_a76_1073348_wa
-#endif
+/* erratum has no workaround in the cpu. Generic code must take care */
+add_erratum_entry cortex_a76, CVE(2022, 23960), WORKAROUND_CVE_2022_23960, NO_APPLY_AT_RESET
-#if ERRATA_A76_1130799
- mov x0, x18
- bl errata_a76_1130799_wa
-#endif
-
-#if ERRATA_A76_1220197
- mov x0, x18
- bl errata_a76_1220197_wa
-#endif
-
-#if ERRATA_A76_1257314
- mov x0, x18
- bl errata_a76_1257314_wa
-#endif
-
-#if ERRATA_A76_1262606 || ERRATA_A76_1275112 || ERRATA_A76_1868343
- mov x0, x18
- bl errata_a76_1262606_1275112_1868343_wa
-#endif
-
-#if ERRATA_A76_1262888
- mov x0, x18
- bl errata_a76_1262888_wa
-#endif
+/* ERRATA_DSU_798953 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_798953, check_errata_dsu_798953
+.equ erratum_cortex_a76_798953_wa, errata_dsu_798953_wa
+add_erratum_entry cortex_a76, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET
-#if ERRATA_A76_1791580
- mov x0, x18
- bl errata_a76_1791580_wa
-#endif
+/* ERRATA_DSU_936184 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_a76
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_a76_936184, check_errata_dsu_936184
+.equ erratum_cortex_a76_936184_wa, errata_dsu_936184_wa
+add_erratum_entry cortex_a76, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
-#if ERRATA_A76_1946160
- mov x0, x18
- bl errata_a76_1946160_wa
-#endif
+cpu_reset_func_start cortex_a76
#if WORKAROUND_CVE_2018_3639
/* If the PE implements SSBS, we don't need the dynamic workaround */
@@ -714,9 +462,7 @@
#endif
#if DYNAMIC_WORKAROUND_CVE_2018_3639
cbnz x0, 1f
- mrs x0, CORTEX_A76_CPUACTLR2_EL1
- orr x0, x0, #CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
- msr CORTEX_A76_CPUACTLR2_EL1, x0
+ sysreg_bit_set CORTEX_A76_CPUACTLR2_EL1, CORTEX_A76_CPUACTLR2_EL1_DISABLE_LOAD_PASS_STORE
isb
#ifdef IMAGE_BL31
@@ -727,8 +473,7 @@
* If the below vector table is used, skip overriding it again for
* CVE_2022_23960 as both use the same vbar.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
b 2f
#endif /* IMAGE_BL31 */
@@ -743,22 +488,11 @@
* mitigation on exception entry from lower ELs. This will be bypassed
* if DYNAMIC_WORKAROUND_CVE_2018_3639 has overridden the vectors.
*/
- adr x0, cortex_a76_wa_cve_vbar
- msr vbar_el3, x0
+ override_vector_table cortex_a76_wa_cve_vbar
isb
#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
2:
-
-#if ERRATA_DSU_798953
- bl errata_dsu_798953_wa
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
-
- ret x19
-endfunc cortex_a76_reset_func
+cpu_reset_func_end cortex_a76
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -769,55 +503,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A76_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76_CORE_PWRDN_EN_MASK
- msr CORTEX_A76_CPUPWRCTLR_EL1, x0
-#if ERRATA_A76_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a76_2743102_wa
- mov x30, x15
-#endif /* ERRATA_A76_2743102 */
+ sysreg_bit_set CORTEX_A76_CPUPWRCTLR_EL1, CORTEX_A76_CORE_PWRDN_EN_MASK
+
+ apply_erratum cortex_a76, ERRATUM(2743102), ERRATA_A76_2743102
+
isb
ret
endfunc cortex_a76_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A76. Must follow AAPCS.
- */
-func cortex_a76_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A76_1073348, cortex_a76, 1073348
- report_errata ERRATA_A76_1130799, cortex_a76, 1130799
- report_errata ERRATA_A76_1165522, cortex_a76, 1165522
- report_errata ERRATA_A76_1220197, cortex_a76, 1220197
- report_errata ERRATA_A76_1257314, cortex_a76, 1257314
- report_errata ERRATA_A76_1262606, cortex_a76, 1262606
- report_errata ERRATA_A76_1262888, cortex_a76, 1262888
- report_errata ERRATA_A76_1275112, cortex_a76, 1275112
- report_errata ERRATA_A76_1286807, cortex_a76, 1286807
- report_errata ERRATA_A76_1791580, cortex_a76, 1791580
- report_errata ERRATA_A76_1868343, cortex_a76, 1868343
- report_errata ERRATA_A76_1946160, cortex_a76, 1946160
- report_errata ERRATA_A76_2743102, cortex_a76, 2743102
- report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
- report_errata ERRATA_DSU_798953, cortex_a76, dsu_798953
- report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76_errata_report
-#endif
+errata_report_shim cortex_a76
/* ---------------------------------------------
* This function provides cortex_a76 specific
diff --git a/lib/cpus/aarch64/cortex_a76ae.S b/lib/cpus/aarch64/cortex_a76ae.S
index 5c19548..08a6ef9 100644
--- a/lib/cpus/aarch64/cortex_a76ae.S
+++ b/lib/cpus/aarch64/cortex_a76ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -25,71 +25,34 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A76AE_BHB_LOOP_COUNT, cortex_a76ae
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif /* WORKAROUND_CVE_2022_23960 */
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /* --------------------------------------------
- * The CPU Ops reset function for Cortex-A76AE.
- * Shall clobber: x0-x19
- * --------------------------------------------
- */
-func cortex_a76ae_reset_func
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a76ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A76ae generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a76ae
- msr vbar_el3, x0
+ override_vector_table wa_cve_vbar_cortex_a76ae
isb
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a76ae, CVE(2022, 23960)
- ret
-endfunc cortex_a76ae_reset_func
+cpu_reset_func_start cortex_a76ae
+cpu_reset_func_end cortex_a76ae
+
+errata_report_shim cortex_a76ae
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
*/
func cortex_a76ae_core_pwr_dwn
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
- msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A76AE_CPUPWRCTLR_EL1, CORTEX_A76AE_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_a76ae_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A76AE. Must follow AAPCS.
- */
-func cortex_a76ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_a76ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a76ae_errata_report
-#endif /* REPORT_ERRATA */
-
/* ---------------------------------------------
* This function provides cortex_a76ae specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a77.S b/lib/cpus/aarch64/cortex_a77.S
index 2882df7..86c2561 100644
--- a/lib/cpus/aarch64/cortex_a77.S
+++ b/lib/cpus/aarch64/cortex_a77.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,26 +26,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1508412.
- * This applies only to revision <= r1p0 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1508412_wa
- /*
- * Compare x0 against revision r1p0
- */
- mov x17, x30
- bl check_errata_1508412
- cbz x0, 3f
- /*
- * Compare x0 against revision r0p0
- */
- bl check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
+ /* move cpu revision in again and compare against r0p0 */
+ mov x0, x7
+ mov x1, #CPU_REV(0, 0)
+ bl cpu_rev_var_ls
cbz x0, 1f
+
ldr x0, =0x0
msr CORTEX_A77_CPUPSELR_EL3, x0
ldr x0, =0x00E8400000
@@ -75,64 +62,30 @@
2:
ldr x0, =0x04004003FF
msr CORTEX_A77_CPUPCR_EL3, x0
- isb
-3:
- ret x17
-endfunc errata_a77_1508412_wa
+workaround_reset_end cortex_a77, ERRATUM(1508412)
-func check_errata_1508412
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1508412
+check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
-func check_errata_1508412_0
- mov x1, #0x0
- b cpu_rev_var_ls
-endfunc check_errata_1508412_0
+workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a77, ERRATUM(1791578)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1925769.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1925769_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1925769
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1925769_wa
+workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
+ /* Disable allocation of splintered pages in the L2 TLB */
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_53
+workaround_reset_end cortex_a77, ERRATUM(1800714)
-func check_errata_1925769
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925769
+check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1946167.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1946167_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1946167
- cbz x0, 1f
+workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
+ sysreg_bit_set CORTEX_A77_CPUECTLR_EL1, CORTEX_A77_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a77, ERRATUM(1925769)
+
+check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
+workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
ldr x0,=0x4
msr CORTEX_A77_CPUPSELR_EL3,x0
ldr x0,=0x10E3900002
@@ -159,188 +112,42 @@
msr CORTEX_A77_CPUPMR_EL3,x0
ldr x0,=0x2001003FF
msr CORTEX_A77_CPUPCR_EL3,x0
+workaround_reset_end cortex_a77, ERRATUM(1946167)
- isb
-1:
- ret x17
-endfunc errata_a77_1946167_wa
+check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
-func check_errata_1946167
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1946167
+workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
+ sysreg_bit_set CORTEX_A77_ACTLR2_EL1, CORTEX_A77_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a77, ERRATUM(2356587)
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1791578.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1791578_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791578
- cbz x0, 1f
+check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1791578_wa
-
-func check_errata_1791578
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1791578
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2356587.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_2356587_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2356587
- cbz x0, 1f
-
- /* Set bit 0 in ACTLR2_EL1 */
- mrs x1, CORTEX_A77_ACTLR2_EL1
- orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
- msr CORTEX_A77_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_2356587_wa
-
-func check_errata_2356587
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2356587
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #2743100
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_a77_2743100_wa
- mov x17, x30
- bl check_errata_2743100
- cbz x0, 1f
-
+workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a77_2743100_wa
+workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
-func check_errata_2743100
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2743100
+check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex A77 Errata #1800714.
- * This applies to revision <= r1p1 of Cortex A77.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a77_1800714_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1800714
- cbz x0, 1f
-
- /* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A77_CPUECTLR_EL1
- orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
- msr CORTEX_A77_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a77_1800714_wa
-
-func check_errata_1800714
- /* Applies to everything <= r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1800714
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A77.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_a77_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A77_1508412
- mov x0, x18
- bl errata_a77_1508412_wa
-#endif
-
-#if ERRATA_A77_1925769
- mov x0, x18
- bl errata_a77_1925769_wa
-#endif
-
-#if ERRATA_A77_1946167
- mov x0, x18
- bl errata_a77_1946167_wa
-#endif
-
-#if ERRATA_A77_1791578
- mov x0, x18
- bl errata_a77_1791578_wa
-#endif
-
-#if ERRATA_A77_2356587
- mov x0, x18
- bl errata_a77_2356587_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A77 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
adr x0, wa_cve_vbar_cortex_a77
msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a77, CVE(2022, 23960)
-#if ERRATA_A77_1800714
- mov x0, x18
- bl errata_a77_1800714_wa
-#endif
+check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- isb
- ret x19
-endfunc cortex_a77_reset_func
+ /* -------------------------------------------------
+ * The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
+ * -------------------------------------------------
+ */
+cpu_reset_func_start cortex_a77
+cpu_reset_func_end cortex_a77
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -351,48 +158,16 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, CORTEX_A77_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_A77_CPUPWRCTLR_EL1, x0
-#if ERRATA_A77_2743100
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a77_2743100_wa
- mov x30, x15
-#endif /* ERRATA_A77_2743100 */
- isb
- ret
-endfunc cortex_a77_core_pwr_dwn
+ sysreg_bit_set CORTEX_A77_CPUPWRCTLR_EL1, \
+ CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex-A77. Must follow AAPCS.
- */
-func cortex_a77_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A77_1508412, cortex_a77, 1508412
- report_errata ERRATA_A77_1791578, cortex_a77, 1791578
- report_errata ERRATA_A77_1800714, cortex_a77, 1800714
- report_errata ERRATA_A77_1925769, cortex_a77, 1925769
- report_errata ERRATA_A77_1946167, cortex_a77, 1946167
- report_errata ERRATA_A77_2356587, cortex_a77, 2356587
- report_errata ERRATA_A77_2743100, cortex_a77, 2743100
- report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
+ apply_erratum cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
- ldp x8, x30, [sp], #16
+ isb
ret
-endfunc cortex_a77_errata_report
-#endif
-
+endfunc cortex_a77_core_pwr_dwn
+errata_report_shim cortex_a77
/* ---------------------------------------------
* This function provides Cortex-A77 specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_a78.S b/lib/cpus/aarch64/cortex_a78.S
index 69d7ab0..b5c24e1 100644
--- a/lib/cpus/aarch64/cortex_a78.S
+++ b/lib/cpus/aarch64/cortex_a78.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2023, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,77 +24,25 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_BHB_LOOP_COUNT, cortex_a78
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of A78.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_1
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1688305_wa
+workaround_reset_start cortex_a78, ERRATUM(1688305), ERRATA_A78_1688305
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_1
+workaround_reset_end cortex_a78, ERRATUM(1688305)
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+check_erratum_ls cortex_a78, ERRATUM(1688305), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1941498.
- * This applies to revisions r0p0, r1p0, and r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1941498_wa
- /* Compare x0 against revision <= r1p1 */
- mov x17, x30
- bl check_errata_1941498
- cbz x0, 1f
+workaround_reset_start cortex_a78, ERRATUM(1821534), ERRATA_A78_1821534
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, CORTEX_A78_ACTLR2_EL1_BIT_2
+workaround_reset_end cortex_a78, ERRATUM(1821534)
- /* Set bit 8 in ECTLR_EL1 */
- mrs x1, CORTEX_A78_CPUECTLR_EL1
- orr x1, x1, #CORTEX_A78_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1941498_wa
+check_erratum_ls cortex_a78, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_1941498
- /* Check for revision <= r1p1, might need to be updated later. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1941498
+workaround_reset_start cortex_a78, ERRATUM(1941498), ERRATA_A78_1941498
+ sysreg_bit_set CORTEX_A78_CPUECTLR_EL1, CORTEX_A78_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78, ERRATUM(1941498)
-/* --------------------------------------------------
- * Errata Workaround for A78 Erratum 1951500.
- * This applies to revisions r1p0 and r1p1 of A78.
- * The issue also exists in r0p0 but there is no fix
- * in that revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1951500_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1951500
- cbz x0, 1f
+check_erratum_ls cortex_a78, ERRATUM(1941498), CPU_REV(1, 1)
+workaround_reset_start cortex_a78, ERRATUM(1951500), ERRATA_A78_1951500
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -120,60 +68,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78_1951500_wa
-
-func check_errata_1951500
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951500
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata #1821534.
- * This applies to revisions r0p0 and r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1821534_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
-
- /* Set bit 2 in ACTLR2_EL1 */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #CORTEX_A78_ACTLR2_EL1_BIT_2
- msr CORTEX_A78_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_a78_1821534_wa
+workaround_reset_end cortex_a78, ERRATUM(1951500)
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
+check_erratum_range cortex_a78, ERRATUM(1951500), CPU_REV(1, 0), CPU_REV(1, 1)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 1952683.
- * This applies to revision r0p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_1952683_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_1952683
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(1952683), ERRATA_A78_1952683
ldr x0,=0x5
msr S3_6_c15_c8_0,x0
ldr x0,=0xEEE10A10
@@ -194,61 +93,21 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000080023ff
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_a78_1952683_wa
+workaround_reset_end cortex_a78, ERRATUM(1952683)
-func check_errata_1952683
- /* Applies to r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1952683
+check_erratum_ls cortex_a78, ERRATUM(1952683), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2132060.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2132060_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2132060
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2132060), ERRATA_A78_2132060
/* Apply the workaround. */
mrs x1, CORTEX_A78_CPUECTLR_EL1
mov x0, #CORTEX_A78_CPUECTLR_EL1_PF_MODE_CNSRV
bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
msr CORTEX_A78_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2132060_wa
+workaround_reset_end cortex_a78, ERRATUM(2132060)
-func check_errata_2132060
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2132060
+check_erratum_ls cortex_a78, ERRATUM(2132060), CPU_REV(1, 2)
-/* --------------------------------------------------------------------
- * Errata Workaround for A78 Erratum 2242635.
- * This applies to revisions r1p0, r1p1, and r1p2 of the Cortex A78
- * processor and is still open.
- * The issue also exists in r0p0 but there is no fix in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------------------------
- */
-func errata_a78_2242635_wa
- /* Compare x0 against revisions r1p0 - r1p2 */
- mov x17, x30
- bl check_errata_2242635
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2242635), ERRATA_A78_2242635
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -257,242 +116,64 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end cortex_a78, ERRATUM(2242635)
- isb
-1:
- ret x17
-endfunc errata_a78_2242635_wa
+check_erratum_range cortex_a78, ERRATUM(2242635), CPU_REV(1, 0), CPU_REV(1, 2)
-func check_errata_2242635
- /* Applies to revisions r1p0 through r1p2. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242635
+workaround_reset_start cortex_a78, ERRATUM(2376745), ERRATA_A78_2376745
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_a78, ERRATUM(2376745)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2376745.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2376745_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2376745
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2376745_wa
+check_erratum_ls cortex_a78, ERRATUM(2376745), CPU_REV(1, 2)
-func check_errata_2376745
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2376745
+workaround_reset_start cortex_a78, ERRATUM(2395406), ERRATA_A78_2395406
+ sysreg_bit_set CORTEX_A78_ACTLR2_EL1, BIT(40)
+workaround_reset_end cortex_a78, ERRATUM(2395406)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2395406.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78_2395406_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395406
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, CORTEX_A78_ACTLR2_EL1
- orr x1, x1, #BIT(40)
- msr CORTEX_A78_ACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78_2395406_wa
+check_erratum_ls cortex_a78, ERRATUM(2395406), CPU_REV(1, 2)
-func check_errata_2395406
- /* Applies to r0p0, r0p1, r1p1, and r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2395406
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2742426.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2742426_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2742426
- cbz x0, 1f
-
+workaround_reset_start cortex_a78, ERRATUM(2742426), ERRATA_A78_2742426
/* Apply the workaround */
mrs x1, CORTEX_A78_ACTLR5_EL1
bic x1, x1, #BIT(56)
orr x1, x1, #BIT(55)
msr CORTEX_A78_ACTLR5_EL1, x1
+workaround_reset_end cortex_a78, ERRATUM(2742426)
-1:
- ret x17
-endfunc errata_a78_2742426_wa
+check_erratum_ls cortex_a78, ERRATUM(2742426), CPU_REV(1, 2)
-func check_errata_2742426
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2742426
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex-A78 Errata 2772019
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_a78_2772019_wa
- mov x17, x30
- bl check_errata_2772019
- cbz x0, 1f
-
-
+workaround_runtime_start cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_a78_2772019_wa
-
-func check_errata_2772019
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2772019
-
-/* ----------------------------------------------------
- * Errata Workaround for Cortex A78 Errata 2779479.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
- */
-func errata_a78_2779479_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779479
- cbz x0, 1f
+workaround_runtime_end cortex_a78, ERRATUM(2772019)
- /* Apply the workaround */
- mrs x1, CORTEX_A78_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78_ACTLR3_EL1, x1
-
-1:
- ret x17
-endfunc errata_a78_2779479_wa
+check_erratum_ls cortex_a78, ERRATUM(2772019), CPU_REV(1, 2)
-func check_errata_2779479
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779479
+workaround_reset_start cortex_a78, ERRATUM(2779479), ERRATA_A78_2779479
+ sysreg_bit_set CORTEX_A78_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78, ERRATUM(2779479)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78, ERRATUM(2779479), CPU_REV(1, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78
- * -------------------------------------------------
+workaround_reset_start cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78_1688305
- mov x0, x18
- bl errata_a78_1688305_wa
-#endif
-
-#if ERRATA_A78_1941498
- mov x0, x18
- bl errata_a78_1941498_wa
-#endif
-
-#if ERRATA_A78_1951500
- mov x0, x18
- bl errata_a78_1951500_wa
-#endif
-
-#if ERRATA_A78_1821534
- mov x0, x18
- bl errata_a78_1821534_wa
-#endif
-
-#if ERRATA_A78_1952683
- mov x0, x18
- bl errata_a78_1952683_wa
-#endif
-
-#if ERRATA_A78_2132060
- mov x0, x18
- bl errata_a78_2132060_wa
-#endif
+ override_vector_table wa_cve_vbar_cortex_a78
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78, CVE(2022, 23960)
-#if ERRATA_A78_2242635
- mov x0, x18
- bl errata_a78_2242635_wa
-#endif
-
-#if ERRATA_A78_2376745
- mov x0, x18
- bl errata_a78_2376745_wa
-#endif
+check_erratum_chosen cortex_a78, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_2395406
- mov x0, x18
- bl errata_a78_2395406_wa
-#endif
-
-#if ERRATA_A78_2742426
- mov x0, x18
- bl errata_a78_2742426_wa
-#endif
-
-#if ERRATA_A78_2779479
- mov x0, x18
- bl errata_a78_2779479_wa
-#endif
-
+cpu_reset_func_start cortex_a78
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -502,74 +183,22 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_reset_func
+cpu_reset_func_end cortex_a78
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_a78_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78_2772019
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78_2772019_wa
- mov x30, x15
-#endif /* ERRATA_A78_2772019 */
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78, ERRATUM(2772019), ERRATA_A78_2772019
+
isb
ret
endfunc cortex_a78_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_1688305, cortex_a78, 1688305
- report_errata ERRATA_A78_1941498, cortex_a78, 1941498
- report_errata ERRATA_A78_1951500, cortex_a78, 1951500
- report_errata ERRATA_A78_1821534, cortex_a78, 1821534
- report_errata ERRATA_A78_1952683, cortex_a78, 1952683
- report_errata ERRATA_A78_2132060, cortex_a78, 2132060
- report_errata ERRATA_A78_2242635, cortex_a78, 2242635
- report_errata ERRATA_A78_2376745, cortex_a78, 2376745
- report_errata ERRATA_A78_2395406, cortex_a78, 2395406
- report_errata ERRATA_A78_2742426, cortex_a78, 2742426
- report_errata ERRATA_A78_2772019, cortex_a78, 2772019
- report_errata ERRATA_A78_2779479, cortex_a78, 2779479
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_errata_report
-#endif
+errata_report_shim cortex_a78
/* ---------------------------------------------
* This function provides cortex_a78 specific
diff --git a/lib/cpus/aarch64/cortex_a78_ae.S b/lib/cpus/aarch64/cortex_a78_ae.S
index d56f835..9f729c1 100644
--- a/lib/cpus/aarch64/cortex_a78_ae.S
+++ b/lib/cpus/aarch64/cortex_a78_ae.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2019-2022, ARM Limited. All rights reserved.
+ * Copyright (c) 2019-2023, Arm Limited. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,50 +22,13 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_A78_AE_BHB_LOOP_COUNT, cortex_a78_ae
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1941500.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1941500_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1941500
- cbz x0, 1f
-
- /* Set bit 8 in ECTLR_EL1 */
- mrs x0, CORTEX_A78_AE_CPUECTLR_EL1
- bic x0, x0, #CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
- msr CORTEX_A78_AE_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1941500_wa
+workaround_reset_start cortex_a78_ae, ERRATUM(1941500), ERRATA_A78_AE_1941500
+ sysreg_bit_clear CORTEX_A78_AE_CPUECTLR_EL1, CORTEX_A78_AE_CPUECTLR_EL1_BIT_8
+workaround_reset_end cortex_a78_ae, ERRATUM(1941500)
-func check_errata_1941500
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1941500
+check_erratum_ls cortex_a78_ae, ERRATUM(1941500), CPU_REV(0, 1)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 1951502.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_1951502_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_1951502
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(1951502), ERRATA_A78_AE_1951502
msr S3_6_c15_c8_0, xzr
ldr x0, =0x10E3900002
msr S3_6_c15_c8_2, x0
@@ -91,33 +54,11 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x2001003FF
msr S3_6_c15_c8_1, x0
+workaround_reset_end cortex_a78_ae, ERRATUM(1951502)
- isb
-1:
- ret x17
-endfunc errata_a78_ae_1951502_wa
+check_erratum_ls cortex_a78_ae, ERRATUM(1951502), CPU_REV(0, 1)
-func check_errata_1951502
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_1951502
-
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2376748.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2376748_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2376748
- cbz x0, 1f
-
+workaround_reset_start cortex_a78_ae, ERRATUM(2376748), ERRATA_A78_AE_2376748
/* -------------------------------------------------------
* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM ST to
* behave like PLD/PRFM LD and not cause invalidations to
@@ -126,104 +67,42 @@
* that share data.
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_0
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2376748_wa
-
-func check_errata_2376748
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2376748
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78_ae, ERRATUM(2376748)
-/* --------------------------------------------------
- * Errata Workaround for A78 AE Erratum 2395408.
- * This applies to revisions r0p0 and r0p1 of A78 AE.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78_ae_2395408_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2395408
- cbz x0, 1f
+check_erratum_ls cortex_a78_ae, ERRATUM(2376748), CPU_REV(0, 1)
+workaround_reset_start cortex_a78_ae, ERRATUM(2395408), ERRATA_A78_AE_2395408
/* --------------------------------------------------------
* Disable folding of demand requests into older prefetches
* with L2 miss requests outstanding by setting the
* CPUACTLR2_EL1[40] to 1.
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78_AE_ACTLR2_EL1
- orr x0, x0, #CORTEX_A78_AE_ACTLR2_EL1_BIT_40
- msr CORTEX_A78_AE_ACTLR2_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78_ae_2395408_wa
-
-func check_errata_2395408
- /* Applies to revisions r0p0 and r0p1. */
- mov x1, #CPU_REV(0, 0)
- mov x2, #CPU_REV(0, 1)
- b cpu_rev_var_range
-endfunc check_errata_2395408
+ sysreg_bit_set CORTEX_A78_AE_ACTLR2_EL1, CORTEX_A78_AE_ACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78_ae, ERRATUM(2395408)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_ls cortex_a78_ae, ERRATUM(2395408), CPU_REV(0, 1)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78-AE
- * -------------------------------------------------
+workaround_reset_start cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-A78AE generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func cortex_a78_ae_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+ override_vector_table wa_cve_vbar_cortex_a78_ae
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78_ae, CVE(2022, 23960)
-#if ERRATA_A78_AE_1941500
- mov x0, x18
- bl errata_a78_ae_1941500_wa
-#endif
+check_erratum_chosen cortex_a78_ae, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_A78_AE_1951502
- mov x0, x18
- bl errata_a78_ae_1951502_wa
-#endif
-
-#if ERRATA_A78_AE_2376748
- mov x0, x18
- bl errata_a78_ae_2376748_wa
-#endif
-
-#if ERRATA_A78_AE_2395408
- mov x0, x18
- bl errata_a78_ae_2395408_wa
-#endif
-
+cpu_reset_func_start cortex_a78_ae
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el3, x0
+ sysreg_bit_clear actlr_el3, CORTEX_A78_ACTLR_TAM_BIT
/* Make sure accesses from non-secure EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- bic x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
- msr actlr_el2, x0
+ sysreg_bit_clear actlr_el2, CORTEX_A78_ACTLR_TAM_BIT
/* Enable group0 counters */
mov x0, #CORTEX_A78_AMU_GROUP0_MASK
@@ -233,19 +112,7 @@
mov x0, #CORTEX_A78_AMU_GROUP1_MASK
msr CPUAMCNTENSET1_EL0, x0
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-A78AE generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_a78_ae
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_a78_ae_reset_func
+cpu_reset_func_end cortex_a78_ae
/* -------------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -256,37 +123,12 @@
* Enable CPU power down bit in power control register
* -------------------------------------------------------
*/
- mrs x0, CORTEX_A78_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_A78_CPUPWRCTLR_EL1, CORTEX_A78_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
isb
ret
endfunc cortex_a78_ae_core_pwr_dwn
- /*
- * Errata printing function for cortex_a78_ae. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_a78_ae_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78_AE_1941500, cortex_a78_ae, 1941500
- report_errata ERRATA_A78_AE_1951502, cortex_a78_ae, 1951502
- report_errata ERRATA_A78_AE_2376748, cortex_a78_ae, 2376748
- report_errata ERRATA_A78_AE_2395408, cortex_a78_ae, 2395408
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78_ae, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78_ae_errata_report
-#endif
+errata_report_shim cortex_a78_ae
/* -------------------------------------------------------
* This function provides cortex_a78_ae specific
diff --git a/lib/cpus/aarch64/cortex_a78c.S b/lib/cpus/aarch64/cortex_a78c.S
index fddd24f..d19c693 100644
--- a/lib/cpus/aarch64/cortex_a78c.S
+++ b/lib/cpus/aarch64/cortex_a78c.S
@@ -17,174 +17,37 @@
#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827430.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827430_wa
- mov x17, x30
- bl check_errata_1827430
- cbz x0, 1f
+#if WORKAROUND_CVE_2022_23960
+ wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
+#endif /* WORKAROUND_CVE_2022_23960 */
+workaround_reset_start cortex_a78c, ERRATUM(1827430), ERRATA_A78C_1827430
/* Disable allocation of splintered pages in the L2 TLB */
- mrs x1, CORTEX_A78C_CPUECTLR_EL1
- orr x1, x1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
- msr CORTEX_A78C_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827430_wa
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, CORTEX_A78C_CPUECTLR_EL1_MM_ASP_EN
+workaround_reset_end cortex_a78c, ERRATUM(1827430)
-func check_errata_1827430
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827430
+check_erratum_ls cortex_a78c, ERRATUM(1827430), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 1827440.
- * This applies to revision r0p0 of the Cortex A78C
- * processor and is fixed in r0p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_1827440_wa
- mov x17, x30
- bl check_errata_1827440
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(1827440), ERRATA_A78C_1827440
/* Force Atomic Store to WB memory be done in L1 data cache */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_1827440_wa
-
-func check_errata_1827440
- /* Applies to revision r0p0 only */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1827440
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_a78c, ERRATUM(1827440)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2376749.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2376749_wa
- /* Check revision */
- mov x17, x30
- bl check_errata_2376749
- cbz x0, 1f
- /* Set CPUACTLR2_EL1[0] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_0
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2376749_wa
+check_erratum_ls cortex_a78c, ERRATUM(1827440), CPU_REV(0, 0)
-func check_errata_2376749
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2376749
-
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Erratum 2395411.
- * This applies to revision r0p1 and r0p2 of the A78C
- * and is currently open. It is a Cat B erratum.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x4, x17
- * --------------------------------------------------
- */
-func errata_a78c_2395411_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2395411
- cbz x0, 1f
-
- /* Set CPUACTRL2_EL1[40] to 1. */
- mrs x1, CORTEX_A78C_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_A78C_CPUACTLR2_EL1_BIT_40
- msr CORTEX_A78C_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_a78c_2395411_wa
-
-func check_errata_2395411
- /* Applies to r0p1 and r0p2 */
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2395411
-
-#if WORKAROUND_CVE_2022_23960
- wa_cve_2022_23960_bhb_vector_table CORTEX_A78C_BHB_LOOP_COUNT, cortex_a78c
-#endif /* WORKAROUND_CVE_2022_23960 */
-
-/* --------------------------------------------------
- * Errata Workaround for A78C Erratum 2132064.
- * This applies to revisions r0p1 and r0p2 of A78C
- * and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_a78c_2132064_wa
- /* Compare x0 against revisions r0p0 - r0p1 */
- mov x17, x30
- bl check_errata_2132064
- cbz x0, 1f
-
+workaround_reset_start cortex_a78c, ERRATUM(2132064), ERRATA_A78C_2132064
/* --------------------------------------------------------
* Place the data prefetcher in the most conservative mode
* to reduce prefetches by writing the following bits to
* the value indicated: ecltr[7:6], PF_MODE = 2'b11
* --------------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUECTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_6
- orr x0, x0, #CORTEX_A78C_CPUECTLR_EL1_BIT_7
- msr CORTEX_A78C_CPUECTLR_EL1, x0
- isb
-1:
- ret x17
-endfunc errata_a78c_2132064_wa
-
-func check_errata_2132064
- /* Applies to revisions r0p1 and r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2132064
+ sysreg_bit_set CORTEX_A78C_CPUECTLR_EL1, (CORTEX_A78C_CPUECTLR_EL1_BIT_6 | CORTEX_A78C_CPUECTLR_EL1_BIT_7)
+workaround_reset_end cortex_a78c, ERRATUM(2132064)
-/* ----------------------------------------------------------
- * Errata Workaround for A78C Erratum 2242638.
- * This applies to revisions r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------
- */
-func errata_a78c_2242638_wa
- /* Compare x0 against revisions r0p1 - r0p2 */
- mov x17, x30
- bl check_errata_2242638
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2132064), CPU_REV(0, 1), CPU_REV(0, 2)
+workaround_reset_start cortex_a78c, ERRATUM(2242638), ERRATA_A78C_2242638
ldr x0, =0x5
msr CORTEX_A78C_IMP_CPUPSELR_EL3, x0
ldr x0, =0x10F600E000
@@ -193,139 +56,51 @@
msr CORTEX_A78C_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_A78C_IMP_CPUPCR_EL3, x0
-
- isb
-1:
- ret x17
-endfunc errata_a78c_2242638_wa
-
-func check_errata_2242638
- /* Applies to revisions r0p1-r0p2. */
- mov x1, #CPU_REV(0, 1)
- mov x2, #CPU_REV(0, 2)
- b cpu_rev_var_range
-endfunc check_errata_2242638
-
-/* ----------------------------------------------------------------
- * Errata Workaround for A78C Erratum 2772121.
- * This applies to revisions r0p0, r0p1 and r0p2 of the Cortex A78C
- * processor and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------------------
- */
-func errata_a78c_2772121_wa
- mov x17, x30
- bl check_errata_2772121
- cbz x0, 1f
-
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_a78c_2772121_wa
-
-func check_errata_2772121
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2772121
+workaround_reset_end cortex_a78c, ERRATUM(2242638)
-/* --------------------------------------------------
- * Errata Workaround for Cortex A78C Errata 2779484.
- * This applies to revisions r0p1 and r0p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_a78c_2779484_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779484
- cbz x0, 1f
+check_erratum_range cortex_a78c, ERRATUM(2242638), CPU_REV(0, 1), CPU_REV(0, 2)
- /* Apply the workaround */
- mrs x1, CORTEX_A78C_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr CORTEX_A78C_ACTLR3_EL1, x1
+workaround_reset_start cortex_a78c, ERRATUM(2376749), ERRATA_A78C_2376749
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_0
+workaround_reset_end cortex_a78c, ERRATUM(2376749)
-1:
- ret x17
-endfunc errata_a78c_2779484_wa
+check_erratum_range cortex_a78c, ERRATUM(2376749), CPU_REV(0, 1), CPU_REV(0, 2)
-func check_errata_2779484
- /* Applies to r0p1 and r0p2*/
- mov x1, #0x01
- mov x2, #0x02
- b cpu_rev_var_range
-endfunc check_errata_2779484
+workaround_reset_start cortex_a78c, ERRATUM(2395411), ERRATA_A78C_2395411
+ sysreg_bit_set CORTEX_A78C_CPUACTLR2_EL1, CORTEX_A78C_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_a78c, ERRATUM(2395411)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_range cortex_a78c, ERRATUM(2395411), CPU_REV(0, 1), CPU_REV(0, 2)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-A78C
- * -------------------------------------------------
- */
-func cortex_a78c_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_A78C_1827430
- mov x0, x18
- bl errata_a78c_1827430_wa
-#endif
-
-#if ERRATA_A78C_1827440
- mov x0, x18
- bl errata_a78c_1827440_wa
-#endif
-
-#if ERRATA_A78C_2132064
- mov x0, x18
- bl errata_a78c_2132064_wa
-#endif
+workaround_runtime_start cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_runtime_end cortex_a78c, ERRATUM(2772121)
-#if ERRATA_A78C_2242638
- mov x0, x18
- bl errata_a78c_2242638_wa
-#endif
+check_erratum_ls cortex_a78c, ERRATUM(2772121), CPU_REV(0, 2)
-#if ERRATA_A78C_2376749
- mov x0, x18
- bl errata_a78c_2376749_wa
-#endif
+workaround_reset_start cortex_a78c, ERRATUM(2779484), ERRATA_A78C_2779484
+ sysreg_bit_set CORTEX_A78C_ACTLR3_EL1, BIT(47)
+workaround_reset_end cortex_a78c, ERRATUM(2779484)
-#if ERRATA_A78C_2395411
- mov x0, x18
- bl errata_a78c_2395411_wa
-#endif
+check_erratum_range cortex_a78c, ERRATUM(2779484), CPU_REV(0, 1), CPU_REV(0, 2)
-#if ERRATA_A78C_2779484
- mov x0, x18
- bl errata_a78c_2779484_wa
-#endif
+check_erratum_chosen cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_a78c, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-A78c generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_a78c
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_a78c
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_a78c, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_a78c_reset_func
+cpu_reset_func_start cortex_a78c
+cpu_reset_func_end cortex_a78c
+
+errata_report_shim cortex_a78c
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -336,48 +111,14 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
- msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
-#if ERRATA_A78C_2772121
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_a78c_2772121_wa
- mov x30, x15
-#endif /* ERRATA_A78C_2772121 */
+ sysreg_bit_set CORTEX_A78C_CPUPWRCTLR_EL1, CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
+
+ apply_erratum cortex_a78c, ERRATUM(2772121), ERRATA_A78C_2772121
+
isb
ret
endfunc cortex_a78c_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex A78C. Must follow AAPCS.
- */
-func cortex_a78c_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_A78C_1827430, cortex_a78c, 1827430
- report_errata ERRATA_A78C_1827440, cortex_a78c, 1827440
- report_errata ERRATA_A78C_2132064, cortex_a78c, 2132064
- report_errata ERRATA_A78C_2242638, cortex_a78c, 2242638
- report_errata ERRATA_A78C_2376749, cortex_a78c, 2376749
- report_errata ERRATA_A78C_2395411, cortex_a78c, 2395411
- report_errata ERRATA_A78C_2772121, cortex_a78c, 2772121
- report_errata ERRATA_A78C_2779484, cortex_a78c, 2779484
- report_errata WORKAROUND_CVE_2022_23960, cortex_a78c, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_a78c_errata_report
-#endif
-
/* ---------------------------------------------
* This function provides cortex_a78c specific
* register information for crash reporting.
diff --git a/lib/cpus/aarch64/cortex_blackhawk.S b/lib/cpus/aarch64/cortex_blackhawk.S
index 8dac4e9..b7b7a2d 100644
--- a/lib/cpus/aarch64/cortex_blackhawk.S
+++ b/lib/cpus/aarch64/cortex_blackhawk.S
@@ -21,12 +21,10 @@
#error "Cortex blackhawk supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-func cortex_blackhawk_reset_func
+cpu_reset_func_start cortex_blackhawk
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_blackhawk_reset_func
+cpu_reset_func_end cortex_blackhawk
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -37,21 +35,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_BLACKHAWK_CPUPWRCTLR_EL1, CORTEX_BLACKHAWK_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_blackhawk_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Blackhawk. Must follow AAPCS.
- */
-func cortex_blackhawk_errata_report
- ret
-endfunc cortex_blackhawk_errata_report
-#endif
+errata_report_shim cortex_blackhawk
/* ---------------------------------------------
* This function provides Cortex Blackhawk specific
diff --git a/lib/cpus/aarch64/cortex_chaberton.S b/lib/cpus/aarch64/cortex_chaberton.S
index 2c47bd3..596fe4a 100644
--- a/lib/cpus/aarch64/cortex_chaberton.S
+++ b/lib/cpus/aarch64/cortex_chaberton.S
@@ -21,12 +21,10 @@
#error "Cortex Chaberton supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
-func cortex_chaberton_reset_func
+cpu_reset_func_start cortex_chaberton
/* Disable speculative loads */
msr SSBS, xzr
- isb
- ret
-endfunc cortex_chaberton_reset_func
+cpu_reset_func_end cortex_chaberton
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -37,21 +35,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_CHABERTON_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_CHABERTON_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_CHABERTON_CPUPWRCTLR_EL1, CORTEX_CHABERTON_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_chaberton_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex Chaberton. Must follow AAPCS.
- */
-func cortex_chaberton_errata_report
- ret
-endfunc cortex_chaberton_errata_report
-#endif
+errata_report_shim cortex_chaberton
/* ---------------------------------------------
* This function provides Cortex Chaberton specific
diff --git a/lib/cpus/aarch64/cortex_x1.S b/lib/cpus/aarch64/cortex_x1.S
index de65365..42634f1 100644
--- a/lib/cpus/aarch64/cortex_x1.S
+++ b/lib/cpus/aarch64/cortex_x1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2022, Google LLC. All rights reserved.
+ * Copyright (c) 2022-2023, Google LLC. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -23,175 +23,50 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X1_BHB_LOOP_COUNT, cortex_x1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1821534.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1821534_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1821534
- cbz x0, 1f
- mrs x1, CORTEX_X1_ACTLR2_EL1
- orr x1, x1, #BIT(2)
- msr CORTEX_X1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x1_1821534_wa
-
-func check_errata_1821534
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1821534
-
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1688305.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1688305_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1688305
- cbz x0, 1f
- mrs x0, CORTEX_X1_ACTLR2_EL1
- orr x0, x0, #BIT(1)
- msr CORTEX_X1_ACTLR2_EL1, x0
- isb
-
-1:
- ret x17
-endfunc errata_x1_1688305_wa
-
-func check_errata_1688305
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1688305
+workaround_reset_start cortex_x1, ERRATUM(1688305), ERRATA_X1_1688305
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(1)
+workaround_reset_end cortex_x1, ERRATUM(1688305)
-/* --------------------------------------------------
- * Errata Workaround for X1 Erratum 1827429.
- * This applies to revision r0p0 and r1p0 of X1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_x1_1827429_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1827429
- cbz x0, 1f
- mrs x0, CORTEX_X1_CPUECTLR_EL1
- orr x0, x0, #BIT(53)
- msr CORTEX_X1_CPUECTLR_EL1, x0
- isb
+check_erratum_ls cortex_x1, ERRATUM(1688305), CPU_REV(1, 0)
-1:
- ret x17
-endfunc errata_x1_1827429_wa
+workaround_reset_start cortex_x1, ERRATUM(1821534), ERRATA_X1_1821534
+ sysreg_bit_set CORTEX_X1_ACTLR2_EL1, BIT(2)
+workaround_reset_end cortex_x1, ERRATUM(1821534)
-func check_errata_1827429
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1827429
+check_erratum_ls cortex_x1, ERRATUM(1821534), CPU_REV(1, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start cortex_x1, ERRATUM(1827429), ERRATA_X1_1827429
+ sysreg_bit_set CORTEX_X1_CPUECTLR_EL1, BIT(53)
+workaround_reset_end cortex_x1, ERRATUM(1827429)
- /* -------------------------------------------------
- * The CPU Ops reset function for Cortex-X1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func cortex_x1_reset_func
- mov x19, x30
- bl cpu_get_rev_var
- mov x18, x0
+check_erratum_ls cortex_x1, ERRATUM(1827429), CPU_REV(1, 0)
-#if ERRATA_X1_1821534
- mov x0, x18
- bl errata_x1_1821534_wa
-#endif
+check_erratum_chosen cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_X1_1688305
- mov x0, x18
- bl errata_x1_1688305_wa
-#endif
-
-#if ERRATA_X1_1827429
- mov x0, x18
- bl errata_x1_1827429_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_x1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex-X1 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_x1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_x1
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x1, CVE(2022, 23960)
- isb
- ret x19
-endfunc cortex_x1_reset_func
+cpu_reset_func_start cortex_x1
+cpu_reset_func_end cortex_x1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
* ---------------------------------------------
*/
func cortex_x1_core_pwr_dwn
- /* ---------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------
- */
- mrs x0, CORTEX_X1_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X1_CORE_PWRDN_EN_MASK
- msr CORTEX_X1_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X1_CPUPWRCTLR_EL1, CORTEX_X1_CORE_PWRDN_EN_MASK
isb
ret
endfunc cortex_x1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex X1. Must follow AAPCS.
- */
-func cortex_x1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X1_1821534, cortex_x1, 1821534
- report_errata ERRATA_X1_1688305, cortex_x1, 1688305
- report_errata ERRATA_X1_1827429, cortex_x1, 1827429
- report_errata WORKAROUND_CVE_2022_23960, cortex_x1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x1_errata_report
-#endif
+errata_report_shim cortex_x1
/* ---------------------------------------------
* This function provides Cortex X1 specific
diff --git a/lib/cpus/aarch64/cortex_x2.S b/lib/cpus/aarch64/cortex_x2.S
index 497bd52..816a58f 100644
--- a/lib/cpus/aarch64/cortex_x2.S
+++ b/lib/cpus/aarch64/cortex_x2.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X2_BHB_LOOP_COUNT, cortex_x2
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2002765.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2002765_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2002765
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2002765), ERRATA_X2_2002765
ldr x0, =0x6
msr S3_6_C15_C8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0xF3A08002
@@ -48,119 +35,24 @@
msr S3_6_C15_C8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x40000001003ff
msr S3_6_C15_C8_1, x0 /* CPUPCR_EL3 */
- isb
-
-1:
- ret x17
-endfunc errata_cortex_x2_2002765_wa
-
-func check_errata_2002765
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2002765
+workaround_reset_end cortex_x2, ERRATUM(2002765)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2058056.
- * This applies to revisions r0p0, r1p0, and r2p0 and
- * is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2058056_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2058056
- cbz x0, 1f
-
- mrs x1, CORTEX_X2_CPUECTLR2_EL1
- mov x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, #CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
- msr CORTEX_X2_CPUECTLR2_EL1, x1
+check_erratum_ls cortex_x2, ERRATUM(2002765), CPU_REV(2, 0)
-1:
- ret x17
-endfunc errata_cortex_x2_2058056_wa
+workaround_reset_start cortex_x2, ERRATUM(2017096), ERRATA_X2_2017096
+ sysreg_bit_set CORTEX_X2_CPUECTLR_EL1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end cortex_x2, ERRATUM(2017096)
-func check_errata_2058056
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2058056
+check_erratum_ls cortex_x2, ERRATUM(2017096), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata #2083908.
- * This applies to revision r2p0 and is open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x2, x17
- * --------------------------------------------------
- */
-func errata_cortex_x2_2083908_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2083908
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2058056), ERRATA_X2_2058056
+ sysreg_bitfield_insert CORTEX_X2_CPUECTLR2_EL1, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_CNSRV, \
+ CORTEX_X2_CPUECTLR2_EL1_PF_MODE_SHIFT, CORTEX_X2_CPUECTLR2_EL1_PF_MODE_WIDTH
+workaround_reset_end cortex_x2, ERRATUM(2058056)
- /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, #BIT(13)
- msr CORTEX_X2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_cortex_x2_2083908_wa
+check_erratum_ls cortex_x2, ERRATUM(2058056), CPU_REV(2, 0)
-func check_errata_2083908
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2083908
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2017096.
- * This applies only to revisions r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2017096_wa
- /* Compare x0 against revision r0p0 to r2p0 */
- mov x17, x30
- bl check_errata_2017096
- cbz x0, 1f
- mrs x1, CORTEX_X2_CPUECTLR_EL1
- orr x1, x1, CORTEX_X2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr CORTEX_X2_CPUECTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2017096_wa
-
-func check_errata_2017096
- /* Applies to r0p0, r1p0, r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2017096
-
- /* --------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2081180.
- * This applies to revision r0p0, r1p0 and r2p0
- * and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2081180_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2081180
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2081180), ERRATA_X2_2081180
/* Apply instruction patching sequence */
ldr x0, =0x3
msr CORTEX_X2_IMP_CPUPSELR_EL3, x0
@@ -178,34 +70,26 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x10002001003F3
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_x2_2081180_wa
+workaround_reset_end cortex_x2, ERRATUM(2081180)
-func check_errata_2081180
- /* Applies to r0p0, r1p0 and r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2081180
+check_erratum_ls cortex_x2, ERRATUM(2081180), CPU_REV(2, 0)
- /* --------------------------------------------------
- * Errata Workaround for Cortex X2 Errata 2216384.
- * This applies to revisions r0p0, r1p0, and r2p0
- * and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * --------------------------------------------------
- */
-func errata_x2_2216384_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216384
- cbz x0, 1f
+workaround_reset_start cortex_x2, ERRATUM(2083908), ERRATA_X2_2083908
+ /* Apply the workaround by setting bit 13 in CPUACTLR5_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, BIT(13)
+workaround_reset_end cortex_x2, ERRATUM(2083908)
+
+check_erratum_range cortex_x2, ERRATUM(2083908), CPU_REV(2, 0), CPU_REV(2, 0)
+
+workaround_reset_start cortex_x2, ERRATUM(2147715), ERRATA_X2_2147715
+ /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
+ sysreg_bit_set CORTEX_X2_CPUACTLR_EL1, CORTEX_X2_CPUACTLR_EL1_BIT_22
+workaround_reset_end cortex_x2, ERRATUM(2147715)
+
+check_erratum_range cortex_x2, ERRATUM(2147715), CPU_REV(2, 0), CPU_REV(2, 0)
- mrs x1, CORTEX_X2_CPUACTLR5_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
- msr CORTEX_X2_CPUACTLR5_EL1, x1
+workaround_reset_start cortex_x2, ERRATUM(2216384), ERRATA_X2_2216384
+ sysreg_bit_set CORTEX_X2_CPUACTLR5_EL1, CORTEX_X2_CPUACTLR5_EL1_BIT_17
/* Apply instruction patching sequence */
ldr x0, =0x5
@@ -216,138 +100,52 @@
msr CORTEX_X2_IMP_CPUPMR_EL3, x0
ldr x0, =0x80000000003FF
msr CORTEX_X2_IMP_CPUPCR_EL3, x0
- isb
-
-1:
- ret x17
-endfunc errata_x2_2216384_wa
+workaround_reset_end cortex_x2, ERRATUM(2216384)
-func check_errata_2216384
- /* Applies to r0p0 - r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2216384
+check_erratum_ls cortex_x2, ERRATUM(2216384), CPU_REV(2, 0)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
- /* ---------------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata 2147715.
- * This applies only to revisions r2p0 and is fixed in r2p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------
- */
-func errata_x2_2147715_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_2147715
- cbz x0, 1f
-
- /* Apply the workaround by setting bit 22 in CPUACTLR_EL1. */
- mrs x1, CORTEX_X2_CPUACTLR_EL1
- orr x1, x1, CORTEX_X2_CPUACTLR_EL1_BIT_22
- msr CORTEX_X2_CPUACTLR_EL1, x1
-
-1:
- ret x17
-endfunc errata_x2_2147715_wa
-
-func check_errata_2147715
- /* Applies to r2p0 */
- mov x1, #0x20
- mov x2, #0x20
- b cpu_rev_var_range
-endfunc check_errata_2147715
-
- /* ---------------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2282622.
- * This applies to revision r0p0, r1p0, r2p0 and r2p1.
- * It is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x1, x17
- * ---------------------------------------------------------------
- */
-func errata_x2_2282622_wa
- /* Compare x0 against revision r2p1 */
- mov x17, x30
- bl check_errata_2282622
- cbz x0, 1f
-
+workaround_reset_start cortex_x2, ERRATUM(2282622), ERRATA_X2_2282622
/* Apply the workaround */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #BIT(0)
- msr CORTEX_X2_CPUACTLR2_EL1, x1
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, BIT(0)
+workaround_reset_end cortex_x2, ERRATUM(2282622)
-1:
- ret x17
-endfunc errata_x2_2282622_wa
+check_erratum_ls cortex_x2, ERRATUM(2282622), CPU_REV(2, 1)
-func check_errata_2282622
- /* Applies to r0p0, r1p0, r2p0 and r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2282622
+workaround_reset_start cortex_x2, ERRATUM(2371105), ERRATA_X2_2371105
+ /* Set bit 40 in CPUACTLR2_EL1 */
+ sysreg_bit_set CORTEX_X2_CPUACTLR2_EL1, CORTEX_X2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end cortex_x2, ERRATUM(2371105)
- /* -------------------------------------------------------
- * Errata Workaround for Cortex-X2 Erratum 2371105.
- * This applies to revisions <= r2p0 and is fixed in r2p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_x2_2371105_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2371105
- cbz x0, 1f
+check_erratum_ls cortex_x2, ERRATUM(2371105), CPU_REV(2, 0)
- /* Set bit 40 in CPUACTLR2_EL1 */
- mrs x1, CORTEX_X2_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X2_CPUACTLR2_EL1_BIT_40
- msr CORTEX_X2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_x2_2371105_wa
+workaround_reset_start cortex_x2, ERRATUM(2768515), ERRATA_X2_2768515
+ /* dsb before isb of power down sequence */
+ dsb sy
+workaround_reset_end cortex_x2, ERRATUM(2768515)
-func check_errata_2371105
- /* Applies to <= r2p0. */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_2371105
+check_erratum_ls cortex_x2, ERRATUM(2768515), CPU_REV(2, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Cortex-X2 Errata #2768515
- * This applies to revisions <= r2p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
+workaround_reset_start cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Cortex-X2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_x2_2768515_wa
- mov x17, x30
- bl check_errata_2768515
- cbz x0, 1f
+ override_vector_table wa_cve_vbar_cortex_x2
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x2, CVE(2022, 23960)
- /* dsb before isb of power down sequence */
- dsb sy
-1:
- ret x17
-endfunc errata_x2_2768515_wa
+check_erratum_chosen cortex_x2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-func check_errata_2768515
- /* Applies to all revisions <= r2p1 */
- mov x1, #0x21
- b cpu_rev_var_ls
-endfunc check_errata_2768515
+/*
+ * ERRATA_DSU_2313941 :
+ * The errata is defined in dsu_helpers.S but applies to cortex_x2
+ * as well. Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_cortex_x2_2313941, check_errata_dsu_2313941
+.equ erratum_cortex_x2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry cortex_x2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -358,122 +156,24 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X2_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X2_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X2_CPUPWRCTLR_EL1, CORTEX_X2_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+
#if ERRATA_X2_2768515
mov x15, x30
bl cpu_get_rev_var
- bl errata_x2_2768515_wa
+ bl erratum_cortex_x2_2768515_wa
mov x30, x15
#endif /* ERRATA_X2_2768515 */
isb
ret
endfunc cortex_x2_core_pwr_dwn
- /*
- * Errata printing function for Cortex X2. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func cortex_x2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X2_2002765, cortex_x2, 2002765
- report_errata ERRATA_X2_2017096, cortex_x2, 2017096
- report_errata ERRATA_X2_2058056, cortex_x2, 2058056
- report_errata ERRATA_X2_2081180, cortex_x2, 2081180
- report_errata ERRATA_X2_2083908, cortex_x2, 2083908
- report_errata ERRATA_X2_2147715, cortex_x2, 2147715
- report_errata ERRATA_X2_2216384, cortex_x2, 2216384
- report_errata ERRATA_X2_2282622, cortex_x2, 2282622
- report_errata ERRATA_X2_2371105, cortex_x2, 2371105
- report_errata ERRATA_X2_2768515, cortex_x2, 2768515
- report_errata WORKAROUND_CVE_2022_23960, cortex_x2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, cortex_x2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x2_errata_report
-#endif
-
-func cortex_x2_reset_func
- mov x19, x30
+errata_report_shim cortex_x2
+cpu_reset_func_start cortex_x2
/* Disable speculative loads */
msr SSBS, xzr
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_X2_2002765
- mov x0, x18
- bl errata_cortex_x2_2002765_wa
-#endif
-
-#if ERRATA_X2_2058056
- mov x0, x18
- bl errata_cortex_x2_2058056_wa
-#endif
-
-#if ERRATA_X2_2083908
- mov x0, x18
- bl errata_cortex_x2_2083908_wa
-#endif
-
-#if ERRATA_X2_2017096
- mov x0, x18
- bl errata_x2_2017096_wa
-#endif
-
-#if ERRATA_X2_2081180
- mov x0, x18
- bl errata_x2_2081180_wa
-#endif
-
-#if ERRATA_X2_2216384
- mov x0, x18
- bl errata_x2_2216384_wa
-#endif
-
-#if ERRATA_X2_2147715
- mov x0, x18
- bl errata_x2_2147715_wa
-#endif
-
-#if ERRATA_X2_2282622
- mov x0, x18
- bl errata_x2_2282622_wa
-#endif
-
-#if ERRATA_X2_2371105
- mov x0, x18
- bl errata_x2_2371105_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc cortex_x2_reset_func
+cpu_reset_func_end cortex_x2
/* ---------------------------------------------
* This function provides Cortex X2 specific
diff --git a/lib/cpus/aarch64/cortex_x3.S b/lib/cpus/aarch64/cortex_x3.S
index f104b48..c781d38 100644
--- a/lib/cpus/aarch64/cortex_x3.S
+++ b/lib/cpus/aarch64/cortex_x3.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -26,141 +26,51 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X3_BHB_LOOP_COUNT, cortex_x3
#endif /* WORKAROUND_CVE_2022_23960 */
- /* ----------------------------------------------------
- * HW will do the cache maintenance while powering down
- * ----------------------------------------------------
- */
-func cortex_x3_core_pwr_dwn
-#if ERRATA_X3_2313909
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_cortex_x3_2313909_wa
- mov x30, x15
-#endif /* ERRATA_X3_2313909 */
+workaround_runtime_start cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ sysreg_bit_set CORTEX_X3_CPUACTLR2_EL1, CORTEX_X3_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end cortex_x3, ERRATUM(2313909), NO_ISB
- /* ---------------------------------------------------
- * Enable CPU power down bit in power control register
- * ---------------------------------------------------
- */
- mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X3_CPUPWRCTLR_EL1, x0
- isb
- ret
-endfunc cortex_x3_core_pwr_dwn
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x3_reset_func
- mov x19, x30
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Cortex-X3 generic vectors are overridden to apply
- * errata mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_cortex_x3
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+check_erratum_ls cortex_x3, ERRATUM(2313909), CPU_REV(1, 0)
- bl cpu_get_rev_var
-
-#if ERRATA_X3_2615812
- bl errata_cortex_x3_2615812_wa
-#endif /* ERRATA_X3_2615812 */
-
- isb
- ret x19
-endfunc cortex_x3_reset_func
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2313909 on power down request.
- * This applies to revision r0p0 and r1p0 of Cortex-X3. Fixed in r1p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2313909_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2313909
- cbz x0, 1f
-
- /* Set bit 36 in ACTLR2_EL1 */
- mrs x1, CORTEX_X3_CPUACTLR2_EL1
- orr x1, x1, #CORTEX_X3_CPUACTLR2_EL1_BIT_36
- msr CORTEX_X3_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_cortex_x3_2313909_wa
-
-func check_errata_2313909
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_2313909
-
-/* ----------------------------------------------------------------------
- * Errata Workaround for Cortex-X3 Erratum 2615812 on power-on.
- * This applies to revision r0p0, r1p0, r1p1 of Cortex-X3. Open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------------------------
- */
-func errata_cortex_x3_2615812_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2615812
- cbz x0, 1f
-
+workaround_reset_start cortex_x3, ERRATUM(2615812), ERRATA_X3_2615812
/* Disable retention control for WFI and WFE. */
mrs x0, CORTEX_X3_CPUPWRCTLR_EL1
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFI_RET_CTRL_BITS_SHIFT, #3
bfi x0, xzr, #CORTEX_X3_CPUPWRCTLR_EL1_WFE_RET_CTRL_BITS_SHIFT, #3
msr CORTEX_X3_CPUPWRCTLR_EL1, x0
-1:
- ret x17
-endfunc errata_cortex_x3_2615812_wa
+workaround_reset_end cortex_x3, ERRATUM(2615812)
-func check_errata_2615812
- /* Applies to r1p1 and below. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2615812
+check_erratum_ls cortex_x3, ERRATUM(2615812), CPU_REV(1, 1)
-#if REPORT_ERRATA
- /*
- * Errata printing function for Cortex-X3. Must follow AAPCS.
- */
-func cortex_x3_errata_report
- stp x8, x30, [sp, #-16]!
+workaround_reset_start cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ override_vector_table wa_cve_vbar_cortex_x3
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x3, CVE(2022, 23960)
- bl cpu_get_rev_var
- mov x8, x0
+check_erratum_chosen cortex_x3, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_X3_2313909, cortex_x3, 2313909
- report_errata ERRATA_X3_2615812, cortex_x3, 2615812
- report_errata WORKAROUND_CVE_2022_23960, cortex_x3, cve_2022_23960
+cpu_reset_func_start cortex_x3
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_x3
- ldp x8, x30, [sp], #16
+ /* ----------------------------------------------------
+ * HW will do the cache maintenance while powering down
+ * ----------------------------------------------------
+ */
+func cortex_x3_core_pwr_dwn
+apply_erratum cortex_x3, ERRATUM(2313909), ERRATA_X3_2313909
+ /* ---------------------------------------------------
+ * Enable CPU power down bit in power control register
+ * ---------------------------------------------------
+ */
+ sysreg_bit_set CORTEX_X3_CPUPWRCTLR_EL1, CORTEX_X3_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ isb
ret
-endfunc cortex_x3_errata_report
-#endif
+endfunc cortex_x3_core_pwr_dwn
+
+errata_report_shim cortex_x3
/* ---------------------------------------------
* This function provides Cortex-X3-
diff --git a/lib/cpus/aarch64/cortex_x4.S b/lib/cpus/aarch64/cortex_x4.S
index db87008..7619f9c 100644
--- a/lib/cpus/aarch64/cortex_x4.S
+++ b/lib/cpus/aarch64/cortex_x4.S
@@ -26,31 +26,22 @@
wa_cve_2022_23960_bhb_vector_table CORTEX_X4_BHB_LOOP_COUNT, cortex_x4
#endif /* WORKAROUND_CVE_2022_23960 */
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func cortex_x4_reset_func
- /* Disable speculative loads */
- msr SSBS, xzr
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
+workaround_reset_start cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
/*
* The Cortex X4 generic vectors are overridden to apply errata
* mitigation on exception entry from lower ELs.
*/
- adr x0, wa_cve_vbar_cortex_x4
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
+ override_vector_table wa_cve_vbar_cortex_x4
+#endif /* IMAGE_BL31 */
+workaround_reset_end cortex_x4, CVE(2022, 23960)
- isb
- ret
-endfunc cortex_x4_reset_func
+check_erratum_chosen cortex_x4, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+
+cpu_reset_func_start cortex_x4
+ /* Disable speculative loads */
+ msr SSBS, xzr
+cpu_reset_func_end cortex_x4
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
@@ -61,33 +52,12 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------------
*/
- mrs x0, CORTEX_X4_CPUPWRCTLR_EL1
- orr x0, x0, #CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr CORTEX_X4_CPUPWRCTLR_EL1, x0
+ sysreg_bit_set CORTEX_X4_CPUPWRCTLR_EL1, CORTEX_X4_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
isb
ret
endfunc cortex_x4_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Cortex X4. Must follow AAPCS.
- */
-func cortex_x4_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2022_23960, cortex_x4, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc cortex_x4_errata_report
-#endif
+errata_report_shim cortex_x4
/* ---------------------------------------------
* This function provides Cortex X4-specific
diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S
index 3c54a6f..884281d 100644
--- a/lib/cpus/aarch64/denver.S
+++ b/lib/cpus/aarch64/denver.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2023, Arm Limited and Contributors. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -207,7 +207,14 @@
2: ret
endfunc denver_disable_dco
-func check_errata_cve_2017_5715
+workaround_reset_start denver, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
+#if IMAGE_BL31
+ adr x1, workaround_bpflush_runtime_exceptions
+ msr vbar_el3, x1
+#endif
+workaround_reset_end denver, CVE(2017, 5715)
+
+check_erratum_custom_start denver, CVE(2017, 5715)
mov x0, #ERRATA_MISSING
#if WORKAROUND_CVE_2017_5715
/*
@@ -224,43 +231,9 @@
1:
#endif
ret
-endfunc check_errata_cve_2017_5715
-
-func check_errata_cve_2018_3639
-#if WORKAROUND_CVE_2018_3639
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2018_3639
-
- /* -------------------------------------------------
- * The CPU Ops reset function for Denver.
- * -------------------------------------------------
- */
-func denver_reset_func
-
- mov x19, x30
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
- /*
- * Check if the CPU supports the special instruction
- * required to flush the indirect branch predictor and
- * RSB. Support for this operation can be determined by
- * comparing bits 19:16 of ID_AFR0_EL1 with 0b0001.
- */
- mrs x0, id_afr0_el1
- mov x1, #0x10000
- and x0, x0, x1
- cmp x0, #0
- adr x1, workaround_bpflush_runtime_exceptions
- mrs x2, vbar_el3
- csel x0, x1, x2, ne
- msr vbar_el3, x0
-#endif
+check_erratum_custom_end denver, CVE(2017, 5715)
-#if WORKAROUND_CVE_2018_3639
+workaround_reset_start denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
/*
* Denver CPUs with DENVER_MIDR_PN3 or earlier, use different
* bits in the ACTLR_EL3 register to disable speculative
@@ -277,8 +250,11 @@
msr actlr_el3, x0
isb
dsb sy
-#endif
+workaround_reset_end denver, CVE(2018, 3639)
+
+check_erratum_chosen denver, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
+cpu_reset_func_start denver
/* ----------------------------------------------------
* Reset ACTLR.PMSTATE to C1 state
* ----------------------------------------------------
@@ -293,9 +269,7 @@
* ----------------------------------------------------
*/
bl denver_enable_dco
-
- ret x19
-endfunc denver_reset_func
+cpu_reset_func_end denver
/* ----------------------------------------------------
* The CPU Ops core power down function for Denver.
@@ -322,27 +296,7 @@
ret
endfunc denver_cluster_pwr_dwn
-#if REPORT_ERRATA
- /*
- * Errata printing function for Denver. Must follow AAPCS.
- */
-func denver_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata WORKAROUND_CVE_2017_5715, denver, cve_2017_5715
- report_errata WORKAROUND_CVE_2018_3639, denver, cve_2018_3639
-
- ldp x8, x30, [sp], #16
- ret
-endfunc denver_errata_report
-#endif
+errata_report_shim denver
/* ---------------------------------------------
* This function provides Denver specific
@@ -367,7 +321,7 @@
.macro denver_cpu_ops_wa midr
declare_cpu_ops_wa denver, \midr, \
denver_reset_func, \
- check_errata_cve_2017_5715, \
+ check_erratum_denver_5715, \
CPU_NO_EXTRA2_FUNC, \
CPU_NO_EXTRA3_FUNC, \
denver_core_pwr_dwn, \
diff --git a/lib/cpus/aarch64/neoverse_e1.S b/lib/cpus/aarch64/neoverse_e1.S
index 96b63cf..45bd8d3 100644
--- a/lib/cpus/aarch64/neoverse_e1.S
+++ b/lib/cpus/aarch64/neoverse_e1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -21,20 +21,18 @@
#error "Neoverse-E1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif
- /* -------------------------------------------------
- * The CPU Ops reset function for Neoverse-E1.
- * Shall clobber: x0-x19
- * -------------------------------------------------
- */
-func neoverse_e1_reset_func
- mov x19, x30
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
-#endif
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to neoverse_e1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
+ */
+.equ check_erratum_neoverse_e1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_e1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_e1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
- ret x19
-endfunc neoverse_e1_reset_func
+cpu_reset_func_start neoverse_e1
+cpu_reset_func_end neoverse_e1
func neoverse_e1_cpu_pwr_dwn
mrs x0, NEOVERSE_E1_CPUPWRCTLR_EL1
@@ -44,27 +42,7 @@
ret
endfunc neoverse_e1_cpu_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_e1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_DSU_936184, neoverse_e1, dsu_936184
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_e1_errata_report
-#endif
-
+errata_report_shim neoverse_e1
.section .rodata.neoverse_e1_regs, "aS"
neoverse_e1_regs: /* The ascii list of register names to be reported */
diff --git a/lib/cpus/aarch64/neoverse_n1.S b/lib/cpus/aarch64/neoverse_n1.S
index 2cf94c7..36a7ee7 100644
--- a/lib/cpus/aarch64/neoverse_n1.S
+++ b/lib/cpus/aarch64/neoverse_n1.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -27,20 +27,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N1_BHB_LOOP_COUNT, neoverse_n1
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1043202.
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_936184:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N1.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n1_1043202_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1043202
- cbz x0, 1f
+.equ check_erratum_neoverse_n1_936184, check_errata_dsu_936184
+.equ erratum_neoverse_n1_936184_wa, errata_dsu_936184_wa
+add_erratum_entry neoverse_n1, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET
+workaround_reset_start neoverse_n1, ERRATUM(1043202), ERRATA_N1_1043202
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -50,314 +47,72 @@
msr CPUPMR_EL3, x0
ldr x0, =0x800200071
msr CPUPCR_EL3, x0
- isb
-1:
- ret x17
-endfunc errata_n1_1043202_wa
+workaround_reset_end neoverse_n1, ERRATUM(1043202)
-func check_errata_1043202
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1043202
+check_erratum_ls neoverse_n1, ERRATUM(1043202), CPU_REV(1, 0)
-/* --------------------------------------------------
- * Disable speculative loads if Neoverse N1 supports
- * SSBS.
- *
- * Shall clobber: x0.
- * --------------------------------------------------
- */
-func neoverse_n1_disable_speculative_loads
- /* Check if the PE implements SSBS */
- mrs x0, id_aa64pfr1_el1
- tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
- b.eq 1f
+workaround_reset_start neoverse_n1, ERRATUM(1073348), ERRATA_N1_1073348
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
+workaround_reset_end neoverse_n1, ERRATUM(1073348)
- /* Disable speculative loads */
- msr SSBS, xzr
+check_erratum_ls neoverse_n1, ERRATUM(1073348), CPU_REV(1, 0)
-1:
- ret
-endfunc neoverse_n1_disable_speculative_loads
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1073348
- * This applies to revision r0p0 and r1p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1073348_wa
- /* Compare x0 against revision r1p0 */
- mov x17, x30
- bl check_errata_1073348
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_6
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1073348_wa
-
-func check_errata_1073348
- /* Applies to r0p0 and r1p0 */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1073348
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1130799
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1130799_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1130799
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1130799_wa
-
-func check_errata_1130799
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1130799
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1165347
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1165347_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1165347
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1165347_wa
+workaround_reset_start neoverse_n1, ERRATUM(1130799), ERRATA_N1_1130799
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_59
+workaround_reset_end neoverse_n1, ERRATUM(1130799)
-func check_errata_1165347
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1165347
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1207823
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1207823_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1207823
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
- msr NEOVERSE_N1_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1207823_wa
+check_erratum_ls neoverse_n1, ERRATUM(1130799), CPU_REV(2, 0)
-func check_errata_1207823
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1207823
+workaround_reset_start neoverse_n1, ERRATUM(1165347), ERRATA_N1_1165347
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_0
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_15
+workaround_reset_end neoverse_n1, ERRATUM(1165347)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1220197
- * This applies to revision <=r2p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1220197_wa
- /* Compare x0 against revision r2p0 */
- mov x17, x30
- bl check_errata_1220197
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_WS_THR_L2_MASK
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1220197_wa
+check_erratum_ls neoverse_n1, ERRATUM(1165347), CPU_REV(2, 0)
-func check_errata_1220197
- /* Applies to <=r2p0 */
- mov x1, #0x20
- b cpu_rev_var_ls
-endfunc check_errata_1220197
+workaround_reset_start neoverse_n1, ERRATUM(1207823), ERRATA_N1_1207823
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_11
+workaround_reset_end neoverse_n1, ERRATUM(1207823)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1257314
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1257314_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1257314
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR3_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
- msr NEOVERSE_N1_CPUACTLR3_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1257314_wa
+check_erratum_ls neoverse_n1, ERRATUM(1207823), CPU_REV(2, 0)
-func check_errata_1257314
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1257314
+workaround_reset_start neoverse_n1, ERRATUM(1220197), ERRATA_N1_1220197
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_WS_THR_L2_MASK
+workaround_reset_end neoverse_n1, ERRATUM(1220197)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262606
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262606_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262606
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262606_wa
+check_erratum_ls neoverse_n1, ERRATUM(1220197), CPU_REV(2, 0)
-func check_errata_1262606
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262606
+workaround_reset_start neoverse_n1, ERRATUM(1257314), ERRATA_N1_1257314
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR3_EL1, NEOVERSE_N1_CPUACTLR3_EL1_BIT_10
+workaround_reset_end neoverse_n1, ERRATUM(1257314)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1262888
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1262888_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1262888
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1262888_wa
+check_erratum_ls neoverse_n1, ERRATUM(1257314), CPU_REV(3, 0)
-func check_errata_1262888
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1262888
+workaround_reset_start neoverse_n1, ERRATUM(1262606), ERRATA_N1_1262606
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1262606)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1275112
- * This applies to revision <=r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1275112_wa
- /* Compare x0 against revision r3p0 */
- mov x17, x30
- bl check_errata_1275112
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n1_1275112_wa
+check_erratum_ls neoverse_n1, ERRATUM(1262606), CPU_REV(3, 0)
-func check_errata_1275112
- /* Applies to <=r3p0 */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1275112
+workaround_reset_start neoverse_n1, ERRATUM(1262888), ERRATA_N1_1262888
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_MM_TLBPF_DIS_BIT
+workaround_reset_end neoverse_n1, ERRATUM(1262888)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1315703.
- * This applies to revision <= r3p0 of Neoverse N1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1315703_wa
- /* Compare x0 against revision r3p1 */
- mov x17, x30
- bl check_errata_1315703
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1262888), CPU_REV(3, 0)
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
+workaround_reset_start neoverse_n1, ERRATUM(1275112), ERRATA_N1_1275112
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1275112)
-1:
- ret x17
-endfunc errata_n1_1315703_wa
+check_erratum_ls neoverse_n1, ERRATUM(1275112), CPU_REV(3, 0)
-func check_errata_1315703
- /* Applies to everything <= r3p0. */
- mov x1, #0x30
- b cpu_rev_var_ls
-endfunc check_errata_1315703
+workaround_reset_start neoverse_n1, ERRATUM(1315703), ERRATA_N1_1315703
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_16
+workaround_reset_end neoverse_n1, ERRATUM(1315703)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Erratum 1542419.
- * This applies to revisions r3p0 - r4p0 of Neoverse N1
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1542419_wa
- /* Compare x0 against revision r3p0 and r4p0 */
- mov x17, x30
- bl check_errata_1542419
- cbz x0, 1f
+check_erratum_ls neoverse_n1, ERRATUM(1315703), CPU_REV(3, 0)
+workaround_reset_start neoverse_n1, ERRATUM(1542419), ERRATA_N1_1542419
/* Apply instruction patching sequence */
ldr x0, =0x0
msr CPUPSELR_EL3, x0
@@ -368,67 +123,17 @@
ldr x0, =0x08000020007D
msr CPUPCR_EL3, x0
isb
-1:
- ret x17
-endfunc errata_n1_1542419_wa
+workaround_reset_end neoverse_n1, ERRATUM(1542419)
-func check_errata_1542419
- /* Applies to everything r3p0 - r4p0. */
- mov x1, #0x30
- mov x2, #0x40
- b cpu_rev_var_range
-endfunc check_errata_1542419
+check_erratum_range neoverse_n1, ERRATUM(1542419), CPU_REV(3, 0), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1868343.
- * This applies to revision <= r4p0 of Neoverse N1.
- * This workaround is the same as the workaround for
- * errata 1262606 and 1275112 but applies to a wider
- * revision range.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1868343_wa
- /*
- * Compare x0 against revision r4p0
- */
- mov x17, x30
- bl check_errata_1868343
- cbz x0, 1f
- mrs x1, NEOVERSE_N1_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
- msr NEOVERSE_N1_CPUACTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n1_1868343_wa
+workaround_reset_start neoverse_n1, ERRATUM(1868343), ERRATA_N1_1868343
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR_EL1, NEOVERSE_N1_CPUACTLR_EL1_BIT_13
+workaround_reset_end neoverse_n1, ERRATUM(1868343)
-func check_errata_1868343
- /* Applies to everything <= r4p0 */
- mov x1, #0x40
- b cpu_rev_var_ls
-endfunc check_errata_1868343
+check_erratum_ls neoverse_n1, ERRATUM(1868343), CPU_REV(4, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #1946160.
- * This applies to revisions r3p0, r3p1, r4p0, and
- * r4p1 of Neoverse N1. It also exists in r0p0, r1p0,
- * and r2p0 but there is no fix in these revisions.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n1_1946160_wa
- /*
- * Compare x0 against r3p0 - r4p1
- */
- mov x17, x30
- bl check_errata_1946160
- cbz x0, 1f
-
+workaround_reset_start neoverse_n1, ERRATUM(1946160), ERRATA_N1_1946160
mov x0, #3
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -437,7 +142,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #4
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800082
@@ -446,7 +150,6 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
mov x0, #5
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3800200
@@ -455,147 +158,62 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
-
isb
-1:
- ret x17
-endfunc errata_n1_1946160_wa
+workaround_reset_end neoverse_n1, ERRATUM(1946160)
-func check_errata_1946160
- /* Applies to r3p0 - r4p1. */
- mov x1, #0x30
- mov x2, #0x41
- b cpu_rev_var_range
-endfunc check_errata_1946160
+check_erratum_range neoverse_n1, ERRATUM(1946160), CPU_REV(3, 0), CPU_REV(4, 1)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse N1 Errata #2743102
- * This applies to revisions <= r4p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_n1_2743102_wa
- mov x17, x30
- bl check_errata_2743102
- cbz x0, 1f
-
+workaround_runtime_start neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n1_2743102_wa
+workaround_runtime_end neoverse_n1, ERRATUM(2743102)
-func check_errata_2743102
- /* Applies to all revisions <= r4p1 */
- mov x1, #0x41
- b cpu_rev_var_ls
-endfunc check_errata_2743102
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
-
-func neoverse_n1_reset_func
- mov x19, x30
+check_erratum_ls neoverse_n1, ERRATUM(2743102), CPU_REV(4, 1)
- bl neoverse_n1_disable_speculative_loads
-
- /* Forces all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N1_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N1_CPUACTLR2_EL1, x0
- isb
-
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_N1_1043202
- mov x0, x18
- bl errata_n1_1043202_wa
-#endif
-
-#if ERRATA_N1_1073348
- mov x0, x18
- bl errata_n1_1073348_wa
-#endif
-
-#if ERRATA_N1_1130799
- mov x0, x18
- bl errata_n1_1130799_wa
-#endif
-
-#if ERRATA_N1_1165347
- mov x0, x18
- bl errata_n1_1165347_wa
-#endif
-
-#if ERRATA_N1_1207823
- mov x0, x18
- bl errata_n1_1207823_wa
-#endif
-
-#if ERRATA_N1_1220197
- mov x0, x18
- bl errata_n1_1220197_wa
-#endif
-
-#if ERRATA_N1_1257314
- mov x0, x18
- bl errata_n1_1257314_wa
-#endif
-
-#if ERRATA_N1_1262606
- mov x0, x18
- bl errata_n1_1262606_wa
-#endif
+workaround_reset_start neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n1, CVE(2022, 23960)
-#if ERRATA_N1_1262888
- mov x0, x18
- bl errata_n1_1262888_wa
-#endif
+check_erratum_chosen neoverse_n1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
-#if ERRATA_N1_1275112
- mov x0, x18
- bl errata_n1_1275112_wa
-#endif
+/* --------------------------------------------------
+ * Disable speculative loads if Neoverse N1 supports
+ * SSBS.
+ *
+ * Shall clobber: x0.
+ * --------------------------------------------------
+ */
+func neoverse_n1_disable_speculative_loads
+ /* Check if the PE implements SSBS */
+ mrs x0, id_aa64pfr1_el1
+ tst x0, #(ID_AA64PFR1_EL1_SSBS_MASK << ID_AA64PFR1_EL1_SSBS_SHIFT)
+ b.eq 1f
-#if ERRATA_N1_1315703
- mov x0, x18
- bl errata_n1_1315703_wa
-#endif
+ /* Disable speculative loads */
+ msr SSBS, xzr
-#if ERRATA_N1_1542419
- mov x0, x18
- bl errata_n1_1542419_wa
-#endif
+1:
+ ret
+endfunc neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1868343
- mov x0, x18
- bl errata_n1_1868343_wa
-#endif
+cpu_reset_func_start neoverse_n1
+ bl neoverse_n1_disable_speculative_loads
-#if ERRATA_N1_1946160
- mov x0, x18
- bl errata_n1_1946160_wa
-#endif
+ /* Forces all cacheable atomic instructions to be near */
+ sysreg_bit_set NEOVERSE_N1_CPUACTLR2_EL1, NEOVERSE_N1_CPUACTLR2_EL1_BIT_2
+ isb
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, actlr_el3
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el3, x0
-
+ sysreg_bit_set actlr_el3, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, actlr_el2
- orr x0, x0, #NEOVERSE_N1_ACTLR_AMEN_BIT
- msr actlr_el2, x0
-
+ sysreg_bit_set actlr_el2, NEOVERSE_N1_ACTLR_AMEN_BIT
/* Enable group0 counters */
mov x0, #NEOVERSE_N1_AMU_GROUP0_MASK
msr CPUAMCNTENSET_EL0, x0
@@ -603,27 +221,9 @@
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some system may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N1_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N1_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_DSU_936184
- bl errata_dsu_936184_wa
+ sysreg_bit_set NEOVERSE_N1_CPUECTLR_EL1, NEOVERSE_N1_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n1_reset_func
+cpu_reset_func_end neoverse_n1
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -634,55 +234,15 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_N1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N1_CORE_PWRDN_EN_MASK
- msr NEOVERSE_N1_CPUPWRCTLR_EL1, x0
-#if ERRATA_N1_2743102
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n1_2743102_wa
- mov x30, x15
-#endif /* ERRATA_N1_2743102 */
+ sysreg_bit_set NEOVERSE_N1_CPUPWRCTLR_EL1, NEOVERSE_N1_CORE_PWRDN_EN_MASK
+
+ apply_erratum neoverse_n1, ERRATUM(2743102), ERRATA_N1_2743102
+
isb
ret
endfunc neoverse_n1_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N1. Must follow AAPCS.
- */
-func neoverse_n1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N1_1043202, neoverse_n1, 1043202
- report_errata ERRATA_N1_1073348, neoverse_n1, 1073348
- report_errata ERRATA_N1_1130799, neoverse_n1, 1130799
- report_errata ERRATA_N1_1165347, neoverse_n1, 1165347
- report_errata ERRATA_N1_1207823, neoverse_n1, 1207823
- report_errata ERRATA_N1_1220197, neoverse_n1, 1220197
- report_errata ERRATA_N1_1257314, neoverse_n1, 1257314
- report_errata ERRATA_N1_1262606, neoverse_n1, 1262606
- report_errata ERRATA_N1_1262888, neoverse_n1, 1262888
- report_errata ERRATA_N1_1275112, neoverse_n1, 1275112
- report_errata ERRATA_N1_1315703, neoverse_n1, 1315703
- report_errata ERRATA_N1_1542419, neoverse_n1, 1542419
- report_errata ERRATA_N1_1868343, neoverse_n1, 1868343
- report_errata ERRATA_N1_1946160, neoverse_n1, 1946160
- report_errata ERRATA_N1_2743102, neoverse_n1, 2743102
- report_errata ERRATA_DSU_936184, neoverse_n1, dsu_936184
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n1_errata_report
-#endif
+errata_report_shim neoverse_n1
/*
* Handle trap of EL0 IC IVAU instructions to EL3 by executing a TLB
diff --git a/lib/cpus/aarch64/neoverse_n2.S b/lib/cpus/aarch64/neoverse_n2.S
index 60d322f..acf8dee 100644
--- a/lib/cpus/aarch64/neoverse_n2.S
+++ b/lib/cpus/aarch64/neoverse_n2.S
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2020-2022, Arm Limited. All rights reserved.
+ * Copyright (c) 2020-2023, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -24,20 +24,17 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_N2_BHB_LOOP_COUNT, neoverse_n2
#endif /* WORKAROUND_CVE_2022_23960 */
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2002655.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
+/*
+ * ERRATA_DSU_2313941:
+ * The errata is defined in dsu_helpers.S and applies to Neoverse N2.
+ * Henceforth creating symbolic names to the already existing errata
+ * workaround functions to get them registered under the Errata Framework.
*/
-func errata_n2_2002655_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2002655
- cbz x0, 1f
+.equ check_erratum_neoverse_n2_2313941, check_errata_dsu_2313941
+.equ erratum_neoverse_n2_2313941_wa, errata_dsu_2313941_wa
+add_erratum_entry neoverse_n2, ERRATUM(2313941), ERRATA_DSU_2313941, APPLY_AT_RESET
+workaround_reset_start neoverse_n2, ERRATUM(2002655), ERRATA_N2_2002655
/* Apply instruction patching sequence */
ldr x0,=0x6
msr S3_6_c15_c8_0,x0
@@ -55,111 +52,33 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x40000001003f3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2002655_wa
-
-func check_errata_2002655
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2002655
+workaround_reset_end neoverse_n2, ERRATUM(2002655)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2067956.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2067956_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2067956
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2067956_wa
+check_erratum_ls neoverse_n2, ERRATUM(2002655), CPU_REV(0, 0)
-func check_errata_2067956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2067956
+workaround_reset_start neoverse_n2, ERRATUM(2025414), ERRATA_N2_2025414
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
+workaround_reset_end neoverse_n2, ERRATUM(2025414)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2025414.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2025414_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2025414
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUECTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUECTLR_EL1_PFSTIDIS_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x1
+check_erratum_ls neoverse_n2, ERRATUM(2025414), CPU_REV(0, 0)
-1:
- ret x17
-endfunc errata_n2_2025414_wa
+workaround_reset_start neoverse_n2, ERRATUM(2067956), ERRATA_N2_2067956
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_46
+workaround_reset_end neoverse_n2, ERRATUM(2067956)
-func check_errata_2025414
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2025414
+check_erratum_ls neoverse_n2, ERRATUM(2067956), CPU_REV(0, 0)
-/* ---------------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2189731.
- * This applies to revision r0p0 of Neoverse N2 and is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ---------------------------------------------------------------
- */
-func errata_n2_2189731_wa
- /* Compare x0 against revision r0p0 */
- mov x17, x30
- bl check_errata_2189731
- cbz x0, 1f
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-
-1:
- ret x17
-endfunc errata_n2_2189731_wa
-
-func check_errata_2189731
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2189731
+workaround_reset_start neoverse_n2, ERRATUM(2138953), ERRATA_N2_2138953
+ /* Apply instruction patching sequence */
+ mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
+ mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_N2_CPUECTLR2_EL1, x1
+workaround_reset_end neoverse_n2, ERRATUM(2138953)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138956.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_n2_2138956_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138956
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2138953), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2138956), ERRATA_N2_2138956
/* Apply instruction patching sequence */
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
@@ -177,120 +96,27 @@
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
- isb
-1:
- ret x17
-endfunc errata_n2_2138956_wa
+workaround_reset_end neoverse_n2, ERRATUM(2138956)
-func check_errata_2138956
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138956
+check_erratum_ls neoverse_n2, ERRATUM(2138956), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242415.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242415_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242415
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2138958), ERRATA_N2_2138958
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2242415_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
+workaround_reset_end neoverse_n2, ERRATUM(2138958)
-func check_errata_2242415
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242415
+check_erratum_ls neoverse_n2, ERRATUM(2138958), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138953.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138953_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138953
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2189731), ERRATA_N2_2189731
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_44
+workaround_reset_end neoverse_n2, ERRATUM(2189731)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUECTLR2_EL1
- mov x0, #NEOVERSE_N2_CPUECTLR2_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR2_EL1_PF_MODE_LSB, #CPUECTLR2_EL1_PF_MODE_WIDTH
- msr NEOVERSE_N2_CPUECTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138953_wa
+check_erratum_ls neoverse_n2, ERRATUM(2189731), CPU_REV(0, 0)
-func check_errata_2138953
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138953
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2138958.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2138958_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2138958
- cbz x0, 1f
-
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_13
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2138958_wa
-
-func check_errata_2138958
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2138958
-
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2242400.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2242400_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2242400
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2242400), ERRATA_N2_2242400
/* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR5_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
- msr NEOVERSE_N2_CPUACTLR5_EL1, x1
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_17
ldr x0, =0x2
msr S3_6_c15_c8_0, x0
ldr x0, =0x10F600E000
@@ -299,174 +125,86 @@
msr S3_6_c15_c8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0
- isb
-1:
- ret x17
-endfunc errata_n2_2242400_wa
+workaround_reset_end neoverse_n2, ERRATUM(2242400)
-func check_errata_2242400
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2242400
+check_erratum_ls neoverse_n2, ERRATUM(2242400), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2280757.
- * This applies to revision r0p0 of Neoverse N2. it is still open.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2280757_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2280757
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2242415), ERRATA_N2_2242415
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2242415)
- /* Apply instruction patching sequence */
- mrs x1, NEOVERSE_N2_CPUACTLR_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
- msr NEOVERSE_N2_CPUACTLR_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2280757_wa
+check_erratum_ls neoverse_n2, ERRATUM(2242415), CPU_REV(0, 0)
-func check_errata_2280757
- /* Applies to r0p0 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2280757
+workaround_reset_start neoverse_n2, ERRATUM(2280757), ERRATA_N2_2280757
+ /* Apply instruction patching sequence */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR_EL1, NEOVERSE_N2_CPUACTLR_EL1_BIT_22
+workaround_reset_end neoverse_n2, ERRATUM(2280757)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2326639.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2326639_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2326639
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2280757), CPU_REV(0, 0)
+workaround_runtime_start neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* Set bit 36 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2326639_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_36
+workaround_runtime_end neoverse_n2, ERRATUM(2326639)
-func check_errata_2326639
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2326639
+check_erratum_ls neoverse_n2, ERRATUM(2326639), CPU_REV(0, 0)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2376738.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current CPU.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2376738_wa
- mov x17, x30
- bl check_errata_2376738
- cbz x0, 1f
-
+workaround_reset_start neoverse_n2, ERRATUM(2376738), ERRATA_N2_2376738
/* Set CPUACTLR2_EL1[0] to 1 to force PLDW/PFRM
* ST to behave like PLD/PFRM LD and not cause
* invalidations to other PE caches.
*/
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
-1:
- ret x17
-endfunc errata_n2_2376738_wa
-
-func check_errata_2376738
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, 0x00
- b cpu_rev_var_ls
-endfunc check_errata_2376738
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_n2, ERRATUM(2376738)
-/* --------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2388450.
- * This applies to revision r0p0 of Neoverse N2,
- * fixed in r0p1.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_n2_2388450_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2388450
- cbz x0, 1f
+check_erratum_ls neoverse_n2, ERRATUM(2376738), CPU_REV(0, 3)
+workaround_reset_start neoverse_n2, ERRATUM(2388450), ERRATA_N2_2388450
/*Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_N2_CPUACTLR2_EL1
- orr x1, x1, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
- msr NEOVERSE_N2_CPUACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_n2_2388450_wa
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_n2, ERRATUM(2388450)
-func check_errata_2388450
- /* Applies to r0p0, fixed in r0p1 */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_2388450
+check_erratum_ls neoverse_n2, ERRATUM(2388450), CPU_REV(0, 0)
-/* -------------------------------------------------------
- * Errata Workaround for Neoverse N2 Erratum 2743089.
- * This applies to revisions <= r0p2 and is fixed in r0p3.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -------------------------------------------------------
- */
-func errata_n2_2743089_wa
- mov x17, x30
- bl check_errata_2743089
- cbz x0, 1f
+workaround_reset_start neoverse_n2, ERRATUM(2743014), ERRATA_N2_2743014
+ /* Set CPUACTLR5_EL1[56:55] to 2'b01 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_55
+ sysreg_bit_clear NEOVERSE_N2_CPUACTLR5_EL1, NEOVERSE_N2_CPUACTLR5_EL1_BIT_56
+workaround_reset_end neoverse_n2, ERRATUM(2743014)
+check_erratum_ls neoverse_n2, ERRATUM(2743014), CPU_REV(0, 2)
+
+workaround_runtime_start neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_n2_2743089_wa
+workaround_runtime_end neoverse_n2, ERRATUM(2743089)
-func check_errata_2743089
- /* Applies to all revisions <= r0p2 */
- mov x1, #0x02
- b cpu_rev_var_ls
-endfunc check_errata_2743089
+check_erratum_ls neoverse_n2, ERRATUM(2743089), CPU_REV(0, 2)
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+workaround_reset_start neoverse_n2, ERRATUM(2779511), ERRATA_N2_2779511
+ /* Set bit 47 in ACTLR3_EL1 */
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR3_EL1, NEOVERSE_N2_CPUACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_n2, ERRATUM(2779511)
+
+check_erratum_ls neoverse_n2, ERRATUM(2779511), CPU_REV(0, 2)
+
+workaround_reset_start neoverse_n2, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-N2 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
+ */
+ override_vector_table wa_cve_vbar_neoverse_n2
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_n2, CVE(2022,23960)
+
+check_erratum_chosen neoverse_n2, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* -------------------------------------------
* The CPU Ops reset function for Neoverse N2.
* -------------------------------------------
*/
-func neoverse_n2_reset_func
- mov x19, x30
+cpu_reset_func_start neoverse_n2
/* Check if the PE implements SSBS */
mrs x0, id_aa64pfr1_el1
@@ -477,174 +215,39 @@
msr SSBS, xzr
1:
/* Force all cacheable atomic instructions to be near */
- mrs x0, NEOVERSE_N2_CPUACTLR2_EL1
- orr x0, x0, #NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
- msr NEOVERSE_N2_CPUACTLR2_EL1, x0
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_DSU_2313941
- bl errata_dsu_2313941_wa
-#endif
-
-#if ERRATA_N2_2067956
- mov x0, x18
- bl errata_n2_2067956_wa
-#endif
-
-#if ERRATA_N2_2025414
- mov x0, x18
- bl errata_n2_2025414_wa
-#endif
-
-#if ERRATA_N2_2189731
- mov x0, x18
- bl errata_n2_2189731_wa
-#endif
-
-
-#if ERRATA_N2_2138956
- mov x0, x18
- bl errata_n2_2138956_wa
-#endif
-
-#if ERRATA_N2_2138953
- mov x0, x18
- bl errata_n2_2138953_wa
-#endif
-
-#if ERRATA_N2_2242415
- mov x0, x18
- bl errata_n2_2242415_wa
-#endif
-
-#if ERRATA_N2_2138958
- mov x0, x18
- bl errata_n2_2138958_wa
-#endif
-
-#if ERRATA_N2_2242400
- mov x0, x18
- bl errata_n2_2242400_wa
-#endif
-
-#if ERRATA_N2_2280757
- mov x0, x18
- bl errata_n2_2280757_wa
-#endif
-
-#if ERRATA_N2_2376738
- mov x0, x18
- bl errata_n2_2376738_wa
-#endif
-
-#if ERRATA_N2_2388450
- mov x0, x18
- bl errata_n2_2388450_wa
-#endif
+ sysreg_bit_set NEOVERSE_N2_CPUACTLR2_EL1, NEOVERSE_N2_CPUACTLR2_EL1_BIT_2
#if ENABLE_FEAT_AMU
/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
- mrs x0, cptr_el3
- orr x0, x0, #TAM_BIT
- msr cptr_el3, x0
-
+ sysreg_bit_set cptr_el3, TAM_BIT
/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
- mrs x0, cptr_el2
- orr x0, x0, #TAM_BIT
- msr cptr_el2, x0
-
+ sysreg_bit_set cptr_el2, TAM_BIT
/* No need to enable the counters as this would be done at el3 exit */
#endif
#if NEOVERSE_Nx_EXTERNAL_LLC
/* Some systems may have External LLC, core needs to be made aware */
- mrs x0, NEOVERSE_N2_CPUECTLR_EL1
- orr x0, x0, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
- msr NEOVERSE_N2_CPUECTLR_EL1, x0
-#endif
-
-#if ERRATA_N2_2002655
- mov x0, x18
- bl errata_n2_2002655_wa
+ sysreg_bit_set NEOVERSE_N2_CPUECTLR_EL1, NEOVERSE_N2_CPUECTLR_EL1_EXTLLC_BIT
#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-N2 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_n2
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_n2_reset_func
+cpu_reset_func_end neoverse_n2
func neoverse_n2_core_pwr_dwn
-#if ERRATA_N2_2326639
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2326639_wa
- mov x30, x15
-#endif /* ERRATA_N2_2326639 */
+ apply_erratum neoverse_n2, ERRATUM(2326639), ERRATA_N2_2326639
/* ---------------------------------------------------
* Enable CPU power down bit in power control register
* No need to do cache maintenance here.
* ---------------------------------------------------
*/
- mrs x0, NEOVERSE_N2_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_N2_CORE_PWRDN_EN_BIT
- msr NEOVERSE_N2_CPUPWRCTLR_EL1, x0
-#if ERRATA_N2_2743089
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_n2_2743089_wa
- mov x30, x15
-#endif /* ERRATA_N2_2743089 */
+ sysreg_bit_set NEOVERSE_N2_CPUPWRCTLR_EL1, NEOVERSE_N2_CORE_PWRDN_EN_BIT
+
+ apply_erratum neoverse_n2, ERRATUM(2743089), ERRATA_N2_2743089
+
isb
ret
endfunc neoverse_n2_core_pwr_dwn
-#if REPORT_ERRATA
-/*
- * Errata printing function for Neoverse N2 cores. Must follow AAPCS.
- */
-func neoverse_n2_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
-
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_N2_2002655, neoverse_n2, 2002655
- report_errata ERRATA_N2_2067956, neoverse_n2, 2067956
- report_errata ERRATA_N2_2025414, neoverse_n2, 2025414
- report_errata ERRATA_N2_2189731, neoverse_n2, 2189731
- report_errata ERRATA_N2_2138956, neoverse_n2, 2138956
- report_errata ERRATA_N2_2138953, neoverse_n2, 2138953
- report_errata ERRATA_N2_2242415, neoverse_n2, 2242415
- report_errata ERRATA_N2_2138958, neoverse_n2, 2138958
- report_errata ERRATA_N2_2242400, neoverse_n2, 2242400
- report_errata ERRATA_N2_2280757, neoverse_n2, 2280757
- report_errata ERRATA_N2_2326639, neoverse_n2, 2326639
- report_errata ERRATA_N2_2376738, neoverse_n2, 2376738
- report_errata ERRATA_N2_2388450, neoverse_n2, 2388450
- report_errata ERRATA_N2_2743089, neoverse_n2, 2743089
- report_errata WORKAROUND_CVE_2022_23960, neoverse_n2, cve_2022_23960
- report_errata ERRATA_DSU_2313941, neoverse_n2, dsu_2313941
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_n2_errata_report
-#endif
+errata_report_shim neoverse_n2
/* ---------------------------------------------
* This function provides Neoverse N2 specific
diff --git a/lib/cpus/aarch64/neoverse_v1.S b/lib/cpus/aarch64/neoverse_v1.S
index 363c2e6..35d2c48 100644
--- a/lib/cpus/aarch64/neoverse_v1.S
+++ b/lib/cpus/aarch64/neoverse_v1.S
@@ -26,20 +26,7 @@
wa_cve_2022_23960_bhb_vector_table NEOVERSE_V1_BHB_LOOP_COUNT, neoverse_v1
#endif /* WORKAROUND_CVE_2022_23960 */
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1618635.
- * This applies to revision r0p0 and is fixed in
- * r1p0.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1618635_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1618635
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1618635), ERRATA_V1_1618635
/* Inserts a DMB SY before and after MRS PAR_EL1 */
ldr x0, =0x0
msr NEOVERSE_V1_CPUPSELR_EL3, x0
@@ -90,146 +77,39 @@
ldr x0, = 0x4004027FF
msr NEOVERSE_V1_CPUPCR_EL3, x0
- /* Synchronize to enable patches */
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1618635_wa
-
-func check_errata_1618635
- /* Applies to revision r0p0. */
- mov x1, #0x00
- b cpu_rev_var_ls
-endfunc check_errata_1618635
+workaround_reset_end neoverse_v1, ERRATUM(1618635)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1774420.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1774420_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1774420
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(1618635), CPU_REV(0, 0)
+workaround_reset_start neoverse_v1, ERRATUM(1774420), ERRATA_V1_1774420
/* Set bit 53 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_53
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1774420_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_53
+workaround_reset_end neoverse_v1, ERRATUM(1774420)
-func check_errata_1774420
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1774420
+check_erratum_ls neoverse_v1, ERRATUM(1774420), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1791573.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1791573_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1791573
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1791573), ERRATA_V1_1791573
/* Set bit 2 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_2
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1791573_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_2
+workaround_reset_end neoverse_v1, ERRATUM(1791573)
-func check_errata_1791573
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1791573
+check_erratum_ls neoverse_v1, ERRATUM(1791573), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1852267.
- * This applies to revisions r0p0 and r1p0, fixed in r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1852267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1852267
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1852267), ERRATA_V1_1852267
/* Set bit 28 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_28
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1852267_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_28
+workaround_reset_end neoverse_v1, ERRATUM(1852267)
-func check_errata_1852267
- /* Applies to r0p0 and r1p0. */
- mov x1, #0x10
- b cpu_rev_var_ls
-endfunc check_errata_1852267
+check_erratum_ls neoverse_v1, ERRATUM(1852267), CPU_REV(1, 0)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1925756.
- * This applies to revisions <= r1p1.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1925756_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1925756
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1925756), ERRATA_V1_1925756
/* Set bit 8 in CPUECTLR_EL1 */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- orr x1, x1, #NEOVERSE_V1_CPUECTLR_EL1_BIT_8
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1925756_wa
+ sysreg_bit_set NEOVERSE_V1_CPUECTLR_EL1, NEOVERSE_V1_CPUECTLR_EL1_BIT_8
+workaround_reset_end neoverse_v1, ERRATUM(1925756)
-func check_errata_1925756
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_1925756
+check_erratum_ls neoverse_v1, ERRATUM(1925756), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Erratum #1940577
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no fix in that
- * revision.
- * Inputs:
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1940577_wa
- /* Compare x0 against revisions r1p0 - r1p1 */
- mov x17, x30
- bl check_errata_1940577
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(1940577), ERRATA_V1_1940577
mov x0, #0
msr S3_6_C15_C8_0, x0
ldr x0, =0x10E3900002
@@ -257,34 +137,11 @@
ldr x0, =0x2001003FF
msr S3_6_C15_C8_1, x0
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_1940577_wa
+workaround_reset_end neoverse_v1, ERRATUM(1940577)
-func check_errata_1940577
- /* Applies to revisions r1p0 - r1p1. */
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1940577
+check_erratum_range neoverse_v1, ERRATUM(1940577), CPU_REV(1, 0), CPU_REV(1, 1)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #1966096
- * This applies to revisions r1p0 - r1p1 and is open.
- * It also exists in r0p0 but there is no workaround
- * for that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_1966096_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_1966096
- cbz x0, 1f
-
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(1966096), ERRATA_V1_1966096
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE010F12
@@ -293,33 +150,20 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x80000000003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(1966096)
-1:
- ret x17
-endfunc errata_neoverse_v1_1966096_wa
+check_erratum_range neoverse_v1, ERRATUM(1966096), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_1966096
- mov x1, #0x10
- mov x2, #0x11
- b cpu_rev_var_range
-endfunc check_errata_1966096
+workaround_reset_start neoverse_v1, ERRATUM(2108267), ERRATA_V1_2108267
+ mrs x1, NEOVERSE_V1_CPUECTLR_EL1
+ mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
+ bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
+ msr NEOVERSE_V1_CPUECTLR_EL1, x1
+workaround_reset_end neoverse_v1, ERRATUM(2108267)
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2139242.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2139242_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2139242
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2108267), CPU_REV(1, 1)
- /* Apply the workaround. */
+workaround_reset_start neoverse_v1, ERRATUM(2139242), ERRATA_V1_2139242
mov x0, #0x3
msr S3_6_C15_C8_0, x0
ldr x0, =0xEE720F14
@@ -328,63 +172,11 @@
msr S3_6_C15_C8_3, x0
ldr x0, =0x40000005003FF
msr S3_6_C15_C8_1, x0
- isb
+workaround_reset_end neoverse_v1, ERRATUM(2139242)
-1:
- ret x17
-endfunc errata_neoverse_v1_2139242_wa
+check_erratum_ls neoverse_v1, ERRATUM(2139242), CPU_REV(1, 1)
-func check_errata_2139242
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2139242
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2108267.
- * This applies to revisions r0p0, r1p0, and r1p1, it
- * is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2108267_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2108267
- cbz x0, 1f
-
- /* Apply the workaround. */
- mrs x1, NEOVERSE_V1_CPUECTLR_EL1
- mov x0, #NEOVERSE_V1_CPUECTLR_EL1_PF_MODE_CNSRV
- bfi x1, x0, #CPUECTLR_EL1_PF_MODE_LSB, #CPUECTLR_EL1_PF_MODE_WIDTH
- msr NEOVERSE_V1_CPUECTLR_EL1, x1
-1:
- ret x17
-endfunc errata_neoverse_v1_2108267_wa
-
-func check_errata_2108267
- /* Applies to r0p0, r1p0, r1p1 */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2108267
-
- /* --------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2216392.
- * This applies to revisions r1p0 and r1p1 and is
- * still open.
- * This issue is also present in r0p0 but there is no
- * workaround in that revision.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * --------------------------------------------------
- */
-func errata_neoverse_v1_2216392_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2216392
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2216392), ERRATA_V1_2216392
ldr x0, =0x5
msr S3_6_c15_c8_0, x0 /* CPUPSELR_EL3 */
ldr x0, =0x10F600E000
@@ -393,167 +185,56 @@
msr S3_6_c15_c8_3, x0 /* CPUPMR_EL3 */
ldr x0, =0x80000000003FF
msr S3_6_c15_c8_1, x0 /* CPUPCR_EL3 */
+workaround_reset_end neoverse_v1, ERRATUM(2216392)
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2216392_wa
+check_erratum_range neoverse_v1, ERRATUM(2216392), CPU_REV(1, 0), CPU_REV(1, 1)
-func check_errata_2216392
- /* Applies to revisions r1p0 and r1p1. */
- mov x1, #CPU_REV(1, 0)
- mov x2, #CPU_REV(1, 1)
- b cpu_rev_var_range
-endfunc check_errata_2216392
-
- /* -----------------------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2294912.
- * This applies to revisions r0p0, r1p0, and r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * -----------------------------------------------------------------
- */
-func errata_neoverse_v1_2294912_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2294912
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2294912), ERRATA_V1_2294912
/* Set bit 0 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_0
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2294912_wa
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_0
+workaround_reset_end neoverse_v1, ERRATUM(2294912)
-func check_errata_2294912
- /* Applies to r0p0, r1p0, and r1p1 right now */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2294912
+check_erratum_ls neoverse_v1, ERRATUM(2294912), CPU_REV(1, 1)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2372203.
- * This applies to revisions <= r1p1 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2372203_wa
- /* Check workaround compatibility. */
- mov x17, x30
- bl check_errata_2372203
- cbz x0, 1f
-
+workaround_reset_start neoverse_v1, ERRATUM(2372203), ERRATA_V1_2372203
/* Set bit 40 in ACTLR2_EL1 */
- mrs x1, NEOVERSE_V1_ACTLR2_EL1
- orr x1, x1, #NEOVERSE_V1_ACTLR2_EL1_BIT_40
- msr NEOVERSE_V1_ACTLR2_EL1, x1
- isb
-1:
- ret x17
-endfunc errata_neoverse_v1_2372203_wa
-
-func check_errata_2372203
- /* Applies to <= r1p1. */
- mov x1, #0x11
- b cpu_rev_var_ls
-endfunc check_errata_2372203
+ sysreg_bit_set NEOVERSE_V1_ACTLR2_EL1, NEOVERSE_V1_ACTLR2_EL1_BIT_40
+workaround_reset_end neoverse_v1, ERRATUM(2372203)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743093.
- * This applies to revisions <= r1p2 and is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x17
- * ----------------------------------------------------
- */
-func errata_neoverse_v1_2743093_wa
- mov x17, x30
- bl check_errata_2743093
- cbz x0, 1f
+check_erratum_ls neoverse_v1, ERRATUM(2372203), CPU_REV(1, 1)
+workaround_runtime_start neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
/* dsb before isb of power down sequence */
dsb sy
-1:
- ret x17
-endfunc errata_neoverse_v1_2743093_wa
+workaround_runtime_end neoverse_v1, ERRATUM(2743093)
-func check_errata_2743093
- /* Applies to all revisions <= r1p2 */
- mov x1, #0x12
- b cpu_rev_var_ls
-endfunc check_errata_2743093
+check_erratum_ls neoverse_v1, ERRATUM(2743093), CPU_REV(1, 2)
- /* ---------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2743233.
- * This applies to revisions r0p0, r1p0, r1p1 and r1p2.
- * It is still open.
- * x0: variant[4:7] and revisions[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ---------------------------------------------------
- */
-func errata_neoverse_v1_2743233_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2743233
- cbz x0, 1f
+workaround_reset_start neoverse_v1, ERRATUM(2743233), ERRATA_V1_2743233
+ sysreg_bit_clear NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_56
+ sysreg_bit_set NEOVERSE_V1_ACTLR5_EL1, NEOVERSE_V1_ACTLR5_EL1_BIT_55
+workaround_reset_end neoverse_v1, ERRATUM(2743233)
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR5_EL1
- bic x1, x1, #BIT(56)
- orr x1, x1, #BIT(55)
- msr NEOVERSE_V1_ACTLR5_EL1, x1
+check_erratum_ls neoverse_v1, ERRATUM(2743233), CPU_REV(1, 2)
-1:
- ret x17
-endfunc errata_neoverse_v1_2743233_wa
+workaround_reset_start neoverse_v1, ERRATUM(2779461), ERRATA_V1_2779461
+ sysreg_bit_set NEOVERSE_V1_ACTLR3_EL1, NEOVERSE_V1_ACTLR3_EL1_BIT_47
+workaround_reset_end neoverse_v1, ERRATUM(2779461)
-func check_errata_2743233
- /* Applies to r0p0, r1p0, r1p1 and r1p2 */
- mov x1, #CPU_REV(1,2)
- b cpu_rev_var_ls
-endfunc check_errata_2743233
+check_erratum_ls neoverse_v1, ERRATUM(2779461), CPU_REV(1, 2)
- /* ----------------------------------------------------
- * Errata Workaround for Neoverse V1 Errata #2779461.
- * This applies to revisions r0p0, r1p0, r1p1, and r1p2.
- * It is still open.
- * x0: variant[4:7] and revision[0:3] of current cpu.
- * Shall clobber: x0-x1, x17
- * ----------------------------------------------------
+workaround_reset_start neoverse_v1, CVE(2022,23960), WORKAROUND_CVE_2022_23960
+#if IMAGE_BL31
+ /*
+ * The Neoverse-V1 generic vectors are overridden to apply errata
+ * mitigation on exception entry from lower ELs.
*/
-func errata_neoverse_v1_2779461_wa
- /* Check revision. */
- mov x17, x30
- bl check_errata_2779461
- cbz x0, 1f
-
- /* Apply the workaround */
- mrs x1, NEOVERSE_V1_ACTLR3_EL1
- orr x1, x1, #BIT(47)
- msr NEOVERSE_V1_ACTLR3_EL1, x1
+ override_vector_table wa_cve_vbar_neoverse_v1
+#endif /* IMAGE_BL31 */
+workaround_reset_end neoverse_v1, CVE(2022,23960)
-1:
- ret x17
-endfunc errata_neoverse_v1_2779461_wa
-
-func check_errata_2779461
- /* Applies to r0p0, r1p0, r1p1, r1p2 */
- mov x1, #CPU_REV(1, 2)
- b cpu_rev_var_ls
-endfunc check_errata_2779461
-
-func check_errata_cve_2022_23960
-#if WORKAROUND_CVE_2022_23960
- mov x0, #ERRATA_APPLIES
-#else
- mov x0, #ERRATA_MISSING
-#endif
- ret
-endfunc check_errata_cve_2022_23960
+check_erratum_chosen neoverse_v1, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
/* ---------------------------------------------
* HW will do the cache maintenance while powering down
@@ -564,148 +245,19 @@
* Enable CPU power down bit in power control register
* ---------------------------------------------
*/
- mrs x0, NEOVERSE_V1_CPUPWRCTLR_EL1
- orr x0, x0, #NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
- msr NEOVERSE_V1_CPUPWRCTLR_EL1, x0
-#if ERRATA_V1_2743093
- mov x15, x30
- bl cpu_get_rev_var
- bl errata_neoverse_v1_2743093_wa
- mov x30, x15
-#endif /* ERRATA_V1_2743093 */
+ sysreg_bit_set NEOVERSE_V1_CPUPWRCTLR_EL1, NEOVERSE_V1_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
+ apply_erratum neoverse_v1, ERRATUM(2743093), ERRATA_V1_2743093
+
isb
ret
endfunc neoverse_v1_core_pwr_dwn
- /*
- * Errata printing function for Neoverse V1. Must follow AAPCS.
- */
-#if REPORT_ERRATA
-func neoverse_v1_errata_report
- stp x8, x30, [sp, #-16]!
-
- bl cpu_get_rev_var
- mov x8, x0
+errata_report_shim neoverse_v1
- /*
- * Report all errata. The revision-variant information is passed to
- * checking functions of each errata.
- */
- report_errata ERRATA_V1_1618635, neoverse_v1, 1618635
- report_errata ERRATA_V1_1774420, neoverse_v1, 1774420
- report_errata ERRATA_V1_1791573, neoverse_v1, 1791573
- report_errata ERRATA_V1_1852267, neoverse_v1, 1852267
- report_errata ERRATA_V1_1925756, neoverse_v1, 1925756
- report_errata ERRATA_V1_1940577, neoverse_v1, 1940577
- report_errata ERRATA_V1_1966096, neoverse_v1, 1966096
- report_errata ERRATA_V1_2108267, neoverse_v1, 2108267
- report_errata ERRATA_V1_2139242, neoverse_v1, 2139242
- report_errata ERRATA_V1_2216392, neoverse_v1, 2216392
- report_errata ERRATA_V1_2294912, neoverse_v1, 2294912
- report_errata ERRATA_V1_2372203, neoverse_v1, 2372203
- report_errata ERRATA_V1_2743093, neoverse_v1, 2743093
- report_errata ERRATA_V1_2743233, neoverse_v1, 2743233
- report_errata ERRATA_V1_2779461, neoverse_v1, 2779461
- report_errata WORKAROUND_CVE_2022_23960, neoverse_v1, cve_2022_23960
-
- ldp x8, x30, [sp], #16
- ret
-endfunc neoverse_v1_errata_report
-#endif
-
-func neoverse_v1_reset_func
- mov x19, x30
-
+cpu_reset_func_start neoverse_v1
/* Disable speculative loads */
msr SSBS, xzr
- isb
-
- /* Get the CPU revision and stash it in x18. */
- bl cpu_get_rev_var
- mov x18, x0
-
-#if ERRATA_V1_1618635
- mov x0, x18
- bl errata_neoverse_v1_1618635_wa
-#endif
-
-#if ERRATA_V1_1774420
- mov x0, x18
- bl errata_neoverse_v1_1774420_wa
-#endif
-
-#if ERRATA_V1_1791573
- mov x0, x18
- bl errata_neoverse_v1_1791573_wa
-#endif
-
-#if ERRATA_V1_1852267
- mov x0, x18
- bl errata_neoverse_v1_1852267_wa
-#endif
-
-#if ERRATA_V1_1925756
- mov x0, x18
- bl errata_neoverse_v1_1925756_wa
-#endif
-
-#if ERRATA_V1_1940577
- mov x0, x18
- bl errata_neoverse_v1_1940577_wa
-#endif
-
-#if ERRATA_V1_1966096
- mov x0, x18
- bl errata_neoverse_v1_1966096_wa
-#endif
-
-#if ERRATA_V1_2139242
- mov x0, x18
- bl errata_neoverse_v1_2139242_wa
-#endif
-
-#if ERRATA_V1_2108267
- mov x0, x18
- bl errata_neoverse_v1_2108267_wa
-#endif
-
-#if ERRATA_V1_2216392
- mov x0, x18
- bl errata_neoverse_v1_2216392_wa
-#endif
-
-#if ERRATA_V1_2294912
- mov x0, x18
- bl errata_neoverse_v1_2294912_wa
-#endif
-
-#if ERRATA_V1_2372203
- mov x0, x18
- bl errata_neoverse_v1_2372203_wa
-#endif
-
-#if ERRATA_V1_2743233
- mov x0, x18
- bl errata_neoverse_v1_2743233_wa
-#endif
-
-#if ERRATA_V1_2779461
- mov x0, x18
- bl errata_neoverse_v1_2779461_wa
-#endif
-
-#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
- /*
- * The Neoverse-V1 generic vectors are overridden to apply errata
- * mitigation on exception entry from lower ELs.
- */
- adr x0, wa_cve_vbar_neoverse_v1
- msr vbar_el3, x0
-#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
-
- isb
- ret x19
-endfunc neoverse_v1_reset_func
+cpu_reset_func_end neoverse_v1
/* ---------------------------------------------
* This function provides Neoverse-V1 specific
diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk
index 4a80bce..8df0a29 100644
--- a/lib/cpus/cpu-ops.mk
+++ b/lib/cpus/cpu-ops.mk
@@ -612,43 +612,43 @@
CPU_FLAG_LIST += ERRATA_A710_2768515
# Flag to apply erratum 2002655 workaround during reset. This erratum applies
-# to revisions r0p0 of the Neoverse-N2 cpu, it is still open.
+# to revisions r0p0 of the Neoverse-N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2002655
# Flag to apply erratum 2067956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2067956
# Flag to apply erratum 2025414 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2025414
# Flag to apply erratum 2189731 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2189731
# Flag to apply erratum 2138956 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138956
# Flag to apply erratum 2138953 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2138953
# Flag to apply erratum 2242415 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242415
# Flag to apply erratum 2138958 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2138958
# Flag to apply erratum 2242400 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2242400
# Flag to apply erratum 2280757 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu and is still open.
+# to revision r0p0 of the Neoverse N2 cpu and is fixed in r0p1.
CPU_FLAG_LIST += ERRATA_N2_2280757
# Flag to apply erraturm 2326639 workaroud during powerdown. This erratum
@@ -656,7 +656,7 @@
CPU_FLAG_LIST += ERRATA_N2_2326639
# Flag to apply erratum 2376738 workaround during reset. This erratum applies
-# to revision r0p0 of the Neoverse N2 cpu, it is fixed in r0p1.
+# to revision r0p0, r0p1, r0p2, r0p3 of the Neoverse N2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_N2_2376738
# Flag to apply erratum 2388450 workaround during reset. This erratum applies
@@ -668,10 +668,18 @@
# r0p3.
CPU_FLAG_LIST += ERRATA_N2_2728475
+# Flag to apply erratum 2743014 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2743014
+
# Flag to apply erratum 2743089 workaround during during powerdown. This erratum
# applies to all revisions <= r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
CPU_FLAG_LIST += ERRATA_N2_2743089
+# Flag to apply erratum 2779511 workaround during reset. This erratum applies
+# to r0p0, r0p1, r0p2 of the Neoverse N2 cpu, it is fixed in r0p3.
+CPU_FLAG_LIST += ERRATA_N2_2779511
+
# Flag to apply erratum 2002765 workaround during reset. This erratum applies
# to revisions r0p0, r1p0, and r2p0 of the Cortex-X2 cpu and is still open.
CPU_FLAG_LIST += ERRATA_X2_2002765
diff --git a/lib/psci/aarch64/runtime_errata.S b/lib/psci/aarch64/runtime_errata.S
index 8d46691..89e3e12 100644
--- a/lib/psci/aarch64/runtime_errata.S
+++ b/lib/psci/aarch64/runtime_errata.S
@@ -20,7 +20,7 @@
mov x18, x0
#if ERRATA_A510_2684597
- bl errata_cortex_a510_2684597_wa
+ bl erratum_cortex_a510_2684597_wa
#endif
ret x19
diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c
index 41dc563..6a0e967 100644
--- a/plat/allwinner/common/sunxi_scpi_pm.c
+++ b/plat/allwinner/common/sunxi_scpi_pm.c
@@ -125,6 +125,32 @@
psci_power_down_wfi();
}
+static int sunxi_system_reset2(int is_vendor, int reset_type, u_register_t cookie)
+{
+ uint32_t ret;
+
+ if (is_vendor || (reset_type != PSCI_RESET2_SYSTEM_WARM_RESET))
+ return PSCI_E_NOT_SUPPORTED;
+
+ gicv2_cpuif_disable();
+
+ /* Send the system reset request to the SCP. */
+ ret = scpi_sys_power_state(scpi_system_reset);
+ if (ret != SCP_OK) {
+ ERROR("PSCI: SCPI %s failed: %d\n", "reset", ret);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ psci_power_down_wfi();
+
+ /*
+ * Should not reach here.
+ * However sunxi_system_reset2 has to return some value
+ * according to PSCI v1.1 spec.
+ */
+ return PSCI_E_SUCCESS;
+}
+
static int sunxi_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
@@ -177,6 +203,7 @@
.pwr_domain_suspend_finish = sunxi_pwr_domain_on_finish,
.system_off = sunxi_system_off,
.system_reset = sunxi_system_reset,
+ .system_reset2 = sunxi_system_reset2,
.validate_power_state = sunxi_validate_power_state,
.validate_ns_entrypoint = sunxi_validate_ns_entrypoint,
.get_sys_suspend_power_state = sunxi_get_sys_suspend_power_state,
diff --git a/plat/arm/board/fvp/fvp_cpu_errata.mk b/plat/arm/board/fvp/fvp_cpu_errata.mk
index 944571d..b8fa4ea 100644
--- a/plat/arm/board/fvp/fvp_cpu_errata.mk
+++ b/plat/arm/board/fvp/fvp_cpu_errata.mk
@@ -30,6 +30,7 @@
CORTEX_A77_H_INC := 1
CORTEX_A78_H_INC := 1
NEOVERSE_N1_H_INC := 1
+NEOVERSE_N2_H_INC := 1
NEOVERSE_V1_H_INC := 1
CORTEX_A78_AE_H_INC := 1
CORTEX_A510_H_INC := 1
@@ -41,6 +42,7 @@
$(eval $(call add_define, CORTEX_A77_H_INC))
$(eval $(call add_define, CORTEX_A78_H_INC))
$(eval $(call add_define, NEOVERSE_N1_H_INC))
+$(eval $(call add_define, NEOVERSE_N2_H_INC))
$(eval $(call add_define, NEOVERSE_V1_H_INC))
$(eval $(call add_define, CORTEX_A78_AE_H_INC))
$(eval $(call add_define, CORTEX_A510_H_INC))
diff --git a/plat/arm/board/fvp/platform.mk b/plat/arm/board/fvp/platform.mk
index 7df150e..e790f92 100644
--- a/plat/arm/board/fvp/platform.mk
+++ b/plat/arm/board/fvp/platform.mk
@@ -222,7 +222,8 @@
else
FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S \
- lib/cpus/aarch32/cortex_a57.S
+ lib/cpus/aarch32/cortex_a57.S \
+ lib/cpus/aarch32/cortex_a53.S
endif
BL1_SOURCES += drivers/arm/smmu/smmu_v3.c \
diff --git a/plat/arm/board/rdn2/platform.mk b/plat/arm/board/rdn2/platform.mk
index 9ebca23..1506714 100644
--- a/plat/arm/board/rdn2/platform.mk
+++ b/plat/arm/board/rdn2/platform.mk
@@ -72,7 +72,8 @@
ifeq (${RAS_FFH_SUPPORT},1)
BL31_SOURCES += ${RDN2_BASE}/rdn2_ras.c \
${CSS_ENT_BASE}/ras/sgi_ras_common.c \
- ${CSS_ENT_BASE}/ras/sgi_ras_sram.c
+ ${CSS_ENT_BASE}/ras/sgi_ras_sram.c \
+ ${CSS_ENT_BASE}/ras/sgi_ras_cpu.c
endif
# Add the FDT_SOURCES and options for Dynamic Config
diff --git a/plat/arm/board/rdn2/rdn2_ras.c b/plat/arm/board/rdn2/rdn2_ras.c
index c1e5ab6..3aed58e 100644
--- a/plat/arm/board/rdn2/rdn2_ras.c
+++ b/plat/arm/board/rdn2/rdn2_ras.c
@@ -14,6 +14,9 @@
/* Non Secure base RAM ECC UE interrupt */
{SGI_SDEI_DS_EVENT_0, NS_RAM_ECC_UE_INT, SGI_RAS_INTR_TYPE_SPI},
+
+ /* CPU 1-bit ECC CE error interrupt */
+ {SGI_SDEI_DS_EVENT_1, PLAT_CORE_FAULT_IRQ, SGI_RAS_INTR_TYPE_PPI}
};
/* RAS error record list definition, used by the common RAS framework. */
@@ -21,11 +24,15 @@
/* Base element RAM Non-secure error record. */
ERR_RECORD_MEMMAP_V1(SOC_NS_RAM_ERR_REC_BASE, 4, NULL,
&sgi_ras_sram_intr_handler, 0),
+ ERR_RECORD_SYSREG_V1(0, 1, NULL, &sgi_ras_cpu_intr_handler, 0),
};
/* RAS error interrupt list definition, used by the common RAS framework. */
struct ras_interrupt plat_ras_interrupts[] = {
{
+ .intr_number = PLAT_CORE_FAULT_IRQ,
+ .err_record = &plat_err_records[1],
+ }, {
.intr_number = NS_RAM_ECC_CE_INT,
.err_record = &plat_err_records[0],
}, {
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 1c95afb..8c16877 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -40,7 +40,11 @@
static const interrupt_prop_t arm_interrupt_props[] = {
PLAT_ARM_G1S_IRQ_PROPS(INTR_GROUP1S),
- PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0)
+ PLAT_ARM_G0_IRQ_PROPS(INTR_GROUP0),
+#if RAS_FFH_SUPPORT
+ INTR_PROP_DESC(PLAT_CORE_FAULT_IRQ, PLAT_RAS_PRI, INTR_GROUP0,
+ GIC_INTR_CFG_LEVEL)
+#endif
};
/*
diff --git a/plat/arm/css/sgi/include/sgi_ras.h b/plat/arm/css/sgi/include/sgi_ras.h
index 24bbfa7..d311807 100644
--- a/plat/arm/css/sgi/include/sgi_ras.h
+++ b/plat/arm/css/sgi/include/sgi_ras.h
@@ -60,4 +60,9 @@
int probe_data,
const struct err_handler_data *const data);
+/* CPU RAS interrupt handler */
+int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec,
+ int probe_data,
+ const struct err_handler_data *const data);
+
#endif /* SGI_RAS_H */
diff --git a/plat/arm/css/sgi/ras/sgi_ras_cpu.c b/plat/arm/css/sgi/ras/sgi_ras_cpu.c
new file mode 100644
index 0000000..5e77dbb
--- /dev/null
+++ b/plat/arm/css/sgi/ras/sgi_ras_cpu.c
@@ -0,0 +1,211 @@
+/*
+ * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <string.h>
+
+#include <bl31/interrupt_mgmt.h>
+#include <lib/el3_runtime/context_mgmt.h>
+#include <lib/extensions/ras.h>
+#include <plat/common/platform.h>
+#include <services/sdei.h>
+#include <services/spm_mm_svc.h>
+
+#include <sgi_ras.h>
+
+#define CPU_CONTEXT_REG_GPR_ARR_SIZE 32
+#define CPU_CONTEXT_REG_EL1_ARR_SIZE 17
+#define CPU_CONTEXT_REG_EL2_ARR_SIZE 16
+#define CPU_CONTEXT_REG_EL3_ARR_SIZE 10
+
+/*
+ * MM Communicate message header GUID to indicate the payload is intended for
+ * CPU MM driver.
+ */
+struct efi_guid cpu_ecc_event_guid = {
+ 0x2c1b3bfc, 0x42cd, 0x4a66,
+ {0xac, 0xd1, 0xa4, 0xd1, 0x63, 0xe9, 0x90, 0xf6}
+ };
+
+/*
+ * CPU error information data structure communicated as part of MM
+ * Communication data payload.
+ */
+typedef struct {
+ uint64_t ErrStatus;
+ uint64_t ErrMisc0;
+ uint64_t ErrAddr;
+ uint64_t SecurityState;
+ uint64_t ErrCtxGpr[CPU_CONTEXT_REG_GPR_ARR_SIZE];
+ uint64_t ErrCtxEl1Reg[CPU_CONTEXT_REG_EL1_ARR_SIZE];
+ uint64_t ErrCtxEl2Reg[CPU_CONTEXT_REG_EL2_ARR_SIZE];
+ uint64_t ErrCtxEl3Reg[CPU_CONTEXT_REG_EL3_ARR_SIZE];
+} cpu_err_info;
+
+/*
+ * Reads the CPU context and error information from the relevant registers and
+ * populates the CPU error information data structure.
+ */
+static void populate_cpu_err_data(cpu_err_info *cpu_info,
+ uint64_t security_state)
+{
+ void *ctx;
+
+ ctx = cm_get_context(security_state);
+
+ cpu_info->ErrStatus = read_erxstatus_el1();
+ cpu_info->ErrMisc0 = read_erxmisc0_el1();
+ cpu_info->ErrAddr = read_erxaddr_el1();
+ cpu_info->SecurityState = security_state;
+
+ /* populate CPU EL1 context information. */
+ cpu_info->ErrCtxEl1Reg[0] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_ELR_EL1);
+ cpu_info->ErrCtxEl1Reg[1] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_ESR_EL1);
+ cpu_info->ErrCtxEl1Reg[2] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_FAR_EL1);
+ cpu_info->ErrCtxEl1Reg[3] = read_isr_el1();
+ cpu_info->ErrCtxEl1Reg[4] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_MAIR_EL1);
+ cpu_info->ErrCtxEl1Reg[5] = read_midr_el1();
+ cpu_info->ErrCtxEl1Reg[6] = read_mpidr_el1();
+ cpu_info->ErrCtxEl1Reg[7] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SCTLR_EL1);
+ cpu_info->ErrCtxEl1Reg[8] = read_ctx_reg(get_gpregs_ctx(ctx),
+ CTX_GPREG_SP_EL0);
+ cpu_info->ErrCtxEl1Reg[9] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SP_EL1);
+ cpu_info->ErrCtxEl1Reg[10] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_SPSR_EL1);
+ cpu_info->ErrCtxEl1Reg[11] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TCR_EL1);
+ cpu_info->ErrCtxEl1Reg[12] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDR_EL0);
+ cpu_info->ErrCtxEl1Reg[13] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDR_EL1);
+ cpu_info->ErrCtxEl1Reg[14] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TPIDRRO_EL0);
+ cpu_info->ErrCtxEl1Reg[15] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TTBR0_EL1);
+ cpu_info->ErrCtxEl1Reg[16] = read_ctx_reg(get_el1_sysregs_ctx(ctx),
+ CTX_TTBR1_EL1);
+
+#if CTX_INCLUDE_EL2_REGS
+ cpu_info->ErrCtxEl2Reg[0] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ELR_EL2);
+ cpu_info->ErrCtxEl2Reg[1] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ESR_EL2);
+ cpu_info->ErrCtxEl2Reg[2] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_FAR_EL2);
+ cpu_info->ErrCtxEl2Reg[3] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HACR_EL2);
+ cpu_info->ErrCtxEl2Reg[4] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HCR_EL2);
+ cpu_info->ErrCtxEl2Reg[5] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_HPFAR_EL2);
+ cpu_info->ErrCtxEl2Reg[6] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_MAIR_EL2);
+ cpu_info->ErrCtxEl2Reg[7] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SCTLR_EL2);
+ cpu_info->ErrCtxEl2Reg[8] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SP_EL2);
+ cpu_info->ErrCtxEl2Reg[9] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_SPSR_EL2);
+ cpu_info->ErrCtxEl2Reg[10] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TCR_EL2);
+ cpu_info->ErrCtxEl2Reg[11] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TPIDR_EL2);
+ cpu_info->ErrCtxEl2Reg[12] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_TTBR0_EL2);
+ cpu_info->ErrCtxEl2Reg[13] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_VTCR_EL2);
+ cpu_info->ErrCtxEl2Reg[14] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_VTTBR_EL2);
+ cpu_info->ErrCtxEl2Reg[15] = read_ctx_reg(get_el2_sysregs_ctx(ctx),
+ CTX_ESR_EL2);
+#endif
+
+ cpu_info->ErrCtxEl3Reg[0] = read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_ELR_EL3);
+ cpu_info->ErrCtxEl3Reg[1] = read_ctx_reg(get_el3state_ctx(ctx),
+ CTX_ESR_EL3);
+ cpu_info->ErrCtxEl3Reg[2] = read_far_el3();
+ cpu_info->ErrCtxEl3Reg[4] = read_mair_el3();
+ cpu_info->ErrCtxEl3Reg[5] = read_sctlr_el3();
+ cpu_info->ErrCtxEl3Reg[6] = 0; /* sp_el3 */
+ cpu_info->ErrCtxEl3Reg[7] = read_tcr_el3();
+ cpu_info->ErrCtxEl3Reg[8] = read_tpidr_el3();
+ cpu_info->ErrCtxEl3Reg[9] = read_ttbr0_el3();
+}
+
+/* CPU RAS interrupt handler */
+int sgi_ras_cpu_intr_handler(const struct err_record_info *err_rec,
+ int probe_data,
+ const struct err_handler_data *const data)
+{
+ struct sgi_ras_ev_map *ras_map;
+ mm_communicate_header_t *header;
+ cpu_err_info cpu_info = {0};
+ uint64_t clear_status;
+ uint32_t intr;
+ int ret;
+
+ cm_el1_sysregs_context_save(NON_SECURE);
+ intr = data->interrupt;
+
+ INFO("[CPU RAS] CPU intr received = %d on cpu_id = %d\n",
+ intr, plat_my_core_pos());
+
+ INFO("[CPU RAS] ERXMISC0_EL1 = 0x%lx\n", read_erxmisc0_el1());
+ INFO("[CPU RAS] ERXSTATUS_EL1 = 0x%lx\n", read_erxstatus_el1());
+ INFO("[CPU RAS] ERXADDR_EL1 = 0x%lx\n", read_erxaddr_el1());
+
+ /* Populate CPU Error Source Information. */
+ populate_cpu_err_data(&cpu_info, get_interrupt_src_ss(data->flags));
+
+ /* Clear the interrupt. */
+ clear_status = read_erxstatus_el1();
+ write_erxstatus_el1(clear_status);
+ plat_ic_end_of_interrupt(intr);
+
+ header = (void *) PLAT_SPM_BUF_BASE;
+ memset(header, 0, sizeof(*header));
+ memcpy(&header->data, &cpu_info, sizeof(cpu_info));
+ header->message_len = sizeof(cpu_info);
+ memcpy(&header->header_guid, (void *) &cpu_ecc_event_guid,
+ sizeof(struct efi_guid));
+
+ spm_mm_sp_call(MM_COMMUNICATE_AARCH64, (uint64_t)header, 0,
+ plat_my_core_pos());
+
+ /*
+ * Find if this is a RAS interrupt. There must be an event against
+ * this interrupt
+ */
+ ras_map = sgi_find_ras_event_map_by_intr(intr);
+ if (ras_map == NULL) {
+ ERROR("SGI: RAS error info for interrupt id: %d not found\n",
+ intr);
+ return -1;
+ }
+
+ /* Dispatch the event to the SDEI client */
+ ret = sdei_dispatch_event(ras_map->sdei_ev_num);
+ if (ret != 0) {
+ /*
+ * sdei_dispatch_event() may return failing result in some
+ * cases, for example kernel may not have registered a handler
+ * or RAS event may happen early during boot. We restore the NS
+ * context when sdei_dispatch_event() returns failing result.
+ */
+ ERROR("SDEI dispatch failed: %d", ret);
+ cm_el1_sysregs_context_restore(NON_SECURE);
+ cm_set_next_eret_context(NON_SECURE);
+ }
+
+ return ret;
+}
diff --git a/plat/brcm/board/stingray/platform.mk b/plat/brcm/board/stingray/platform.mk
index aa2fe86..67413c6 100644
--- a/plat/brcm/board/stingray/platform.mk
+++ b/plat/brcm/board/stingray/platform.mk
@@ -210,7 +210,8 @@
BL2_SOURCES += plat/${SOC_DIR}/driver/ihost_pll_config.c \
plat/${SOC_DIR}/src/bl2_setup.c \
- plat/${SOC_DIR}/driver/swreg.c
+ plat/${SOC_DIR}/driver/swreg.c \
+ lib/cpus/aarch64/cpu_helpers.S
ifeq (${USE_DDR},yes)
PLAT_INCLUDES += -Iplat/${SOC_DIR}/driver/ddr/soc/include
diff --git a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
index 8e66361..c8a3adf 100644
--- a/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mm/imx8mm_bl31_setup.c
@@ -131,7 +131,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
int i;
@@ -146,9 +146,6 @@
imx_csu_init(csu_cfg);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mm/platform.mk b/plat/imx/imx8m/imx8mm/platform.mk
index 2462517..6f6daf8 100644
--- a/plat/imx/imx8m/imx8mm/platform.mk
+++ b/plat/imx/imx8m/imx8mm/platform.mk
@@ -159,6 +159,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
index aeb1cbf..147249e 100644
--- a/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mn/imx8mn_bl31_setup.c
@@ -122,7 +122,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
int i;
@@ -143,9 +143,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mn/platform.mk b/plat/imx/imx8m/imx8mn/platform.mk
index 4651610..a6b43f2 100644
--- a/plat/imx/imx8m/imx8mn/platform.mk
+++ b/plat/imx/imx8m/imx8mn/platform.mk
@@ -65,6 +65,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
index e25668b..b0a41c7 100644
--- a/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
+++ b/plat/imx/imx8m/imx8mp/imx8mp_bl31_setup.c
@@ -118,7 +118,7 @@
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
- unsigned int console_base = 0U;
+ unsigned int console_base = IMX_BOOT_UART_BASE;
static console_t console;
unsigned int val;
unsigned int i;
@@ -139,9 +139,6 @@
val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x2c);
mmio_write_32(IMX_IOMUX_GPR_BASE + 0x2c, val | 0x3DFF0000);
-#if IMX_BOOT_UART_BASE
- console_base = IMX_BOOT_UART_BASE;
-#endif
if (console_base == 0U) {
console_base = imx8m_uart_get_base();
}
diff --git a/plat/imx/imx8m/imx8mp/platform.mk b/plat/imx/imx8m/imx8mp/platform.mk
index 21836d9..a8400a4 100644
--- a/plat/imx/imx8m/imx8mp/platform.mk
+++ b/plat/imx/imx8m/imx8mp/platform.mk
@@ -156,6 +156,9 @@
$(eval $(call add_define,BL32_SIZE))
IMX_BOOT_UART_BASE ?= 0x30890000
+ifeq (${IMX_BOOT_UART_BASE},auto)
+ override IMX_BOOT_UART_BASE := 0
+endif
$(eval $(call add_define,IMX_BOOT_UART_BASE))
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
diff --git a/plat/nuvoton/common/nuvoton_helpers.S b/plat/nuvoton/common/nuvoton_helpers.S
new file mode 100644
index 0000000..09035a1
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_helpers.S
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef NUVOTON_HELPERS_S
+#define NUVOTON_HELPERS_S
+
+#include <asm_macros.S>
+#include <cortex_a35.h>
+#include <platform_def.h>
+
+ .globl plat_is_my_cpu_primary
+ .globl plat_my_core_pos
+ .globl plat_calc_core_pos
+ .globl plat_reset_handler
+ .globl plat_get_my_entrypoint
+ .globl plat_secondary_cold_boot_setup
+ .globl plat_crash_console_init
+ .globl plat_crash_console_putc
+ .globl plat_crash_console_flush
+ .globl platform_mem_init
+ .globl npcm845x_mailbox_init
+
+ /* --------------------------------------------------------------------
+ * Helper macro that reads the part number of the current CPU and jumps
+ * to the given label if it matches the CPU MIDR provided.
+ *
+ * Clobbers x0.
+ * --------------------------------------------------------------------
+ */
+ .macro jump_if_cpu_midr _cpu_midr, _label
+
+ mrs x0, midr_el1
+ ubfx x0, x0, MIDR_PN_SHIFT, #12
+ cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK)
+ b.eq \_label
+
+ .endm
+
+ /* ----------------------------------------------
+ * The mailbox_base is used to distinguish warm/cold
+ * reset. The mailbox_base is in the data section, not
+ * in .bss, this allows function to start using this
+ * variable before the runtime memory is initialized.
+ * ----------------------------------------------
+ */
+ .section .data.mailbox_base
+ .align 3
+ mailbox_base: .quad 0x0
+
+ /* ---------------------------------------------
+ * void plat_reset_handler(void);
+ *
+ * To add: Determine the SoC type and call the appropriate
+ * reset handler.
+ *----------------------------------------------- */
+
+func plat_reset_handler
+ ret
+endfunc plat_reset_handler
+
+ /* ----------------------------------------------
+ * unsigned int plat_is_my_cpu_primary(void);
+ * This function checks if this is the primary CPU
+ * ----------------------------------------------
+ */
+func plat_is_my_cpu_primary
+ mrs x0, mpidr_el1
+ and x0, x0, #(MPIDR_CPU_MASK)
+ cmp x0, #PLAT_PRIMARY_CPU
+ cset x0, eq
+ ret
+endfunc plat_is_my_cpu_primary
+
+ /* ----------------------------------------------
+ * unsigned int plat_my_core_pos(void)
+ * This Function uses the plat_calc_core_pos()
+ * to get the index of the calling CPU.
+ * ----------------------------------------------
+ */
+func plat_my_core_pos
+ mrs x0, mpidr_el1
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_my_core_pos
+
+ /*
+ * unsigned int plat_calc_core_pos(uint64_t mpidr)
+ * helper function to calculate the core position.
+ * With this function.
+ */
+func plat_calc_core_pos
+ and x1, x0, #MPIDR_CPU_MASK
+ and x0, x0, #MPIDR_CLUSTER_MASK
+ add x0, x1, x0, LSR #6
+ ret
+endfunc plat_calc_core_pos
+
+ /* ---------------------------------------------
+ * function to get the entrypoint.
+ * ---------------------------------------------
+ */
+ /* ---------------------------------------------------------------------
+ * uintptr_t plat_get_my_entrypoint (void);
+ *
+ * Main job of this routine is to distinguish between a cold and a warm
+ * boot.
+ *
+ * This functions returns:
+ * - 0 for a cold boot.
+ * - Any other value for a warm boot.
+ * ---------------------------------------------------------------------
+ */
+func plat_get_my_entrypoint
+ mov x1, x30
+ bl plat_is_my_cpu_primary
+ /*
+ * Secondaries always cold boot.
+ */
+ cbz w0, 1f
+ /*
+ * Primaries warm boot if they are requested
+ * to power off.
+ */
+ mov_imm x0, PLAT_NPCM_TM_HOLD_BASE
+ ldr x0, [x0]
+ cmp x0, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF
+ adr x0, plat_wait_for_warm_boot
+ csel x0, x0, xzr, eq
+ ret x1
+1: mov x0, #0
+ ret x1
+endfunc plat_get_my_entrypoint
+
+func npcm845x_mailbox_init
+ adrp x1, mailbox_base
+ str x0, [x1, :lo12:mailbox_base]
+ ret
+endfunc npcm845x_mailbox_init
+
+func plat_wait_for_warm_boot
+ /*
+ * Calculate address of our hold entry.
+ * As the function will never return, there is no need to save LR.
+ */
+ bl plat_my_core_pos
+ lsl x0, x0, #3
+ mov x8, x0
+ mov_imm x2, PLAT_NPCM_TM_HOLD_BASE
+ add x0, x0, x2
+ mov_imm x2, PLAT_NPCM_TRUSTED_NOTIFICATION_BASE
+ add x8, x8, x2
+ /*
+ * This code runs way before requesting the warmboot of this core,
+ * so it is possible to clear the mailbox before getting a request
+ * to boot.
+ */
+ mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
+ str x1,[x0]
+
+ /* Notify that core is in pending state - do not use x0!, uses x7 and x8! */
+ mov x7, PLAT_NPCM_TM_NOTIFICATION_START
+ str x7,[x8]
+ /*
+ * This code runs way before requesting the warmboot of this core,
+ * so it is possible to clear the mailbox before getting a request
+ * to boot.
+ */
+ mov x1, PLAT_NPCM_TM_HOLD_STATE_WAIT
+ str x1,[x0]
+ /* Wait until we have a go */
+poll_mailbox:
+ wfe
+ ldr x1, [x0]
+ cmp x1, PLAT_NPCM_TM_HOLD_STATE_GO
+ bne poll_mailbox
+
+ mov x7, PLAT_NPCM_TM_NOTIFICATION_BR
+ str x7,[x8]
+ /* Jump to the provided entrypoint */
+ mov_imm x0, PLAT_NPCM_TM_ENTRYPOINT
+ ldr x1, [x0]
+ br x1
+endfunc plat_wait_for_warm_boot
+
+func plat_secondary_cold_boot_setup
+ b plat_wait_for_warm_boot
+endfunc plat_secondary_cold_boot_setup
+
+func plat_crash_console_init
+ mov x0, #1
+ ret
+endfunc plat_crash_console_init
+
+func plat_crash_console_putc
+ ret
+endfunc plat_crash_console_putc
+
+func plat_crash_console_flush
+ mov x0, #0
+ ret
+endfunc plat_crash_console_flush
+
+func platform_mem_init
+ ret
+endfunc platform_mem_init
+
+#endif /* NUVOTON_HELPERS_S */
diff --git a/plat/nuvoton/common/nuvoton_pm.c b/plat/nuvoton/common/nuvoton_pm.c
new file mode 100644
index 0000000..833ebfb
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_pm.c
@@ -0,0 +1,75 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch_helpers.h>
+#include <lib/psci/psci.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+
+/* Allow npcm845x to override these functions */
+#pragma weak plat_arm_program_trusted_mailbox
+#pragma weak plat_setup_psci_ops /* changed to weak */
+
+
+/*******************************************************************************
+ * ARM standard platform handler called to check the validity of the non secure
+ * entrypoint. Returns 0 if the entrypoint is valid, or -1 otherwise.
+ ******************************************************************************/
+int arm_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /*
+ * Check if the non secure entrypoint lies within the non
+ * secure DRAM.
+ */
+ if ((entrypoint >= ARM_NS_DRAM1_BASE) &&
+ (entrypoint < (ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
+ return 0;
+ }
+#ifdef __aarch64__
+ if ((entrypoint >= ARM_DRAM2_BASE) &&
+ (entrypoint < (ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
+ return 0;
+ }
+#endif
+
+ return -1;
+}
+
+int arm_validate_psci_entrypoint(uintptr_t entrypoint)
+{
+ return (arm_validate_ns_entrypoint(entrypoint) == 0) ? PSCI_E_SUCCESS :
+ PSCI_E_INVALID_ADDRESS;
+}
+
+/******************************************************************************
+ * Helper function to save the platform state before a system suspend. Save the
+ * state of the system components which are not in the Always ON power domain.
+ *****************************************************************************/
+void arm_system_pwr_domain_save(void)
+{
+ /* Assert system power domain is available on the platform */
+ assert(PLAT_MAX_PWR_LVL > ARM_PWR_LVL1);
+
+ plat_arm_gic_save();
+
+ /*
+ * Unregister console now so that it is not registered for a second
+ * time during resume.
+ */
+ arm_console_runtime_end();
+
+ /*
+ * All the other peripheral which are configured by TF-A are
+ * re-initialized on resume from system suspend. Hence we
+ * don't save their state here.
+ */
+}
diff --git a/plat/nuvoton/common/nuvoton_topology.c b/plat/nuvoton/common/nuvoton_topology.c
new file mode 100644
index 0000000..892d9e2
--- /dev/null
+++ b/plat/nuvoton/common/nuvoton_topology.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <lib/psci/psci.h>
+#include <lib/semihosting.h>
+#include <plat/common/platform.h>
+
+/*
+ * Since NPCM845 have only powered/non-powered state,
+ * the tree is structure of level 0
+ * (Single cluster == 0) and 4 representing a "leaf" for every CPU
+ */
+const unsigned char npcm845x_power_domain_tree_desc[] = {
+ PLATFORM_CLUSTER_COUNT,
+ PLATFORM_MAX_CPU_PER_CLUSTER
+};
+
+const unsigned char *plat_get_power_domain_tree_desc(void)
+{
+ /* A single cluster with 4 CPUs */
+ return npcm845x_power_domain_tree_desc;
+}
+
+int plat_core_pos_by_mpidr(u_register_t mpidr)
+{
+ unsigned int cluster_id, cpu_id;
+
+ mpidr &= MPIDR_AFFINITY_MASK;
+
+ if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)) {
+ return -1;
+ }
+
+ cluster_id = (unsigned int)MPIDR_AFFLVL1_VAL(mpidr);
+ cpu_id = (unsigned int)MPIDR_AFFLVL0_VAL(mpidr);
+
+ if (cluster_id > PLATFORM_CLUSTER_COUNT ||
+ cpu_id > PLATFORM_MAX_CPU_PER_CLUSTER) {
+ return -1;
+ }
+
+ return (int)(cpu_id + (cluster_id * 4));
+}
diff --git a/plat/nuvoton/common/plat_nuvoton_gic.c b/plat/nuvoton/common/plat_nuvoton_gic.c
new file mode 100644
index 0000000..300670d
--- /dev/null
+++ b/plat/nuvoton/common/plat_nuvoton_gic.c
@@ -0,0 +1,51 @@
+/*
+ * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <common/interrupt_props.h>
+#include <drivers/arm/gicv2.h>
+#include <plat/common/platform.h>
+#include <platform_def.h>
+
+static const interrupt_prop_t g0_interrupt_props[] = {
+ INTR_PROP_DESC(FIQ_SMP_CALL_SGI, GIC_HIGHEST_SEC_PRIORITY,
+ GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
+};
+
+gicv2_driver_data_t arm_gic_data = {
+ .gicd_base = BASE_GICD_BASE,
+ .gicc_base = BASE_GICC_BASE,
+ .interrupt_props = g0_interrupt_props,
+ .interrupt_props_num = ARRAY_SIZE(g0_interrupt_props),
+};
+
+void plat_gic_driver_init(void)
+{
+ gicv2_driver_init(&arm_gic_data);
+}
+
+void plat_gic_init(void)
+{
+ gicv2_distif_init();
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+void plat_gic_cpuif_enable(void)
+{
+ gicv2_cpuif_enable();
+}
+
+void plat_gic_cpuif_disable(void)
+{
+ gicv2_cpuif_disable();
+}
+
+void plat_gic_pcpu_init(void)
+{
+ gicv2_pcpu_distif_init();
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
new file mode 100644
index 0000000..26ddb4b
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
@@ -0,0 +1,352 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <drivers/console.h>
+#include <drivers/generic_delay_timer.h>
+#include <drivers/ti/uart/uart_16550.h>
+#include <lib/debugfs.h>
+#include <lib/extensions/ras.h>
+#include <lib/mmio.h>
+#include <lib/xlat_tables/xlat_tables_compat.h>
+#include <npcm845x_clock.h>
+#include <npcm845x_gcr.h>
+#include <npcm845x_lpuart.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_npcm845x.h>
+#include <platform_def.h>
+
+/*
+ * Placeholder variables for copying the arguments that have been passed to
+ * BL31 from BL2.
+ */
+static entry_point_info_t bl32_image_ep_info;
+static entry_point_info_t bl33_image_ep_info;
+
+#if !RESET_TO_BL31
+/*
+ * Check that BL31_BASE is above ARM_FW_CONFIG_LIMIT. The reserved page
+ * is required for SOC_FW_CONFIG/TOS_FW_CONFIG passed from BL2.
+ */
+/* CASSERT(BL31_BASE >= ARM_FW_CONFIG_LIMIT, assert_bl31_base_overflows); */
+#endif /* !RESET_TO_BL31 */
+
+#define MAP_BL31_TOTAL MAP_REGION_FLAT( \
+ BL31_START, \
+ BL31_END - BL31_START, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#if RECLAIM_INIT_CODE
+IMPORT_SYM(unsigned long, __INIT_CODE_START__, BL_INIT_CODE_BASE);
+IMPORT_SYM(unsigned long, __INIT_CODE_END__, BL_CODE_END_UNALIGNED);
+
+#define BL_INIT_CODE_END ((BL_CODE_END_UNALIGNED + PAGE_SIZE - 1) & \
+ ~(PAGE_SIZE - 1))
+
+#define MAP_BL_INIT_CODE MAP_REGION_FLAT( \
+ BL_INIT_CODE_BASE, \
+ BL_INIT_CODE_END - \
+ BL_INIT_CODE_BASE, \
+ MT_CODE | MT_SECURE)
+#endif /* RECLAIM_INIT_CODE */
+
+#if SEPARATE_NOBITS_REGION
+#define MAP_BL31_NOBITS MAP_REGION_FLAT( \
+ BL31_NOBITS_BASE, \
+ BL31_NOBITS_LIMIT - \
+ BL31_NOBITS_BASE, \
+ MT_MEMORY | MT_RW | EL3_PAS)
+
+#endif /* SEPARATE_NOBITS_REGION */
+
+/******************************************************************************
+ * Return a pointer to the 'entry_point_info' structure of the next image
+ * for the security state specified. BL33 corresponds to the non-secure
+ * image type while BL32 corresponds to the secure image type.
+ * A NULL pointer is returned if the image does not exist.
+ *****************************************************************************/
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type)
+{
+ entry_point_info_t *next_image_info;
+
+ assert(sec_state_is_valid(type));
+ next_image_info = (type == NON_SECURE)
+ ? &bl33_image_ep_info : &bl32_image_ep_info;
+/*
+ * None of the images on the ARM development platforms can have 0x0
+ * as the entrypoint
+ */
+ if (next_image_info->pc) {
+ return next_image_info;
+ } else {
+ return NULL;
+ }
+}
+
+int board_uart_init(void)
+{
+ unsigned long UART_BASE_ADDR;
+ static console_t console;
+
+#ifdef CONFIG_TARGET_ARBEL_PALLADIUM
+ UART_Init(UART0_DEV, UART_MUX_MODE1,
+ UART_BAUDRATE_115200);
+ UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV);
+#else
+ UART_BASE_ADDR = npcm845x_get_base_uart(UART0_DEV);
+#endif /* CONFIG_TARGET_ARBEL_PALLADIUM */
+
+/*
+ * Register UART w/o initialization -
+ * A clock rate of zero means to skip the initialisation.
+ */
+ console_16550_register((uintptr_t)UART_BASE_ADDR, 0, 0, &console);
+
+ return 0;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+ return (unsigned int)COUNTER_FREQUENCY;
+}
+
+/******************************************************************************
+ * Perform any BL31 early platform setup common to ARM standard platforms.
+ * Here is an opportunity to copy parameters passed by the calling EL (S-EL1
+ * in BL2 & EL3 in BL1) before they are lost (potentially). This needs to be
+ * done before the MMU is initialized so that the memory layout can be used
+ * while creating page tables. BL2 has flushed this information to memory,
+ * so we are guaranteed to pick up good data.
+ *****************************************************************************/
+void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
+ u_register_t arg2, u_register_t arg3)
+{
+#if RESET_TO_BL31
+ void *from_bl2 = (void *)arg0;
+ void *plat_params_from_bl2 = (void *)arg3;
+
+ if (from_bl2 != NULL) {
+ assert(from_bl2 == NULL);
+ }
+
+ if (plat_params_from_bl2 != NULL) {
+ assert(plat_params_from_bl2 == NULL);
+ }
+#endif /* RESET_TO_BL31 */
+
+/* Initialize Delay timer */
+ generic_delay_timer_init();
+
+/* Do Specific Board/Chip initializations */
+ board_uart_init();
+
+#if RESET_TO_BL31
+ /* There are no parameters from BL2 if BL31 is a reset vector */
+ assert(from_bl2 == NULL);
+ assert(plat_params_from_bl2 == NULL);
+
+#ifdef BL32_BASE
+ /* Populate entry point information for BL32 */
+ SET_PARAM_HEAD(&bl32_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+ SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
+ bl32_image_ep_info.pc = BL32_BASE;
+ bl32_image_ep_info.spsr = arm_get_spsr_for_bl32_entry();
+
+#if defined(SPD_spmd)
+/*
+ * SPM (hafnium in secure world) expects SPM Core manifest base address
+ * in x0, which in !RESET_TO_BL31 case loaded after base of non shared
+ * SRAM(after 4KB offset of SRAM). But in RESET_TO_BL31 case all non
+ * shared SRAM is allocated to BL31, so to avoid overwriting of manifest
+ * keep it in the last page.
+ */
+ bl32_image_ep_info.args.arg0 = ARM_TRUSTED_SRAM_BASE +
+ PLAT_ARM_TRUSTED_SRAM_SIZE - PAGE_SIZE;
+#endif /* SPD_spmd */
+#endif /* BL32_BASE */
+
+/* Populate entry point information for BL33 */
+ SET_PARAM_HEAD(&bl33_image_ep_info,
+ PARAM_EP,
+ VERSION_1,
+ 0);
+
+/*
+ * Tell BL31 where the non-trusted software image
+ * is located and the entry state information
+ */
+ bl33_image_ep_info.pc = plat_get_ns_image_entrypoint();
+ /* Generic ARM code will switch to EL2, revert to EL1 */
+ bl33_image_ep_info.spsr = arm_get_spsr_for_bl33_entry();
+ bl33_image_ep_info.spsr &= ~0x8;
+ bl33_image_ep_info.spsr |= 0x4;
+
+ SET_SECURITY_STATE(bl33_image_ep_info.h.attr, (uint32_t)NON_SECURE);
+
+#if defined(SPD_spmd) && !(ARM_LINUX_KERNEL_AS_BL33)
+/*
+ * Hafnium in normal world expects its manifest address in x0,
+ * which is loaded at base of DRAM.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_DRAM1_BASE;
+#endif /* SPD_spmd && !ARM_LINUX_KERNEL_AS_BL33 */
+
+#if ARM_LINUX_KERNEL_AS_BL33
+/*
+ * According to the file ``Documentation/arm64/booting.txt`` of the
+ * Linux kernel tree, Linux expects the physical address of the device
+ * tree blob (DTB) in x0, while x1-x3 are reserved for future use and
+ * must be 0.
+ */
+ bl33_image_ep_info.args.arg0 = (u_register_t)ARM_PRELOADED_DTB_BASE;
+ bl33_image_ep_info.args.arg1 = 0U;
+ bl33_image_ep_info.args.arg2 = 0U;
+ bl33_image_ep_info.args.arg3 = 0U;
+#endif /* ARM_LINUX_KERNEL_AS_BL33 */
+
+#else /* RESET_TO_BL31 */
+/*
+ * In debug builds, we pass a special value in 'plat_params_from_bl2'
+ * to verify platform parameters from BL2 to BL31.
+ * In release builds, it's not used.
+ */
+ assert(((unsigned long long)plat_params_from_bl2) ==
+ ARM_BL31_PLAT_PARAM_VAL);
+
+/*
+ * Check params passed from BL2 should not be NULL,
+ */
+ bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
+
+ assert(params_from_bl2 != NULL);
+ assert(params_from_bl2->h.type == PARAM_BL_PARAMS);
+ assert(params_from_bl2->h.version >= VERSION_2);
+
+ bl_params_node_t *bl_params = params_from_bl2->head;
+
+/*
+ * Copy BL33 and BL32 (if present), entry point information.
+ * They are stored in Secure RAM, in BL2's address space.
+ */
+ while (bl_params != NULL) {
+ if (bl_params->image_id == BL32_IMAGE_ID) {
+ bl32_image_ep_info = *bl_params->ep_info;
+ }
+
+ if (bl_params->image_id == BL33_IMAGE_ID) {
+ bl33_image_ep_info = *bl_params->ep_info;
+ }
+
+ bl_params = bl_params->next_params_info;
+ }
+
+ if (bl33_image_ep_info.pc == 0U) {
+ panic();
+ }
+#endif /* RESET_TO_BL31 */
+}
+
+/*******************************************************************************
+ * Perform any BL31 platform setup common to ARM standard platforms
+ ******************************************************************************/
+void bl31_platform_setup(void)
+{
+/* Initialize the GIC driver, cpu and distributor interfaces */
+ plat_gic_driver_init();
+ plat_gic_init();
+
+#if RESET_TO_BL31
+#if defined(PLAT_ARM_MEM_PROT_ADDR)
+ arm_nor_psci_do_dyn_mem_protect();
+#endif /* PLAT_ARM_MEM_PROT_ADDR */
+#else
+/*
+ * In this soluction, we also do the security initialzation
+ * even when BL31 is not in the reset vector
+ */
+ npcm845x_security_setup();
+#endif /* RESET_TO_BL31 */
+
+/* Enable and initialize the System level generic timer */
+ mmio_write_32(ARM_SYS_CNTCTL_BASE + CNTCR_OFF,
+ CNTCR_FCREQ(0U) | CNTCR_EN);
+
+/* Initialize power controller before setting up topology */
+ plat_arm_pwrc_setup();
+
+#if RAS_EXTENSION
+ ras_init();
+#endif
+
+#if USE_DEBUGFS
+ debugfs_init();
+#endif /* USE_DEBUGFS */
+}
+
+void arm_console_runtime_init(void)
+{
+/* Added in order to ignore the original weak function */
+}
+
+void plat_arm_program_trusted_mailbox(uintptr_t address)
+{
+/*
+ * now we don't use ARM mailbox,
+ * so that function added to ignore the weak one
+ */
+}
+
+void __init bl31_plat_arch_setup(void)
+{
+ npcm845x_bl31_plat_arch_setup();
+}
+
+void __init plat_arm_pwrc_setup(void)
+{
+/* NPCM850 is always powered so no need for power control */
+}
+
+void __init npcm845x_bl31_plat_arch_setup(void)
+{
+ const mmap_region_t bl_regions[] = {
+ MAP_BL31_TOTAL,
+#if RECLAIM_INIT_CODE
+ MAP_BL_INIT_CODE,
+#endif /* RECLAIM_INIT_CODE */
+#if SEPARATE_NOBITS_REGION
+ MAP_BL31_NOBITS,
+#endif /* SEPARATE_NOBITS_REGION */
+ ARM_MAP_BL_RO,
+#if USE_ROMLIB
+ ARM_MAP_ROMLIB_CODE,
+ ARM_MAP_ROMLIB_DATA,
+#endif /* USE_ROMLIB */
+#if USE_COHERENT_MEM
+ ARM_MAP_BL_COHERENT_RAM,
+#endif /* USE_COHERENT_MEM */
+ ARM_MAP_SHARED_RAM,
+#ifdef SECONDARY_BRINGUP
+ ARM_MAP_NS_DRAM1,
+ #ifdef BL32_BASE
+ ARM_MAP_BL32_CORE_MEM
+ #endif /* BL32_BASE */
+#endif /* SECONDARY_BRINGUP */
+ {0}
+ };
+ setup_page_tables(bl_regions, plat_arm_get_mmap());
+ enable_mmu_el3(0U);
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_common.c b/plat/nuvoton/npcm845x/npcm845x_common.c
new file mode 100644
index 0000000..fc393fd
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_common.c
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2022-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/bl_common.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+
+#include <lib/xlat_tables/xlat_tables_compat.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+
+#include <platform_def.h>
+
+const mmap_region_t plat_arm_mmap[] = {
+ MAP_DEVICE0,
+ MAP_DEVICE1,
+ {0}
+};
diff --git a/plat/nuvoton/npcm845x/npcm845x_psci.c b/plat/nuvoton/npcm845x/npcm845x_psci.c
new file mode 100644
index 0000000..a954265
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_psci.c
@@ -0,0 +1,436 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <lib/semihosting.h>
+#include <npcm845x_clock.h>
+#include <plat/arm/common/plat_arm.h>
+#include <plat/common/platform.h>
+#include <plat_npcm845x.h>
+
+#define ADP_STOPPED_APPLICATION_EXIT 0x20026
+
+/* Make composite power state parameter till power level 0 */
+#if PSCI_EXTENDED_STATE_ID
+/* Not Extended */
+#define npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+#else
+#define npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type) \
+ (((lvl0_state) << PSTATE_ID_SHIFT) | \
+ ((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
+ ((type) << PSTATE_TYPE_SHIFT))
+#endif /* PSCI_EXTENDED_STATE_ID */
+
+#define npcm845x_make_pwrstate_lvl1(lvl1_state, lvl0_state, pwr_lvl, type) \
+ (((lvl1_state) << PLAT_LOCAL_PSTATE_WIDTH) | \
+ npcm845x_make_pwrstate_lvl0(lvl0_state, pwr_lvl, type))
+
+/*
+ * The table storing the valid idle power states. Ensure that the
+ * array entries are populated in ascending order of state-id to
+ * enable us to use binary search during power state validation.
+ * The table must be terminated by a NULL entry.
+ */
+static const unsigned int npcm845x_pm_idle_states[] = {
+/*
+ * Cluster = 0 (RUN) CPU=1 (RET, higest in idle) -
+ * Retention. The Power state is Stand-by
+ */
+
+/* State-id - 0x01 */
+ npcm845x_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_RET,
+ MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
+
+/*
+ * For testing purposes.
+ * Only CPU suspend to standby is supported by NPCM845x
+ */
+ /* State-id - 0x02 */
+ npcm845x_make_pwrstate_lvl1(PLAT_LOCAL_STATE_RUN, PLAT_LOCAL_STATE_OFF,
+ MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
+ 0,
+};
+
+/*******************************************************************************
+ * Platform handler called to check the validity of the non secure
+ * entrypoint.
+ ******************************************************************************/
+int npcm845x_validate_ns_entrypoint(uintptr_t entrypoint)
+{
+ /*
+ * Check if the non secure entrypoint lies within the non
+ * secure DRAM.
+ */
+ NOTICE("%s() nuvoton_psci\n", __func__);
+#ifdef PLAT_ARM_TRUSTED_DRAM_BASE
+ if ((entrypoint >= PLAT_ARM_TRUSTED_DRAM_BASE) &&
+ (entrypoint < (PLAT_ARM_TRUSTED_DRAM_BASE +
+ PLAT_ARM_TRUSTED_DRAM_SIZE))) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+#endif /* PLAT_ARM_TRUSTED_DRAM_BASE */
+ /* For TFTS purposes, '0' is also illegal */
+ #ifdef SPD_tspd
+ if (entrypoint == 0) {
+ return PSCI_E_INVALID_ADDRESS;
+ }
+ #endif /* SPD_tspd */
+ return PSCI_E_SUCCESS;
+}
+
+/*******************************************************************************
+ * Platform handler called when a CPU is about to enter standby.
+ ******************************************************************************/
+void npcm845x_cpu_standby(plat_local_state_t cpu_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ uint64_t scr;
+
+ scr = read_scr_el3();
+ write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
+
+ /*
+ * Enter standby state
+ * dsb is good practice before using wfi to enter low power states
+ */
+ isb();
+ dsb();
+ wfi();
+
+ /* Once awake */
+ write_scr_el3(scr);
+}
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be turned on. The
+ * mpidr determines the CPU to be turned on.
+ ******************************************************************************/
+int npcm845x_pwr_domain_on(u_register_t mpidr)
+{
+ int rc = PSCI_E_SUCCESS;
+ int cpu_id = plat_core_pos_by_mpidr(mpidr);
+
+ if ((unsigned int)cpu_id >= PLATFORM_CORE_COUNT) {
+ ERROR("%s() CPU 0x%X\n", __func__, cpu_id);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ if (cpu_id == -1) {
+ /* domain on was not called by a CPU */
+ ERROR("%s() was not per CPU 0x%X\n", __func__, cpu_id);
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ unsigned int pos = (unsigned int)plat_core_pos_by_mpidr(mpidr);
+ uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE;
+
+ assert(pos < PLATFORM_CORE_COUNT);
+
+ hold_base += pos * PLAT_NPCM_TM_HOLD_ENTRY_SIZE;
+
+ mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_GO);
+ /* No cache maintenance here, hold_base is mapped as device memory. */
+
+ /* Make sure that the write has completed */
+ dsb();
+ isb();
+
+ sev();
+
+ return rc;
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be suspended. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void npcm845x_pwr_domain_suspend(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ gicv2_cpuif_disable();
+
+ NOTICE("%s() Out of suspend\n", __func__);
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain has just been powered on after
+ * being turned off earlier. The target_state encodes the low power state that
+ * each level has woken up from.
+ ******************************************************************************/
+void npcm845x_pwr_domain_on_finish(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
+ PLAT_LOCAL_STATE_OFF);
+
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+
+/*******************************************************************************
+ * Platform handler called when a power domain has just been powered on after
+ * having been suspended earlier. The target_state encodes the low power state
+ * that each level has woken up from.
+ ******************************************************************************/
+void npcm845x_pwr_domain_suspend_finish(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
+ PLAT_LOCAL_STATE_OFF);
+
+ gicv2_pcpu_distif_init();
+ gicv2_cpuif_enable();
+}
+
+
+void __dead2 npcm845x_system_reset(void)
+{
+ uintptr_t RESET_BASE_ADDR;
+ uint32_t val;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+ console_flush();
+
+ dsbsy();
+ isb();
+
+ /*
+ * In future - support all reset types. For now, SW1 reset
+ * Enable software reset 1 to reboot the BMC
+ */
+ RESET_BASE_ADDR = (uintptr_t)0xF0801000;
+
+ /* Read SW1 control register */
+ val = mmio_read_32(RESET_BASE_ADDR + 0x44);
+ /* Keep SPI BMC & MC persist*/
+ val &= 0xFBFFFFDF;
+ /* Setting SW1 control register */
+ mmio_write_32(RESET_BASE_ADDR + 0x44, val);
+ /* Set SW1 reset */
+ mmio_write_32(RESET_BASE_ADDR + 0x14, 0x8);
+ dsb();
+
+ while (1) {
+ ;
+ }
+}
+
+int npcm845x_validate_power_state(unsigned int power_state,
+ psci_power_state_t *req_state)
+{
+ unsigned int state_id;
+ int i;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+ assert(req_state);
+
+ /*
+ * Currently we are using a linear search for finding the matching
+ * entry in the idle power state array. This can be made a binary
+ * search if the number of entries justify the additional complexity.
+ */
+ for (i = 0; !!npcm845x_pm_idle_states[i]; i++) {
+ if (power_state == npcm845x_pm_idle_states[i]) {
+ break;
+ }
+ }
+
+ /* Return error if entry not found in the idle state array */
+ if (!npcm845x_pm_idle_states[i]) {
+ return PSCI_E_INVALID_PARAMS;
+ }
+
+ i = 0;
+ state_id = psci_get_pstate_id(power_state);
+
+ /* Parse the State ID and populate the state info parameter */
+ while (state_id) {
+ req_state->pwr_domain_state[i++] = (uint8_t)state_id &
+ PLAT_LOCAL_PSTATE_MASK;
+ state_id >>= PLAT_LOCAL_PSTATE_WIDTH;
+ }
+
+ return PSCI_E_SUCCESS;
+}
+
+/*
+ * The NPCM845 doesn't truly support power management at SYSTEM power domain.
+ * The SYSTEM_SUSPEND will be down-graded to the cluster level within
+ * the platform layer. The `fake` SYSTEM_SUSPEND allows us to validate
+ * some of the driver save and restore sequences on FVP.
+ */
+#if !ARM_BL31_IN_DRAM
+void npcm845x_get_sys_suspend_power_state(psci_power_state_t *req_state)
+{
+ unsigned int i;
+
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (i = ARM_PWR_LVL0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ req_state->pwr_domain_state[i] = (uint8_t)PLAT_LOCAL_STATE_OFF;
+ }
+}
+#endif /* !ARM_BL31_IN_DRAM */
+
+/*
+ * The rest of the PSCI implementation are for testing purposes only.
+ * Not supported in Arbel
+ */
+void __dead2 npcm845x_system_off(void)
+{
+ console_flush();
+
+ dsbsy();
+ isb();
+
+ /* NPCM845 doesn't allow real system off, Do reaset instead */
+ /* Do reset here TBD which, in the meanwhile SW1 reset */
+ for (;;) {
+ wfi();
+ }
+}
+
+void __dead2 plat_secondary_cold_boot_setup(void);
+
+void __dead2 npcm845x_pwr_down_wfi(
+ const psci_power_state_t *target_state)
+{
+ uintptr_t hold_base = PLAT_NPCM_TM_HOLD_BASE;
+ unsigned int pos = plat_my_core_pos();
+
+ if (pos == 0) {
+ /*
+ * The secondaries will always be in a wait
+ * for warm boot on reset, but the BSP needs
+ * to be able to distinguish between waiting
+ * for warm boot (e.g. after psci_off, waiting
+ * for psci_on) and a cold boot.
+ */
+ mmio_write_64(hold_base, PLAT_NPCM_TM_HOLD_STATE_BSP_OFF);
+ /* No cache maintenance here, we run with caches off already. */
+ dsb();
+ isb();
+ }
+
+ wfe();
+
+ while (1) {
+ ;
+ }
+}
+
+/*******************************************************************************
+ * Platform handler called when a power domain is about to be turned off. The
+ * target_state encodes the power state that each level should transition to.
+ ******************************************************************************/
+void npcm845x_pwr_domain_off(const psci_power_state_t *target_state)
+{
+ NOTICE("%s() nuvoton_psci\n", __func__);
+
+ for (size_t i = 0; (uint64_t)i <= PLAT_MAX_PWR_LVL; i++) {
+ INFO("%s: target_state->pwr_domain_state[%lu]=%x\n",
+ __func__, i, target_state->pwr_domain_state[i]);
+ }
+
+ plat_secondary_cold_boot_setup();
+}
+
+static const plat_psci_ops_t npcm845x_plat_psci_ops = {
+ .cpu_standby = npcm845x_cpu_standby,
+ .pwr_domain_on = npcm845x_pwr_domain_on,
+ .pwr_domain_suspend = npcm845x_pwr_domain_suspend,
+ .pwr_domain_on_finish = npcm845x_pwr_domain_on_finish,
+ .pwr_domain_suspend_finish = npcm845x_pwr_domain_suspend_finish,
+ .system_reset = npcm845x_system_reset,
+ .validate_power_state = npcm845x_validate_power_state,
+ .validate_ns_entrypoint = npcm845x_validate_ns_entrypoint,
+
+ /* For testing purposes only This PSCI states are not supported */
+ .pwr_domain_off = npcm845x_pwr_domain_off,
+ .pwr_domain_pwr_down_wfi = npcm845x_pwr_down_wfi,
+};
+
+/* For reference only
+ * typedef struct plat_psci_ops {
+ * void (*cpu_standby)(plat_local_state_t cpu_state);
+ * int (*pwr_domain_on)(u_register_t mpidr);
+ * void (*pwr_domain_off)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend_pwrdown_early)(
+ * const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_on_finish)(const psci_power_state_t *target_state);
+ * void (*pwr_domain_on_finish_late)(
+ * const psci_power_state_t *target_state);
+ * void (*pwr_domain_suspend_finish)(
+ * const psci_power_state_t *target_state);
+ * void __dead2 (*pwr_domain_pwr_down_wfi)(
+ * const psci_power_state_t *target_state);
+ * void __dead2 (*system_off)(void);
+ * void __dead2 (*system_reset)(void);
+ * int (*validate_power_state)(unsigned int power_state,
+ * psci_power_state_t *req_state);
+ * int (*validate_ns_entrypoint)(uintptr_t ns_entrypoint);
+ * void (*get_sys_suspend_power_state)(
+ * psci_power_state_t *req_state);
+ * int (*get_pwr_lvl_state_idx)(plat_local_state_t pwr_domain_state,
+ * int pwrlvl);
+ * int (*translate_power_state_by_mpidr)(u_register_t mpidr,
+ * unsigned int power_state,
+ * psci_power_state_t *output_state);
+ * int (*get_node_hw_state)(u_register_t mpidr, unsigned int power_level);
+ * int (*mem_protect_chk)(uintptr_t base, u_register_t length);
+ * int (*read_mem_protect)(int *val);
+ * int (*write_mem_protect)(int val);
+ * int (*system_reset2)(int is_vendor,
+ * int reset_type, u_register_t cookie);
+ * } plat_psci_ops_t;
+ */
+
+int plat_setup_psci_ops(uintptr_t sec_entrypoint,
+ const plat_psci_ops_t **psci_ops)
+{
+ uintptr_t *entrypoint = (void *)PLAT_NPCM_TM_ENTRYPOINT;
+
+ *entrypoint = sec_entrypoint;
+
+ *psci_ops = &npcm845x_plat_psci_ops;
+
+ return 0;
+}
diff --git a/plat/nuvoton/npcm845x/npcm845x_serial_port.c b/plat/nuvoton/npcm845x/npcm845x_serial_port.c
new file mode 100644
index 0000000..946e9d0
--- /dev/null
+++ b/plat/nuvoton/npcm845x/npcm845x_serial_port.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+ *
+ * Copyright (C) 2017-2023 Nuvoton Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <stdbool.h>
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/arm/gicv2.h>
+#include <drivers/delay_timer.h>
+#include <drivers/generic_delay_timer.h>
+#include <lib/mmio.h>
+#include <lib/psci/psci.h>
+#include <npcm845x_clock.h>
+#include <npcm845x_gcr.h>
+#include <npcm845x_lpuart.h>
+#include <plat_npcm845x.h>
+
+
+uintptr_t npcm845x_get_base_uart(UART_DEV_T devNum)
+{
+ return 0xF0000000 + devNum * 0x1000;
+}
+
+uintptr_t npcm845x_get_base_clk(void)
+{
+ return 0xF0801000;
+}
+
+uintptr_t npcm845x_get_base_gcr(void)
+{
+ return 0xF0800000;
+}
+
+void npcm845x_wait_for_empty(int uart_n)
+{
+ volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)npcm845x_get_base_uart(uart_n);
+
+ while ((*(uint8_t *)(uintptr_t)(&uart->lsr) & 0x40) == 0x00) {
+/*
+ * wait for THRE (Transmitter Holding Register Empty)
+ * and TSR (Transmitter Shift Register) to be empty.
+ * Some delay. notice needed some delay so UartUpdateTool
+ * will pass w/o error log
+ */
+ }
+
+ volatile int delay;
+
+ for (delay = 0; delay < 10000; delay++) {
+ ;
+ }
+}
+
+int UART_Init(UART_DEV_T devNum, UART_BAUDRATE_T baudRate)
+{
+ uint32_t val = 0;
+ uintptr_t clk_base = npcm845x_get_base_clk();
+ uintptr_t gcr_base = npcm845x_get_base_gcr();
+ uintptr_t uart_base = npcm845x_get_base_uart(devNum);
+ volatile struct npcmX50_uart *uart = (struct npcmX50_uart *)uart_base;
+
+/* Use CLKREF to be independent of CPU frequency */
+ volatile struct clk_ctl *clk_ctl_obj = (struct clk_ctl *)clk_base;
+ volatile struct npcm845x_gcr *gcr_ctl_obj =
+ (struct npcm845x_gcr *)gcr_base;
+
+ clk_ctl_obj->clksel = clk_ctl_obj->clksel & ~(0x3 << 8);
+ clk_ctl_obj->clksel = clk_ctl_obj->clksel | (0x2 << 8);
+
+ /* Set devider according to baudrate */
+ clk_ctl_obj->clkdiv1 =
+ (unsigned int)(clk_ctl_obj->clkdiv1 & ~(0x1F << 16));
+
+ /* clear bits 11-15 - set value 0 */
+ if (devNum == UART3_DEV) {
+ clk_ctl_obj->clkdiv2 =
+ (unsigned int)(clk_ctl_obj->clkdiv2 & ~(0x1F << 11));
+ }
+
+ npcm845x_wait_for_empty(devNum);
+
+ val = (uint32_t)LCR_WLS_8bit;
+ mmio_write_8((uintptr_t)&uart->lcr, (uint8_t)val);
+
+ /* disable all interrupts */
+ mmio_write_8((uintptr_t)&uart->ier, 0);
+
+ /*
+ * Set the RX FIFO trigger level, reset RX, TX FIFO
+ */
+ val = (uint32_t)(FCR_FME | FCR_RFR | FCR_TFR | FCR_RFITL_4B);
+
+ /* reset TX and RX FIFO */
+ mmio_write_8((uintptr_t)(&uart->fcr), (uint8_t)val);
+
+ /* Set port for 8 bit, 1 stop, no parity */
+ val = (uint32_t)LCR_WLS_8bit;
+
+ /* Set DLAB bit; Accesses the Divisor Latch Registers (DLL, DLM). */
+ val |= 0x80;
+ mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
+
+ /* Baud Rate = UART Clock 24MHz / (16 * (11+2)) = 115384 */
+ mmio_write_8((uintptr_t)(&uart->dll), 11);
+ mmio_write_8((uintptr_t)(&uart->dlm), 0x00);
+
+ val = mmio_read_8((uintptr_t)&uart->lcr);
+
+ /* Clear DLAB bit; Accesses RBR, THR or IER registers. */
+ val &= 0x7F;
+ mmio_write_8((uintptr_t)(&uart->lcr), (uint8_t)val);
+
+ if (devNum == UART0_DEV) {
+ gcr_ctl_obj->mfsel4 &= ~(1 << 1);
+ gcr_ctl_obj->mfsel1 |= 1 << 9;
+ } else if (devNum == UART3_DEV) {
+ /* Pin Mux */
+ gcr_ctl_obj->mfsel4 &= ~(1 << 1);
+ gcr_ctl_obj->mfsel1 |= 1 << 11;
+ gcr_ctl_obj->spswc &= (7 << 0);
+ gcr_ctl_obj->spswc |= (2 << 0);
+ } else {
+ /* halt */
+ while (1) {
+ ;
+ }
+ }
+
+ return 0;
+}
diff --git a/plat/nuvoton/npcm845x/platform.mk b/plat/nuvoton/npcm845x/platform.mk
new file mode 100644
index 0000000..f38ae29
--- /dev/null
+++ b/plat/nuvoton/npcm845x/platform.mk
@@ -0,0 +1,397 @@
+#
+# Copyright (c) 2015-2023, ARM Limited and Contributors. All rights reserved.
+#
+# Copyright (c) 2017-2023 Nuvoton Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# This is a debug flag for bring-up. It allows reducing CPU numbers
+# SECONDARY_BRINGUP := 1
+RESET_TO_BL31 := 1
+PMD_SPM_AT_SEL2 := 0
+#temporary until the RAM size is reduced
+USE_COHERENT_MEM := 1
+
+
+$(eval $(call add_define,RESET_TO_BL31))
+
+ifeq (${ARCH}, aarch64)
+# On ARM standard platorms, the TSP can execute from Trusted SRAM,
+# Trusted DRAM (if available) or the TZC secured area of DRAM.
+# TZC secured DRAM is the default.
+
+ARM_TSP_RAM_LOCATION ?= dram
+
+ifeq (${ARM_TSP_RAM_LOCATION}, tsram)
+ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
+else ifeq (${ARM_TSP_RAM_LOCATION}, tdram)
+ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_DRAM_ID
+else ifeq (${ARM_TSP_RAM_LOCATION}, dram)
+ARM_TSP_RAM_LOCATION_ID = ARM_DRAM_ID
+else
+$(error "Unsupported ARM_TSP_RAM_LOCATION value")
+endif
+
+# Process flags
+# Process ARM_BL31_IN_DRAM flag
+ARM_BL31_IN_DRAM := 0
+$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
+$(eval $(call add_define,ARM_BL31_IN_DRAM))
+else
+ARM_TSP_RAM_LOCATION_ID = ARM_TRUSTED_SRAM_ID
+endif
+
+$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
+
+# For the original power-state parameter format, the State-ID can be encoded
+# according to the recommended encoding or zero. This flag determines which
+# State-ID encoding to be parsed.
+ARM_RECOM_STATE_ID_ENC := 0
+
+# If the PSCI_EXTENDED_STATE_ID is set, then ARM_RECOM_STATE_ID_ENC
+# need to be set. Else throw a build error.
+ifeq (${PSCI_EXTENDED_STATE_ID}, 1)
+ifeq (${ARM_RECOM_STATE_ID_ENC}, 0)
+$(error Build option ARM_RECOM_STATE_ID_ENC needs to be set if \
+ PSCI_EXTENDED_STATE_ID is set for ARM platforms)
+endif
+endif
+
+# Process ARM_RECOM_STATE_ID_ENC flag
+$(eval $(call assert_boolean,ARM_RECOM_STATE_ID_ENC))
+$(eval $(call add_define,ARM_RECOM_STATE_ID_ENC))
+
+# Process ARM_DISABLE_TRUSTED_WDOG flag
+# By default, Trusted Watchdog is always enabled unless SPIN_ON_BL1_EXIT is set
+ARM_DISABLE_TRUSTED_WDOG := 0
+ifeq (${SPIN_ON_BL1_EXIT}, 1)
+ARM_DISABLE_TRUSTED_WDOG := 1
+endif
+$(eval $(call assert_boolean,ARM_DISABLE_TRUSTED_WDOG))
+$(eval $(call add_define,ARM_DISABLE_TRUSTED_WDOG))
+
+# Process ARM_CONFIG_CNTACR
+ARM_CONFIG_CNTACR := 1
+$(eval $(call assert_boolean,ARM_CONFIG_CNTACR))
+$(eval $(call add_define,ARM_CONFIG_CNTACR))
+
+# Process ARM_BL31_IN_DRAM flag
+ARM_BL31_IN_DRAM := 0
+$(eval $(call assert_boolean,ARM_BL31_IN_DRAM))
+$(eval $(call add_define,ARM_BL31_IN_DRAM))
+
+# Process ARM_PLAT_MT flag
+ARM_PLAT_MT := 0
+$(eval $(call assert_boolean,ARM_PLAT_MT))
+$(eval $(call add_define,ARM_PLAT_MT))
+
+# Use translation tables library v2 by default
+ARM_XLAT_TABLES_LIB_V1 := 0
+$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
+$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
+
+# Don't have the Linux kernel as a BL33 image by default
+ARM_LINUX_KERNEL_AS_BL33 := 0
+$(eval $(call assert_boolean,ARM_LINUX_KERNEL_AS_BL33))
+$(eval $(call add_define,ARM_LINUX_KERNEL_AS_BL33))
+
+ifeq (${ARM_LINUX_KERNEL_AS_BL33},1)
+ifeq (${ARCH},aarch64)
+ifneq (${RESET_TO_BL31},1)
+$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_BL31=1.")
+endif
+else
+ifneq (${RESET_TO_SP_MIN},1)
+$(error "ARM_LINUX_KERNEL_AS_BL33 is only available if RESET_TO_SP_MIN=1.")
+endif
+endif
+
+ifndef PRELOADED_BL33_BASE
+$(error "PRELOADED_BL33_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+endif
+
+ifndef ARM_PRELOADED_DTB_BASE
+$(error "ARM_PRELOADED_DTB_BASE must be set if ARM_LINUX_KERNEL_AS_BL33 is used.")
+endif
+
+$(eval $(call add_define,ARM_PRELOADED_DTB_BASE))
+endif
+
+# Use an implementation of SHA-256 with a smaller memory footprint
+# but reduced speed.
+$(eval $(call add_define,MBEDTLS_SHA256_SMALLER))
+
+# Add the build options to pack Trusted OS Extra1 and Trusted OS Extra2 images
+# in the FIP if the platform requires.
+ifneq ($(BL32_EXTRA1),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra1,--tos-fw-extra1))
+endif
+ifneq ($(BL32_EXTRA2),)
+$(eval $(call TOOL_ADD_IMG,bl32_extra2,--tos-fw-extra2))
+endif
+
+# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
+ENABLE_PSCI_STAT := 1
+ENABLE_PMF := 1
+
+# On ARM platforms, separate the code and read-only data sections to allow
+# mapping the former as executable and the latter as execute-never.
+SEPARATE_CODE_AND_RODATA := 1
+
+# On ARM platforms, disable SEPARATE_NOBITS_REGION by default. Both PROGBITS
+# and NOBITS sections of BL31 image are adjacent to each other and loaded
+# into Trusted SRAM.
+SEPARATE_NOBITS_REGION := 0
+
+# In order to support SEPARATE_NOBITS_REGION for Arm platforms, we need to load
+# BL31 PROGBITS into secure DRAM space and BL31 NOBITS into SRAM. Hence mandate
+# the build to require that ARM_BL31_IN_DRAM is enabled as well.
+ifeq ($(SEPARATE_NOBITS_REGION),1)
+ifneq ($(ARM_BL31_IN_DRAM),1)
+$(error For SEPARATE_NOBITS_REGION, ARM_BL31_IN_DRAM must be enabled)
+endif
+
+ifneq ($(RECLAIM_INIT_CODE),0)
+$(error For SEPARATE_NOBITS_REGION, RECLAIM_INIT_CODE cannot be supported)
+endif
+endif
+
+# Disable ARM Cryptocell by default
+ARM_CRYPTOCELL_INTEG := 0
+$(eval $(call assert_boolean,ARM_CRYPTOCELL_INTEG))
+$(eval $(call add_define,ARM_CRYPTOCELL_INTEG))
+
+# Enable PIE support for RESET_TO_BL31 case
+ifeq (${RESET_TO_BL31},1)
+ENABLE_PIE := 1
+endif
+
+# CryptoCell integration relies on coherent buffers for passing data from
+# the AP CPU to the CryptoCell
+
+ifeq (${ARM_CRYPTOCELL_INTEG},1)
+ifeq (${USE_COHERENT_MEM},0)
+$(error "ARM_CRYPTOCELL_INTEG needs USE_COHERENT_MEM to be set.")
+endif
+endif
+
+PLAT_INCLUDES := -Iinclude/plat/nuvoton/npcm845x \
+ -Iinclude/plat/nuvoton/common \
+ -Iinclude/drivers/nuvoton/npcm845x \
+
+ifeq (${ARCH}, aarch64)
+PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
+endif
+
+# Include GICv3 driver files
+include drivers/arm/gic/v2/gicv2.mk
+
+NPCM850_GIC_SOURCES := ${GICV2_SOURCES}
+
+BL31_SOURCES +=lib/cpus/aarch64/cortex_a35.S \
+ plat/common/plat_psci_common.c \
+ drivers/ti/uart/aarch64/16550_console.S \
+ plat/nuvoton/npcm845x/npcm845x_psci.c \
+ plat/nuvoton/npcm845x/npcm845x_serial_port.c \
+ plat/nuvoton/common/nuvoton_topology.c \
+ plat/nuvoton/npcm845x/npcm845x_bl31_setup.c
+
+PLAT_BL_COMMON_SOURCES := drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ plat/common/plat_gicv2.c \
+ plat/arm/common/arm_gicv2.c \
+ plat/nuvoton/common/plat_nuvoton_gic.c \
+ ${NPCM850_GIC_SOURCES} \
+ plat/nuvoton/npcm845x/npcm845x_common.c \
+ plat/nuvoton/common/nuvoton_helpers.S \
+ lib/semihosting/semihosting.c \
+ lib/semihosting/${ARCH}/semihosting_call.S \
+ plat/arm/common/arm_common.c \
+ plat/arm/common/arm_console.c
+
+ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
+PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
+ lib/xlat_tables/${ARCH}/xlat_tables.c
+else
+include lib/xlat_tables_v2/xlat_tables.mk
+
+PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
+endif
+
+ARM_IO_SOURCES += plat/arm/common/arm_io_storage.c \
+ plat/arm/common/fconf/arm_fconf_io.c
+
+ifeq (${SPD},spmd)
+ifeq (${SPMD_SPM_AT_SEL2},1)
+ARM_IO_SOURCES += plat/arm/common/fconf/arm_fconf_sp.c
+endif
+endif
+
+BL1_SOURCES += drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl1_setup.c \
+ plat/arm/common/arm_err.c \
+ ${ARM_IO_SOURCES}
+
+ifdef EL3_PAYLOAD_BASE
+# Need the plat_arm_program_trusted_mailbox() function to release secondary CPUs
+# from their holding pen
+BL1_SOURCES += plat/arm/common/arm_pm.c
+endif
+
+BL2_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ drivers/io/io_fip.c \
+ drivers/io/io_memmap.c \
+ drivers/io/io_storage.c \
+ plat/arm/common/arm_bl2_setup.c \
+ plat/arm/common/arm_err.c \
+ ${ARM_IO_SOURCES}
+
+# Firmware Configuration Framework sources
+include lib/fconf/fconf.mk
+
+# Add `libfdt` and Arm common helpers required for Dynamic Config
+include lib/libfdt/libfdt.mk
+
+DYN_CFG_SOURCES += plat/arm/common/arm_dyn_cfg.c \
+ plat/arm/common/arm_dyn_cfg_helpers.c \
+ common/fdt_wrappers.c
+
+BL1_SOURCES += ${DYN_CFG_SOURCES}
+BL2_SOURCES += ${DYN_CFG_SOURCES}
+
+ifeq (${BL2_AT_EL3},1)
+BL2_SOURCES += plat/arm/common/arm_bl2_el3_setup.c
+endif
+
+# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
+# the AArch32 descriptors.
+BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
+BL2_SOURCES += plat/arm/common/arm_image_load.c \
+ common/desc_image_load.c
+
+ifeq (${SPD},opteed)
+BL2_SOURCES += lib/optee/optee_utils.c
+endif
+
+BL2U_SOURCES += drivers/delay_timer/delay_timer.c \
+ drivers/delay_timer/generic_delay_timer.c \
+ plat/arm/common/arm_bl2u_setup.c
+
+BL31_SOURCES += plat/arm/common/arm_bl31_setup.c \
+ plat/nuvoton/common/nuvoton_pm.c \
+ plat/nuvoton/common/nuvoton_topology.c \
+ plat/common/plat_psci_common.c
+
+ifeq (${ENABLE_PMF}, 1)
+ifeq (${ARCH}, aarch64)
+BL31_SOURCES += plat/arm/common/aarch64/execution_state_switch.c \
+ plat/arm/common/arm_sip_svc.c \
+ lib/pmf/pmf_smc.c
+else
+BL32_SOURCES += plat/arm/common/arm_sip_svc.c \
+ lib/pmf/pmf_smc.c
+endif
+endif
+
+ifeq (${EL3_EXCEPTION_HANDLING},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
+endif
+
+ifeq (${SDEI_SUPPORT},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_sdei.c
+ifeq (${SDEI_IN_FCONF},1)
+BL31_SOURCES += plat/arm/common/fconf/fconf_sdei_getter.c
+endif
+endif
+
+# RAS sources
+ifeq (${RAS_EXTENSION},1)
+BL31_SOURCES += lib/extensions/ras/std_err_record.c \
+ lib/extensions/ras/ras_common.c
+endif
+
+# Pointer Authentication sources
+ifeq (${ENABLE_PAUTH}, 1)
+PLAT_BL_COMMON_SOURCES += plat/arm/common/aarch64/arm_pauth.c \
+ lib/extensions/pauth/pauth_helpers.S
+endif
+
+ifeq (${SPD},spmd)
+BL31_SOURCES += plat/common/plat_spmd_manifest.c \
+ common/fdt_wrappers.c \
+ ${LIBFDT_SRCS}
+endif
+
+ifneq (${TRUSTED_BOARD_BOOT},0)
+# Include common TBB sources
+AUTH_SOURCES := drivers/auth/auth_mod.c \
+ drivers/auth/crypto_mod.c \
+ drivers/auth/img_parser_mod.c \
+ lib/fconf/fconf_tbbr_getter.c
+
+# Include the selected chain of trust sources.
+ifeq (${COT},tbbr)
+AUTH_SOURCES += drivers/auth/tbbr/tbbr_cot_common.c
+BL1_SOURCES += drivers/auth/tbbr/tbbr_cot_bl1.c
+BL2_SOURCES += drivers/auth/tbbr/tbbr_cot_bl2.c
+else ifeq (${COT},dualroot)
+AUTH_SOURCES += drivers/auth/dualroot/cot.c
+else
+$(error Unknown chain of trust ${COT})
+endif
+
+BL1_SOURCES += ${AUTH_SOURCES} \
+ bl1/tbbr/tbbr_img_desc.c \
+ plat/arm/common/arm_bl1_fwu.c \
+ plat/common/tbbr/plat_tbbr.c
+
+BL2_SOURCES += ${AUTH_SOURCES} \
+ plat/common/tbbr/plat_tbbr.c
+
+$(eval $(call TOOL_ADD_IMG,ns_bl2u,--fwu,FWU_))
+
+# We expect to locate the *.mk files under the directories specified below
+ifeq (${ARM_CRYPTOCELL_INTEG},0)
+CRYPTO_LIB_MK := drivers/auth/mbedtls/mbedtls_crypto.mk
+else
+CRYPTO_LIB_MK := drivers/auth/cryptocell/cryptocell_crypto.mk
+endif
+
+IMG_PARSER_LIB_MK := drivers/auth/mbedtls/mbedtls_x509.mk
+
+$(info Including ${CRYPTO_LIB_MK})
+include ${CRYPTO_LIB_MK}
+
+$(info Including ${IMG_PARSER_LIB_MK})
+include ${IMG_PARSER_LIB_MK}
+endif
+
+ifeq (${RECLAIM_INIT_CODE}, 1)
+ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
+$(error "To reclaim init code xlat tables v2 must be used")
+endif
+endif
+
+ifeq (${MEASURED_BOOT},1)
+MEASURED_BOOT_MK := drivers/measured_boot/measured_boot.mk
+$(info Including ${MEASURED_BOOT_MK})
+include ${MEASURED_BOOT_MK}
+endif
+
+ifeq (${EL3_EXCEPTION_HANDLING},1)
+BL31_SOURCES += plat/arm/common/aarch64/arm_ehf.c
+endif
+
+BL1_SOURCES :=
+BL2_SOURCES :=
+BL2U_SOURCES :=
+
+DEBUG_CONSOLE ?= 0
+$(eval $(call add_define,DEBUG_CONSOLE))
+
+$(eval $(call add_define,ARM_TSP_RAM_LOCATION_ID))
+
diff --git a/plat/xilinx/common/include/pm_defs.h b/plat/xilinx/common/include/pm_defs.h
index b80cf45..72ba107 100644
--- a/plat/xilinx/common/include/pm_defs.h
+++ b/plat/xilinx/common/include/pm_defs.h
@@ -174,9 +174,7 @@
PM_CLOCK_GETSTATE,
PM_CLOCK_SETDIVIDER,
PM_CLOCK_GETDIVIDER,
- PM_CLOCK_SETRATE,
- PM_CLOCK_GETRATE,
- PM_CLOCK_SETPARENT,
+ PM_CLOCK_SETPARENT = 43,
PM_CLOCK_GETPARENT,
PM_SECURE_IMAGE,
/* FPGA PL Readback */
diff --git a/plat/xilinx/common/plat_fdt.c b/plat/xilinx/common/plat_fdt.c
index 3d12d51..dc3e893 100644
--- a/plat/xilinx/common/plat_fdt.c
+++ b/plat/xilinx/common/plat_fdt.c
@@ -4,8 +4,10 @@
* SPDX-License-Identifier: BSD-3-Clause
*
*/
+#include <common/debug.h>
#include <common/fdt_fixup.h>
#include <common/fdt_wrappers.h>
+#include <libfdt.h>
#include <plat_fdt.h>
#include <platform_def.h>
diff --git a/plat/xilinx/common/plat_startup.c b/plat/xilinx/common/plat_startup.c
index f45c9f0..5beb765 100644
--- a/plat/xilinx/common/plat_startup.c
+++ b/plat/xilinx/common/plat_startup.c
@@ -157,10 +157,10 @@
#endif /* PLAT_versal_net */
/**
- * xbl_tfa_handover() - Populates the bl32 and bl33 image info structures.
+ * xbl_handover() - Populates the bl32 and bl33 image info structures.
* @bl32: BL32 image info structure.
* @bl33: BL33 image info structure.
- * @tfa_handoff_addr: TF-A handoff address.
+ * @handoff_addr: TF-A handoff address.
*
* Process the handoff parameters from the XBL and populate the BL32 and BL33
* image info structures accordingly.
diff --git a/plat/xilinx/versal/aarch64/versal_helpers.S b/plat/xilinx/versal/aarch64/versal_helpers.S
index f868b18..350ddc4 100644
--- a/plat/xilinx/versal/aarch64/versal_helpers.S
+++ b/plat/xilinx/versal/aarch64/versal_helpers.S
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
index bc62efc..ccebff2 100644
--- a/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
+++ b/plat/xilinx/versal_net/aarch64/versal_net_helpers.S
@@ -6,9 +6,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
-#include <asm_macros.S>
-
#include <arch.h>
+#include <asm_macros.S>
#include <drivers/arm/gicv3.h>
#include <platform_def.h>
diff --git a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
index a96c378..b584031 100644
--- a/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
+++ b/plat/xilinx/zynqmp/aarch64/zynqmp_common.c
@@ -229,20 +229,9 @@
size_t i, j, len;
const char *name = "EG/EV";
-#ifdef IMAGE_BL32
- /*
- * For BL32, get the chip id info directly by reading corresponding
- * registers instead of making pm call. This has limitation
- * that these registers should be configured to have access
- * from APU which is default case.
- */
- chipid[0] = mmio_read_32(ZYNQMP_CSU_BASEADDR + ZYNQMP_CSU_IDCODE_OFFSET);
- chipid[1] = mmio_read_32(EFUSE_BASEADDR + EFUSE_IPDISABLE_OFFSET);
-#else
if (pm_get_chipid(chipid) != PM_RET_SUCCESS) {
return "XCZUUNKN";
}
-#endif
id = chipid[0] & (ZYNQMP_CSU_IDCODE_DEVICE_CODE_MASK |
ZYNQMP_CSU_IDCODE_SVD_MASK);
diff --git a/plat/xilinx/zynqmp/platform.mk b/plat/xilinx/zynqmp/platform.mk
index 36fa0f8..9c79855 100644
--- a/plat/xilinx/zynqmp/platform.mk
+++ b/plat/xilinx/zynqmp/platform.mk
@@ -20,7 +20,7 @@
EL3_EXCEPTION_HANDLING := $(SDEI_SUPPORT)
# pncd SPD requires secure SGI to be handled at EL1
-ifeq (${SPD},pncd)
+ifeq (${SPD}, $(filter ${SPD},pncd tspd))
ifeq (${ZYNQMP_WDT_RESTART},1)
$(error "Error: ZYNQMP_WDT_RESTART and SPD=pncd are incompatible")
endif
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
index ece5954..0199597 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.c
@@ -1321,39 +1321,6 @@
}
/**
- * pm_clock_setrate - Set the clock rate for given id.
- * @clock_id: Id of the clock.
- * @rate: rate value in hz.
- *
- * This function is used by master to set rate for any clock.
- *
- * Return: Returns status, either success or error+reason.
- *
- */
-enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
- uint64_t rate)
-{
- return PM_RET_ERROR_NOTSUPPORTED;
-}
-
-/**
- * pm_clock_getrate - Get the clock rate for given id.
- * @clock_id: Id of the clock.
- * @rate: rate value in hz.
- *
- * This function is used by master to get rate
- * for any clock.
- *
- * Return: Returns status, either success or error+reason.
- *
- */
-enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
- uint64_t *rate)
-{
- return PM_RET_ERROR_NOTSUPPORTED;
-}
-
-/**
* pm_clock_setparent - Set the clock parent for given id.
* @clock_id: Id of the clock.
* @parent_index: Index of the parent clock into clock's parents array.
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
index a2597bc..f69a3e7 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_api_sys.h
@@ -143,10 +143,6 @@
uint32_t divider);
enum pm_ret_status pm_clock_getdivider(uint32_t clock_id,
uint32_t *divider);
-enum pm_ret_status pm_clock_setrate(uint32_t clock_id,
- uint64_t rate);
-enum pm_ret_status pm_clock_getrate(uint32_t clock_id,
- uint64_t *rate);
enum pm_ret_status pm_clock_setparent(uint32_t clock_id,
uint32_t parent_index);
enum pm_ret_status pm_clock_getparent(uint32_t clock_id,
diff --git a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
index e297ecb..5a6a9f8 100644
--- a/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
+++ b/plat/xilinx/zynqmp/pm_service/zynqmp_pm_svc_main.c
@@ -435,23 +435,6 @@
SMC_RET1(handle, (uint64_t)ret | ((uint64_t)value) << 32);
}
- case PM_CLOCK_SETRATE:
- ret = pm_clock_setrate(pm_arg[0],
- ((uint64_t)pm_arg[2]) << 32 | pm_arg[1]);
-
- SMC_RET1(handle, (uint64_t)ret);
-
- case PM_CLOCK_GETRATE:
- {
- uint64_t value = 0;
-
- ret = pm_clock_getrate(pm_arg[0], &value);
- SMC_RET2(handle, (uint64_t)ret |
- (((uint64_t)value & 0xFFFFFFFFU) << 32U),
- (value >> 32U) & 0xFFFFFFFFU);
-
- }
-
case PM_CLOCK_SETPARENT:
ret = pm_clock_setparent(pm_arg[0], pm_arg[1]);
SMC_RET1(handle, (uint64_t)ret);
diff --git a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
index ed3300b..02d0b23 100644
--- a/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
+++ b/plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
@@ -28,9 +28,6 @@
&tsp_boot_console);
console_set_scope(&tsp_boot_console,
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_BOOT);
-
- /* Initialize the platform config for future decision making */
- zynqmp_config_setup();
}
/*******************************************************************************
diff --git a/services/std_svc/errata_abi/cpu_errata_info.h b/services/std_svc/errata_abi/cpu_errata_info.h
index 00a3b73..9906fac 100644
--- a/services/std_svc/errata_abi/cpu_errata_info.h
+++ b/services/std_svc/errata_abi/cpu_errata_info.h
@@ -39,7 +39,7 @@
#include <cortex_a9.h>
#endif
-#define MAX_ERRATA_ENTRIES 16
+#define MAX_ERRATA_ENTRIES 32
#define ERRATA_LIST_END (MAX_ERRATA_ENTRIES - 1)
diff --git a/services/std_svc/errata_abi/errata_abi_main.c b/services/std_svc/errata_abi/errata_abi_main.c
index d7f501b..71a907b 100644
--- a/services/std_svc/errata_abi/errata_abi_main.c
+++ b/services/std_svc/errata_abi/errata_abi_main.c
@@ -346,8 +346,10 @@
[12] = {2388450, 0x00, 0x00, ERRATA_N2_2388450},
[13] = {2728475, 0x00, 0x02, ERRATA_N2_2728475, \
ERRATA_NON_ARM_INTERCONNECT},
- [14] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
- [15 ... ERRATA_LIST_END] = UNDEF_ERRATA,
+ [14] = {2743014, 0x00, 0x02, ERRATA_N2_2743014},
+ [15] = {2743089, 0x00, 0x02, ERRATA_N2_2743089},
+ [16] = {2779511, 0x00, 0x02, ERRATA_N2_2779511},
+ [17 ... ERRATA_LIST_END] = UNDEF_ERRATA,
}
},
#endif /* NEOVERSE_N2_H_INC */