commit 987c20a683b2914695c853d61437def35f75b86b
author Soby Mathew <soby.mathew@arm.com> Mon Mar 18 16:15:12 2019 +0000
committer GitHub <noreply@github.com> Mon Mar 18 16:15:12 2019 +0000
tree 7504880d9bfb8b2958076ec60b7ab5629b041edb
parent 3ff353d35a614b8c57637ea59d1d19245e24f1d0
parent a5447ecabba37752d67a3b06c3f8845fe23b43d9

Merge pull request #1894 from jts-arm/e1_midr

Fix MIDR_EL1 value for Neoverse E1

include/lib/cpus/aarch64/neoverse_e1.h

diff --git a/include/lib/cpus/aarch64/neoverse_e1.h b/include/lib/cpus/aarch64/neoverse_e1.h
index 7084604..96b4661 100644
--- a/include/lib/cpus/aarch64/neoverse_e1.h
+++ b/include/lib/cpus/aarch64/neoverse_e1.h
@@ -9,7 +9,7 @@
 
 #include <lib/utils_def.h>
 
-#define NEOVERSE_E1_MIDR		U(0x410FD060)
+#define NEOVERSE_E1_MIDR		U(0x410FD4A0)
 
 /*******************************************************************************
  * CPU Extended Control register specific definitions.