feat(stm32mp2): add RETRAM map/unmap capability
Add RETRAM base address and size definition at platform level.
RETRAM is used by the DDR driver to store retention registers (DDR
training results) in order to restore them in standby exit sequence.
Add map/unmap services at platform level and configure dedicated RISAB5.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
Signed-off-by: Maxime Méré <maxime.mere@foss.st.com>
Change-Id: I460b36fccce62e83c1fbff298f96b23530aaa4f3
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 9af221c..76930bd 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -120,6 +120,10 @@
int stm32mp_map_ddr_non_cacheable(void);
int stm32mp_unmap_ddr(void);
+/* Functions to map RETRAM, and unmap it */
+int stm32mp_map_retram(void);
+int stm32mp_unmap_retram(void);
+
/* Function to save boot info */
void stm32_save_boot_info(boot_api_context_t *boot_context);
/* Function to get boot peripheral info */
diff --git a/plat/st/stm32mp2/bl2_plat_setup.c b/plat/st/stm32mp2/bl2_plat_setup.c
index eb6c6f8..20cbc6e 100644
--- a/plat/st/stm32mp2/bl2_plat_setup.c
+++ b/plat/st/stm32mp2/bl2_plat_setup.c
@@ -237,6 +237,16 @@
fconf_populate("TB_FW", STM32MP_DTB_BASE);
+ /*
+ * RISAB5 setup (dedicated for RETRAM)
+ *
+ * Allow secure read/writes data accesses to non-secure
+ * blocks or pages, all RISAB registers are writable.
+ * DDR retention registers are saved there and restored
+ * when exiting standby low power state.
+ */
+ mmio_write_32(RISAB5_BASE + RISAB_CR, RISAB_CR_SRWIAD);
+
stm32mp_io_setup();
}
diff --git a/plat/st/stm32mp2/stm32mp2_def.h b/plat/st/stm32mp2/stm32mp2_def.h
index 615e5c9..9838b55 100644
--- a/plat/st/stm32mp2/stm32mp2_def.h
+++ b/plat/st/stm32mp2/stm32mp2_def.h
@@ -73,6 +73,9 @@
#define STM32MP_SYSRAM_SIZE U(0x00040000)
#define SRAM1_BASE U(0x0E040000)
#define SRAM1_SIZE_FOR_TFA U(0x00010000)
+#define RETRAM_BASE U(0x0E080000)
+#define RETRAM_SIZE U(0x00020000)
+
#define STM32MP_SEC_SYSRAM_SIZE STM32MP_SYSRAM_SIZE
/* DDR configuration */
@@ -376,6 +379,7 @@
* STM32MP RIF
******************************************************************************/
#define RISAB3_BASE U(0x42110000)
+#define RISAB5_BASE U(0x42130000)
/*******************************************************************************
* STM32MP CA35SSC
diff --git a/plat/st/stm32mp2/stm32mp2_private.c b/plat/st/stm32mp2/stm32mp2_private.c
index d33fa0b..a37de56 100644
--- a/plat/st/stm32mp2/stm32mp2_private.c
+++ b/plat/st/stm32mp2/stm32mp2_private.c
@@ -71,6 +71,19 @@
enable_mmu_el3(0);
}
+int stm32mp_map_retram(void)
+{
+ return mmap_add_dynamic_region(RETRAM_BASE, RETRAM_BASE,
+ RETRAM_SIZE,
+ MT_RW | MT_SECURE);
+}
+
+int stm32mp_unmap_retram(void)
+{
+ return mmap_remove_dynamic_region(RETRAM_BASE,
+ RETRAM_SIZE);
+}
+
uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
{
if (bank == GPIO_BANK_Z) {