diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst
new file mode 100644
index 0000000..e88a458
--- /dev/null
+++ b/docs/plat/marvell/misc/mvebu-a8k-addr-map.rst
@@ -0,0 +1,49 @@
+Address decoding flow and address translation units of Marvell Armada 8K SoC family
+===================================================================================
+
+::
+
+  +--------------------------------------------------------------------------------------------------+
+  |                                                              +-------------+    +--------------+ |
+  |                                                              | Memory      +-----   DRAM CS    | |
+  |+------------+ +-----------+ +-----------+                    | Controller  |    +--------------+ |
+  ||  AP DMA    | |           | |           |                    +-------------+                     |
+  ||  SD/eMMC   | | CA72 CPUs | |  AP MSS   |                    +-------------+                     |
+  ||  MCI-0/1   | |           | |           |                    | Memory      |                     |
+  |+------+-----+ +--+--------+ +--------+--+  +------------+    | Controller  |     +-------------+ |
+  |       |          |                   |     |            +----- Translaton  |     |AP           | |
+  |       |          |                   |     |            |    +-------------+     |Configuration| |
+  |       |          |                   +-----+            +-------------------------Space        | |
+  |       |          | +-------------+         |  CCU       |                        +-------------+ |
+  |       |          | | MMU         +---------+  Windows   |   +-----------+        +-------------+ |
+  |       |          +-| translation |         |  Lookup    +----           +---------   AP SPI    | |
+  |       |            +-------------+         |            |   |           |        +-------------+ |
+  |       |            +-------------+         |            |   |  IO       |        +-------------+ |
+  |       +------------| SMMU        +---------+            |   |  Windows  +---------  AP MCI0/1  | |
+  |                    | translation |         +------------+   |  Lookup   |        +-------------+ |
+  |                    +---------+---+                          |           |        +-------------+ |
+  |             -                |                              |           +---------   AP STM    | |
+  |             +-----------------                              |           |        +-------------+ |
+  | AP          |                |                              +-+---------+                        |
+  +---------------------------------------------------------------|----------------------------------+
+  +-------------|-------------------------------------------------|----------------------------------+
+  | CP          |            +-------------+               +------+-----+      +-------------------+ |
+  |             |            |             |               |            +-------   SB CFG Space    | |
+  |             |            |   DIOB      |               |            |      +-------------------+ |
+  |             |            |   Windows   -----------------  IOB       |      +-------------------+ |
+  |             |            |   Control   |               |  Windows   +------| SB PCIe-0 - PCIe2 | |
+  |             |            |             |               |  Lookup    |      +-------------------+ |
+  |             |            +------+------+               |            |      +-------------------+ |
+  |             |                   |                      |            +------+      SB NAND      | |
+  |             |                   |                      +------+-----+      +-------------------+ |
+  |             |                   |                             |                                  |
+  |             |                   |                             |                                  |
+  |   +------------------+   +------------+                +------+-----+      +-------------------+ |
+  |   | Network Engine   |   |            |                |            +-------  SB SPI-0/SPI-1   | |
+  |   | Security Engine  |   | PCIe, MSS  |                |  RUNIT     |      +-------------------+ |
+  |   | SATA, USB        |   | DMA        |                |  Windows   |      +-------------------+ |
+  |   | SD/eMMC          |   |            |                |  Lookup    +-------   SB Device Bus   | |
+  |   | TDM, I2C         |   |            |                |            |      +-------------------+ |
+  |   +------------------+   +------------+                +------------+                            |
+  |                                                                                                  |
+  +--------------------------------------------------------------------------------------------------+
diff --git a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt b/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt
deleted file mode 100644
index 586e8b7..0000000
--- a/docs/plat/marvell/misc/mvebu-a8k-addr-map.txt
+++ /dev/null
@@ -1,47 +0,0 @@
-Address decoding flow and address translation units of Marvell Armada 8K SoC family
-
-+--------------------------------------------------------------------------------------------------+
-|                                                              +-------------+    +--------------+ |
-|                                                              | Memory      +-----   DRAM CS    | |
-|+------------+ +-----------+ +-----------+                    | Controller  |    +--------------+ |
-||  AP DMA    | |           | |           |                    +-------------+                     |
-||  SD/eMMC   | | CA72 CPUs | |  AP MSS   |                    +-------------+                     |
-||  MCI-0/1   | |           | |           |                    | Memory      |                     |
-|+------+-----+ +--+--------+ +--------+--+  +------------+    | Controller  |     +-------------+ |
-|       |          |                   |     |            +----- Translaton  |     |AP           | |
-|       |          |                   |     |            |    +-------------+     |Configuration| |
-|       |          |                   +-----+            +-------------------------Space        | |
-|       |          | +-------------+         |  CCU       |                        +-------------+ |
-|       |          | | MMU         +---------+  Windows   |   +-----------+        +-------------+ |
-|       |          +-| translation |         |  Lookup    +----           +---------   AP SPI    | |
-|       |            +-------------+         |            |   |           |        +-------------+ |
-|       |            +-------------+         |            |   |  IO       |        +-------------+ |
-|       +------------| SMMU        +---------+            |   |  Windows  +---------  AP MCI0/1  | |
-|                    | translation |         +------------+   |  Lookup   |        +-------------+ |
-|                    +---------+---+                          |           |        +-------------+ |
-|             -                |                              |           +---------   AP STM    | |
-|             +-----------------                              |           |        +-------------+ |
-| AP          |                |                              +-+---------+                        |
-+---------------------------------------------------------------|----------------------------------+
-+-------------|-------------------------------------------------|----------------------------------+
-| CP          |            +-------------+               +------+-----+      +-------------------+ |
-|             |            |             |               |            +-------   SB CFG Space    | |
-|             |            |   DIOB      |               |            |      +-------------------+ |
-|             |            |   Windows   -----------------  IOB       |      +-------------------+ |
-|             |            |   Control   |               |  Windows   +------| SB PCIe-0 - PCIe2 | |
-|             |            |             |               |  Lookup    |      +-------------------+ |
-|             |            +------+------+               |            |      +-------------------+ |
-|             |                   |                      |            +------+      SB NAND      | |
-|             |                   |                      +------+-----+      +-------------------+ |
-|             |                   |                             |                                  |
-|             |                   |                             |                                  |
-|   +------------------+   +------------+                +------+-----+      +-------------------+ |
-|   | Network Engine   |   |            |                |            +-------  SB SPI-0/SPI-1   | |
-|   | Security Engine  |   | PCIe, MSS  |                |  RUNIT     |      +-------------------+ |
-|   | SATA, USB        |   | DMA        |                |  Windows   |      +-------------------+ |
-|   | SD/eMMC          |   |            |                |  Lookup    +-------   SB Device Bus   | |
-|   | TDM, I2C         |   |            |                |            |      +-------------------+ |
-|   +------------------+   +------------+                +------------+                            |
-|                                                                                                  |
-+--------------------------------------------------------------------------------------------------+
-
diff --git a/docs/plat/marvell/misc/mvebu-amb.rst b/docs/plat/marvell/misc/mvebu-amb.rst
new file mode 100644
index 0000000..d734003
--- /dev/null
+++ b/docs/plat/marvell/misc/mvebu-amb.rst
@@ -0,0 +1,58 @@
+AMB - AXI MBUS address decoding
+===============================
+
+AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs.
+
+The Runit offers a second level of address windows lookup. It is used to map
+transaction towards the CD BootROM, SPI0, SPI1 and Device bus (NOR).
+
+The Runit contains eight configurable windows. Each window defines a contiguous,
+address space and the properties associated with that address space.
+
+::
+
+  Unit        Bank         ATTR
+  Device-Bus  DEV_BOOT_CS  0x2F
+              DEV_CS0      0x3E
+              DEV_CS1      0x3D
+              DEV_CS2      0x3B
+              DEV_CS3      0x37
+  SPI-0       SPI_A_CS0    0x1E
+              SPI_A_CS1    0x5E
+              SPI_A_CS2    0x9E
+              SPI_A_CS3    0xDE
+              SPI_A_CS4    0x1F
+              SPI_A_CS5    0x5F
+              SPI_A_CS6    0x9F
+              SPI_A_CS7    0xDF
+  SPI         SPI_B_CS0    0x1A
+              SPI_B_CS1    0x5A
+              SPI_B_CS2    0x9A
+              SPI_B_CS3    0xDA
+  BOOT_ROM    BOOT_ROM     0x1D
+  UART        UART         0x01
+
+Mandatory functions
+-------------------
+
+- marvell_get_amb_memory_map
+    Returns the AMB windows configuration and the number of windows
+
+Mandatory structures
+--------------------
+
+- amb_memory_map
+    Array that include the configuration of the windows. Every window/entry is a
+    struct which has 2 parameters:
+
+      - Base address of the window
+      - Attribute of the window
+
+Examples
+--------
+
+.. code:: c
+
+    struct addr_map_win amb_memory_map[] = {
+        {0xf900,	AMB_DEV_CS0_ID},
+    };
diff --git a/docs/plat/marvell/misc/mvebu-amb.txt b/docs/plat/marvell/misc/mvebu-amb.txt
deleted file mode 100644
index 2a7a41e..0000000
--- a/docs/plat/marvell/misc/mvebu-amb.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-AMB - AXI MBUS address decoding
--------------------------------
-
-AXI to M-bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs.
-
-- The Runit offers a second level of address windows lookup. It is used to map transaction towards
-the CD BootROM, SPI0, SPI1 and Device bus (NOR).
-- The Runit contains eight configurable windows. Each window defines a contiguous,
-address space and the properties associated with that address space.
-
-Unit		Bank		ATTR
-Device-Bus	DEV_BOOT_CS 	0x2F
-		DEV_CS0     	0x3E
-		DEV_CS1     	0x3D
-		DEV_CS2     	0x3B
-		DEV_CS3     	0x37
-SPI-0		SPI_A_CS0 	0x1E
-		SPI_A_CS1 	0x5E
-		SPI_A_CS2 	0x9E
-		SPI_A_CS3 	0xDE
-		SPI_A_CS4 	0x1F
-		SPI_A_CS5 	0x5F
-		SPI_A_CS6 	0x9F
-		SPI_A_CS7 	0xDF
-SPI1		SPI_B_CS0 	0x1A
-		SPI_B_CS1 	0x5A
-		SPI_B_CS2	0x9A
-		SPI_B_CS3	0xDA
-BOOT_ROM	BOOT_ROM	0x1D
-UART		UART		0x01
-
-Mandatory functions:
-	- marvell_get_amb_memory_map
-		returns the AMB windows configuration and the number of windows
-
-Mandatory structures:
-	amb_memory_map - Array that include the configuration of the windows
-	  every window/entry is a struct which has 2 parameters:
-	  - base address of the window
-	  - Attribute of the window
-
-Examples:
-	struct addr_map_win amb_memory_map[] = {
-		{0xf900,	AMB_DEV_CS0_ID},
-	};
diff --git a/docs/plat/marvell/misc/mvebu-ccu.rst b/docs/plat/marvell/misc/mvebu-ccu.rst
new file mode 100644
index 0000000..5bac11f
--- /dev/null
+++ b/docs/plat/marvell/misc/mvebu-ccu.rst
@@ -0,0 +1,33 @@
+Marvell CCU address decoding bindings
+=====================================
+
+CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
+The CCU node includes a description of the address decoding configuration.
+
+Mandatory functions
+-------------------
+
+- marvell_get_ccu_memory_map
+    Return the CCU windows configuration and the number of windows of the
+    specific AP.
+
+Mandatory structures
+--------------------
+
+- ccu_memory_map
+    Array that includes the configuration of the windows. Every window/entry is
+    a struct which has 3 parameters:
+
+      - Base address of the window
+      - Size of the window
+      - Target-ID of the window
+
+Example
+-------
+
+.. code:: c
+
+	struct addr_map_win ccu_memory_map[] = {
+		{0x00000000f2000000,     0x00000000e000000,      IO_0_TID}, /* IO window */
+	};
diff --git a/docs/plat/marvell/misc/mvebu-ccu.txt b/docs/plat/marvell/misc/mvebu-ccu.txt
deleted file mode 100644
index 9764027..0000000
--- a/docs/plat/marvell/misc/mvebu-ccu.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-Marvell CCU address decoding bindings
-=====================================
-
-CCU configration driver (1st stage address translation) for Marvell Armada 8K and 8K+ SoCs.
-
-The CCU node includes a description of the address decoding configuration.
-
-Mandatory functions:
-	- marvell_get_ccu_memory_map
-		return the CCU windows configuration and the number of windows
-		of the specific AP.
-
-Mandatory structures:
-	ccu_memory_map - Array that includes the configuration of the windows
-	  every window/entry is a struct which has 3 parameters:
-	  - Base address of the window
-	  - Size of the window
-	  - Target-ID of the window
-
-Example:
-	struct addr_map_win ccu_memory_map[] = {
-		{0x00000000f2000000,     0x00000000e000000,      IO_0_TID}, /* IO window */
-	};
diff --git a/docs/plat/marvell/misc/mvebu-io-win.rst b/docs/plat/marvell/misc/mvebu-io-win.rst
new file mode 100644
index 0000000..52845ca
--- /dev/null
+++ b/docs/plat/marvell/misc/mvebu-io-win.rst
@@ -0,0 +1,46 @@
+Marvell IO WIN address decoding bindings
+========================================
+
+IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
+The IO WIN includes a description of the address decoding configuration.
+
+Transactions that are decoded by CCU windows as IO peripheral, have an additional
+layer of decoding. This additional address decoding layer defines one of the
+following targets:
+
+- **0x0** = BootRom
+- **0x1** = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
+- **0x2** = SPI direct access
+- **0x3** = PCIe registers
+- **0x4** = MCI Port
+- **0x5** = PCIe port
+
+Mandatory functions
+-------------------
+
+- marvell_get_io_win_memory_map
+    Returns the IO windows configuration and the number of windows of the
+    specific AP.
+
+Mandatory structures
+--------------------
+
+- io_win_memory_map
+    Array that include the configuration of the windows. Every window/entry is
+    a struct which has 3 parameters:
+
+	  - Base address of the window
+	  - Size of the window
+	  - Target-ID of the window
+
+Example
+-------
+
+.. code:: c
+
+	struct addr_map_win io_win_memory_map[] = {
+		{0x00000000fe000000,	0x000000001f00000,	PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
+		{0x00000000ffe00000,	0x000000000100000,	PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
+		{0x00000000f6000000,	0x000000000100000,	MCIPHY_TID},	/* MCI window  1Mb for PHY-reg*/
+	};
diff --git a/docs/plat/marvell/misc/mvebu-io-win.txt b/docs/plat/marvell/misc/mvebu-io-win.txt
deleted file mode 100644
index c83ad1f..0000000
--- a/docs/plat/marvell/misc/mvebu-io-win.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Marvell IO WIN address decoding bindings
-=====================================
-
-IO Window configration driver (2nd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
-
-The IO WIN includes a description of the address decoding configuration.
-
-Transactions that are decoded by CCU windows as IO peripheral, have an additional
-layer of decoding. This additional address decoding layer defines one of the
-following targets:
-	0x0 = BootRom
-	0x1 = STM (Serial Trace Macro-cell, a programmer's port into trace stream)
-	0x2 = SPI direct access
-	0x3 = PCIe registers
-	0x4 = MCI Port
-	0x5 = PCIe port
-
-Mandatory functions:
-	- marvell_get_io_win_memory_map
-		returns the IO windows configuration and the number of windows
-		of the specific AP.
-
-Mandatory structures:
-	io_win_memory_map - Array that include the configuration of the windows
-	  every window/entry is a struct which has 3 parameters:
-	  - Base address of the window
-	  - Size of the window
-	  - Target-ID of the window
-
-Example:
-	struct addr_map_win io_win_memory_map[] = {
-		{0x00000000fe000000,	0x000000001f00000,	PCIE_PORT_TID}, /* PCIe window 31Mb for PCIe port*/
-		{0x00000000ffe00000,	0x000000000100000,	PCIE_REGS_TID}, /* PCI-REG window 64Kb for PCIe-reg*/
-		{0x00000000f6000000,	0x000000000100000,	MCIPHY_TID},	/* MCI window  1Mb for PHY-reg*/
-	};
diff --git a/docs/plat/marvell/misc/mvebu-iob.rst b/docs/plat/marvell/misc/mvebu-iob.rst
new file mode 100644
index 0000000..d02a7e8
--- /dev/null
+++ b/docs/plat/marvell/misc/mvebu-iob.rst
@@ -0,0 +1,52 @@
+Marvell IOB address decoding bindings
+=====================================
+
+IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
+
+The IOB includes a description of the address decoding configuration.
+
+IOB supports up to n (in CP110 n=24) windows for external memory transaction.
+When a transaction passes through the IOB, its address is compared to each of
+the enabled windows. If there is a hit and it passes the security checks, it is
+advanced to the target port.
+
+Mandatory functions
+-------------------
+
+- marvell_get_iob_memory_map
+     Returns the IOB windows configuration and the number of windows
+
+Mandatory structures
+--------------------
+
+- iob_memory_map
+     Array that includes the configuration of the windows. Every window/entry is
+     a struct which has 3 parameters:
+
+       - Base address of the window
+       - Size of the window
+       - Target-ID of the window
+
+Target ID options
+-----------------
+
+- **0x0** = Internal configuration space
+- **0x1** = MCI0
+- **0x2** = PEX1_X1
+- **0x3** = PEX2_X1
+- **0x4** = PEX0_X4
+- **0x5** = NAND flash
+- **0x6** = RUNIT (NOR/SPI/BootRoom)
+- **0x7** = MCI1
+
+Example
+-------
+
+.. code:: c
+
+	struct addr_map_win iob_memory_map[] = {
+		{0x00000000f7000000,	0x0000000001000000,	PEX1_TID}, /* PEX1_X1 window */
+		{0x00000000f8000000,	0x0000000001000000,	PEX2_TID}, /* PEX2_X1 window */
+		{0x00000000f6000000,	0x0000000001000000,	PEX0_TID}, /* PEX0_X4 window */
+		{0x00000000f9000000,	0x0000000001000000,	NAND_TID}  /* NAND window */
+	};
diff --git a/docs/plat/marvell/misc/mvebu-iob.txt b/docs/plat/marvell/misc/mvebu-iob.txt
deleted file mode 100644
index 97ec09d..0000000
--- a/docs/plat/marvell/misc/mvebu-iob.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Marvell IOB address decoding bindings
-=====================================
-
-IO bridge configration driver (3rd stage address translation) for Marvell Armada 8K and 8K+ SoCs.
-
-The IOB includes a description of the address decoding configuration.
-
-IOB supports up to n (in CP110 n=24) windows for external memory transaction.
-When a transaction passes through the IOB, its address is compared to each of
-the enabled windows. If there is a hit and it passes the security checks, it is
-advanced to the target port.
-
-Mandatory functions:
-	- marvell_get_iob_memory_map
-		returns the IOB windows configuration and the number of windows
-
-Mandatory structures:
-	iob_memory_map - Array that include the configuration of the windows
-	  every window/entry is a struct which has 3 parameters:
-	  - Base address of the window
-	  - Size of the window
-	  - Target-ID of the window
-
-Target ID options:
-	- 0x0 = Internal configuration space
-	- 0x1 = MCI0
-	- 0x2 = PEX1_X1
-	- 0x3 = PEX2_X1
-	- 0x4 = PEX0_X4
-	- 0x5 = NAND flash
-	- 0x6 = RUNIT (NOR/SPI/BootRoom)
-	- 0x7 = MCI1
-
-Example:
-	struct addr_map_win iob_memory_map[] = {
-		{0x00000000f7000000,	0x0000000001000000,	PEX1_TID}, /* PEX1_X1 window */
-		{0x00000000f8000000,	0x0000000001000000,	PEX2_TID}, /* PEX2_X1 window */
-		{0x00000000f6000000,	0x0000000001000000,	PEX0_TID}, /* PEX0_X4 window */
-		{0x00000000f9000000,	0x0000000001000000,	NAND_TID}  /* NAND window */
-	};