rockchip: rk3399: add dram driver
add dram driver, and kernel can through sip function talk to bl31 to
do ddr frequency scaling. and ddr auto powerdown.
Change-Id: I0d0f2869aed95e336c6e23ba96a9310985c84840
diff --git a/plat/rockchip/rk3399/rk3399_def.h b/plat/rockchip/rk3399/rk3399_def.h
index 8ee71a8..fdf93fd 100644
--- a/plat/rockchip/rk3399/rk3399_def.h
+++ b/plat/rockchip/rk3399/rk3399_def.h
@@ -61,6 +61,12 @@
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
+#define CIC_BASE (MMIO_BASE + 0x1620000)
+#define CIC_SIZE SIZE_K(4)
+
+#define DCF_BASE (MMIO_BASE + 0x16a0000)
+#define DCF_SIZE SIZE_K(4)
+
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
@@ -85,12 +91,21 @@
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
+#define SRAM_BASE (MMIO_BASE + 0x18c0000)
+#define SRAM_SIZE SIZE_K(192)
+
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
+#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
+#define DDRC0_SIZE SIZE_K(32)
+
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
+#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
+#define DDRC1_SIZE SIZE_K(32)
+
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
@@ -100,6 +115,14 @@
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
+#define DDR_PI_OFFSET 0x800
+#define DDR_PHY_OFFSET 0x2000
+
+#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
+#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
+#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
+#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
+
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000