corstone700: splitting the platform support into FVP and FPGA
This patch performs the following:
- Creating two corstone700 platforms under corstone700 board:
fvp and fpga
- Since the FVP and FPGA have IP differences, this commit provides a specific DTS for each platform
- The platform can be specified using the TARGET_PLATFORM Makefile variable
(possible values are: fvp or fpga)
- Allowing to use u-boot by:
- Enabling NEED_BL33 option
- Fixing non-secure image base: For no preloaded bl33 we want to
have the NS base set on shared ram. Setup a memory map region
for NS in shared map and set the bl33 address in the area.
- Setting the SYS_COUNTER_FREQ_IN_TICKS based on the selected
platform
- Setting ARM_MAP_SHARED_RAM and ARM_MAP_NS_SHARED_RAM to use MT_MEMORY
Change-Id: I4c8ac3387acb1693ab617bcccab00d80e340c163
Signed-off-by: Rui Miguel Silva <rui.silva@linaro.org>
Signed-off-by: Abdellatif El Khlifi <abdellatif.elkhlifi@arm.com>
diff --git a/fdts/corstone700_fvp.dts b/fdts/corstone700_fvp.dts
new file mode 100644
index 0000000..3b1202d
--- /dev/null
+++ b/fdts/corstone700_fvp.dts
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2020, Arm Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+/dts-v1/;
+
+#include "corstone700.dtsi"
+
+/ {
+ model = "corstone700-fvp";
+
+ /*
+ * Intel StrataFlash J3 NOR flash: 2 x 16-bit interleaved components
+ * Flash total size: 32 MB
+ * Allocated flash space: 8 MB
+ */
+
+ flash@8500000 {
+ compatible = "cfi-flash";
+ reg = <0x8500000 0x800000>;
+ bank-width = <4>;
+ device-width= <2>;
+ };
+
+ ethernet: eth@4010000 {
+ compatible = "smsc,lan91c111";
+ reg = <0x40100000 0x10000>;
+ phy-mode = "mii";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 116 0xf04>;
+ reg-io-width = <2>;
+ smsc,irq-push-pull;
+ };
+};
+
+&refclk {
+ clock-frequency = <50000000>;
+};