tree 7950a0f8c0d417e2f3519ccfb136ec48ca9b9717
parent 7169a29cf3507c5aecdeb073c9d5af476d736d0d
author laurenw-arm <lauren.wehrmeister@arm.com> 1566334284 -0500
committer Deepika Bhavnani <deepika.bhavnani@arm.com> 1570206684 +0300

Neoverse N1 Errata Workaround 1542419

Coherent I-cache is causing a prefetch violation where when the core
executes an instruction that has recently been modified, the core might
fetch a stale instruction which violates the ordering of instruction
fetches.

The workaround includes an instruction sequence to implementation
defined registers to trap all EL0 IC IVAU instructions to EL3 and a trap
handler to execute a TLB inner-shareable invalidation to an arbitrary
address followed by a DSB.

Signed-off-by: Lauren Wehrmeister <lauren.wehrmeister@arm.com>
Change-Id: Ic3b7cbb11cf2eaf9005523ef5578a372593ae4d6