refactor(neoverse-rd): move away from nrd_base_platform_def.h
The nrd_base_platform_def.h file includes CSS, RoS, firmware and
platform port related definitions. This approach of consolidating the
various definitions for multiple generation of platforms into the
nrd_base_platform_def.h file is not scaling well.
So in preparation of moving away from the use of nrd_base_platform_def.h
file for first generation of reference design platforms (A75/N1/V1),
split the definitions in this file into multiple include files. The new
files into which the definitions are refactored are -
- nrd_css_def1.h: includes CSS hardware related definitions
- nrd_css_fw_def1.h: includes CSS firmware related definitions
- nrd_ros_fw_def1.h: includes RoS firmware related definitions
- nrd_plat_arm_def1.h: includes platform port related definitions
RoS (Rest Of System) is used to refer to the part of the reference
design platform that excludes CSS.
The definitions that are only relavant to the first generation of
reference design platforms have been refactored from the
nrd_base_platform_def.h file.
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: Ie730d913235221488c385f9ddf1da46a2b760816
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
new file mode 100644
index 0000000..e5a7466
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_def1.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS specific memory and interrupt map
+ * definitions for the first generation platforms based on the A75, N1 and V1
+ * CPUs. There are minor differences in the memory map of these platforms and
+ * those differences are not in the scope of this file.
+ */
+
+#ifndef NRD_CSS_DEF1_H
+#define NRD_CSS_DEF1_H
+
+/*******************************************************************************
+ * CSS memory map related defines
+ ******************************************************************************/
+
+/* PL011 UART */
+#define SOC_CSS_SEC_UART_BASE UL(0x2A410000)
+#define SOC_CSS_NSEC_UART_BASE UL(0x2A400000)
+#define SOC_CSS_UART_SIZE UL(0x10000)
+
+/* CSS peripherals */
+#define NRD_DEVICE_BASE UL(0x20000000)
+#define NRD_DEVICE_SIZE UL(0x20000000)
+
+/* Secure Watchdog */
+#define SBSA_SECURE_WDOG_BASE UL(0x2A480000)
+
+#endif /* NRD_CSS_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
new file mode 100644
index 0000000..0949d36
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_css_fw_def1.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the CSS firmware specific definitions for
+ * the first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD1_CSS_FW_DEF1_H
+#define NRD1_CSS_FW_DEF1_H
+
+#include <nrd_css_def1.h>
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+/*
+ * Since BL31 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL31_SIZE is
+ * calculated using the current BL31 PROGBITS debug size plus the sizes of BL2
+ * and BL1-RW.
+ */
+#define NRD_BL31_SIZE UL(116 * 1024) /* 116 KB */
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define SOC_CSS_UART_CLK_IN_HZ UL(7372800)
+
+/*******************************************************************************
+ * Watchdog config
+ ******************************************************************************/
+
+#define SBSA_SECURE_WDOG_TIMEOUT UL(100)
+
+/*******************************************************************************
+ * Platform ID
+ ******************************************************************************/
+
+/* Platform ID address */
+#define SSC_VERSION (SSC_REG_BASE + SSC_VERSION_OFFSET)
+#ifndef __ASSEMBLER__
+/* SSC_VERSION related accessors */
+/* Returns the part number of the platform */
+#define GET_NRD_PART_NUM \
+ GET_SSC_VERSION_PART_NUM(mmio_read_32(SSC_VERSION))
+/* Returns the configuration number of the platform */
+#define GET_NRD_CONFIG_NUM \
+ GET_SSC_VERSION_CONFIG(mmio_read_32(SSC_VERSION))
+#endif /* __ASSEMBLER__ */
+
+/*******************************************************************************
+ * MMU mappings
+ ******************************************************************************/
+
+#define NRD_MAP_DEVICE \
+ MAP_REGION_FLAT( \
+ NRD_DEVICE_BASE, \
+ NRD_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define NRD_MAP_DEVICE_REMOTE_CHIP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ NRD_DEVICE_BASE, \
+ NRD_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+#define ARM_MAP_SHARED_RAM_REMOTE_CHIP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ ARM_SHARED_RAM_BASE, \
+ ARM_SHARED_RAM_SIZE, \
+ MT_NON_CACHEABLE | MT_RW | MT_SECURE)
+
+#if SPM_MM
+/*
+ * Stand-alone MM logs would be routed via secure UART. Define page table
+ * entry for secure UART which would be common to all platforms.
+ */
+#define SOC_PLATFORM_SECURE_UART \
+ MAP_REGION_FLAT( \
+ SOC_CSS_SEC_UART_BASE, \
+ SOC_CSS_UART_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+#endif
+
+#endif /* NRD_CSS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
new file mode 100644
index 0000000..641f5e0
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_plat_arm_def1.h
@@ -0,0 +1,195 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the platform port definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs.
+ */
+
+#ifndef NRD_PLAT_ARM_DEF1_H
+#define NRD_PLAT_ARM_DEF1_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_defs.h>
+#include <plat/arm/common/arm_def.h>
+#include <plat/arm/common/arm_spm_def.h>
+#include <plat/arm/css/common/css_def.h>
+#include <plat/common/common_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/*******************************************************************************
+ * Core count
+ ******************************************************************************/
+
+#define PLATFORM_CORE_COUNT (NRD_CHIP_COUNT * \
+ PLAT_ARM_CLUSTER_COUNT * \
+ NRD_MAX_CPUS_PER_CLUSTER * \
+ NRD_MAX_PE_PER_CPU)
+
+/*******************************************************************************
+ * XLAT definitions
+ ******************************************************************************/
+
+#if defined(IMAGE_BL31)
+# if SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP)
+# define PLAT_ARM_MMAP_ENTRIES (10 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (8 + ((NRD_CHIP_COUNT - 1) * 3))
+# define PLAT_SP_IMAGE_MMAP_REGIONS (12)
+# define PLAT_SP_IMAGE_MAX_XLAT_TABLES (14)
+# else
+# define PLAT_ARM_MMAP_ENTRIES (5 + ((NRD_CHIP_COUNT - 1) * 3))
+# define MAX_XLAT_TABLES (6 + ((NRD_CHIP_COUNT - 1) * 3))
+# endif
+#elif defined(IMAGE_BL32)
+# define PLAT_ARM_MMAP_ENTRIES (8)
+# define MAX_XLAT_TABLES (5)
+#elif defined(IMAGE_BL2)
+# define PLAT_ARM_MMAP_ENTRIES (11 + (NRD_CHIP_COUNT - 1))
+
+/*
+ * MAX_XLAT_TABLES entries need to be doubled because when the address width
+ * exceeds 40 bits an additional level of translation is required. In case of
+ * multichip platforms peripherals also fall into address space with width
+ * > 40 bits.
+ */
+# define MAX_XLAT_TABLES (7 + ((NRD_CHIP_COUNT - 1) * 2))
+#elif !USE_ROMLIB
+# define PLAT_ARM_MMAP_ENTRIES (11)
+# define MAX_XLAT_TABLES (7)
+#else
+# define PLAT_ARM_MMAP_ENTRIES (12)
+# define MAX_XLAT_TABLES (6)
+#endif
+
+/*******************************************************************************
+ * Stack size
+ ******************************************************************************/
+
+#if defined(IMAGE_BL1)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE (0x1000)
+# else
+# define PLATFORM_STACK_SIZE (0x440)
+# endif
+#elif defined(IMAGE_BL2)
+# if TRUSTED_BOARD_BOOT
+# define PLATFORM_STACK_SIZE (0x1000)
+# else
+# define PLATFORM_STACK_SIZE (0x400)
+# endif
+#elif defined(IMAGE_BL2U)
+# define PLATFORM_STACK_SIZE (0x400)
+#elif defined(IMAGE_BL31)
+# if SPM_MM
+# define PLATFORM_STACK_SIZE (0x500)
+# else
+# define PLATFORM_STACK_SIZE (0x400)
+# endif
+#elif defined(IMAGE_BL32)
+# define PLATFORM_STACK_SIZE (0x440)
+#endif
+
+#if (SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP))
+/*
+ * Secure partition stack follows right after the memory region that is shared
+ * between EL3 and S-EL0.
+ */
+#define PLAT_ARM_SP_IMAGE_STACK_BASE (PLAT_SP_IMAGE_NS_BUF_BASE + \
+ PLAT_SP_IMAGE_NS_BUF_SIZE)
+#endif /* SPM_MM || (SPMC_AT_EL3 && SPMC_AT_EL3_SEL0_SP) */
+
+/*******************************************************************************
+ * BL sizes
+ ******************************************************************************/
+
+#define PLAT_ARM_MAX_BL1_RW_SIZE (64 * 1024) /* 64 KB */
+#if USE_ROMLIB
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE (0x1000)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE (0xe000)
+#else
+#define PLAT_ARM_MAX_ROMLIB_RW_SIZE (0)
+#define PLAT_ARM_MAX_ROMLIB_RO_SIZE (0)
+#endif
+
+/*
+ * PLAT_ARM_MAX_BL2_SIZE is calculated using the current BL2 debug size plus a
+ * little space for growth. Additional 8KiB space is added per chip in
+ * order to accommodate the additional level of translation required for "TZC"
+ * peripheral access which lies in >4TB address space.
+ *
+ */
+#if TRUSTED_BOARD_BOOT
+# define PLAT_ARM_MAX_BL2_SIZE (0x20000 + ((NRD_CHIP_COUNT - 1) * \
+ 0x2000))
+#else
+# define PLAT_ARM_MAX_BL2_SIZE (0x14000 + ((NRD_CHIP_COUNT - 1) * \
+ 0x2000))
+#endif
+
+#define PLAT_ARM_MAX_BL31_SIZE (NRD_BL31_SIZE + \
+ PLAT_ARM_MAX_BL2_SIZE + \
+ PLAT_ARM_MAX_BL1_RW_SIZE)
+
+/*******************************************************************************
+ * ROM, SRAM and DRAM config
+ ******************************************************************************/
+
+#define PLAT_ARM_TRUSTED_SRAM_SIZE (0x00080000) /* 512 KB */
+
+#define PLAT_ARM_TRUSTED_ROM_BASE (0x0)
+#define PLAT_ARM_TRUSTED_ROM_SIZE (0x00080000) /* 512KB */
+
+#define PLAT_ARM_NSRAM_BASE (0x06000000)
+#define PLAT_ARM_NSRAM_SIZE (0x00080000) /* 512KB */
+
+#define PLAT_ARM_DRAM2_BASE ULL(0x8080000000)
+#define PLAT_ARM_DRAM2_SIZE ULL(0x180000000)
+
+/*******************************************************************************
+ * Console config
+ ******************************************************************************/
+
+#define PLAT_ARM_BOOT_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_BOOT_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_RUN_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_RUN_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+#define PLAT_ARM_CRASH_UART_BASE SOC_CSS_SEC_UART_BASE
+#define PLAT_ARM_CRASH_UART_CLK_IN_HZ SOC_CSS_UART_CLK_IN_HZ
+
+/*******************************************************************************
+ * Flash config
+ ******************************************************************************/
+
+#define PLAT_ARM_MEM_PROT_ADDR (V2M_FLASH0_BASE + \
+ V2M_FLASH0_SIZE - V2M_FLASH_BLOCK_SIZE)
+
+/*******************************************************************************
+ * SCMI config
+ ******************************************************************************/
+
+/* Number of SCMI channels on the platform */
+#define PLAT_ARM_SCMI_CHANNEL_COUNT NRD_CHIP_COUNT
+
+/*******************************************************************************
+ * SDS config
+ ******************************************************************************/
+
+/* Index of SDS region used in the communication with SCP */
+#define SDS_SCP_AP_REGION_ID U(0)
+/* SDS ID for unusable CPU MPID list structure */
+#define SDS_ISOLATED_CPU_LIST_ID U(128)
+
+/*******************************************************************************
+ * GIC config
+ ******************************************************************************/
+
+#define PLAT_ARM_NSTIMER_FRAME_ID (0)
+#define PLAT_ARM_G1S_IRQ_PROPS(grp) CSS_G1S_IRQ_PROPS(grp)
+#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)
+#define PLAT_SP_PRI (0x10)
+
+#endif /* NRD_PLAT_ARM_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
new file mode 100644
index 0000000..c96c1f3
--- /dev/null
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_ros_fw_def1.h
@@ -0,0 +1,49 @@
+/*
+ * Copyright (c) 2024, Arm Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ * This file is limited to include the RoS firmware specific definitions for the
+ * first generation platforms based on the A75, N1 and V1 CPUs. RoS (Rest Of
+ * System) is used to refer to the part of the reference design platform that
+ * excludes CSS.
+ */
+
+#ifndef NRD_ROS_FW_DEF1_H
+#define NRD_ROS_FW_DEF1_H
+
+/*******************************************************************************
+ * MMU mapping
+ ******************************************************************************/
+
+#define PLAT_ARM_SECURE_MAP_DEVICE \
+ MAP_REGION_FLAT( \
+ SOC_CSS_DEVICE_BASE, \
+ SOC_CSS_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE | MT_USER)
+
+#define SOC_CSS_MAP_DEVICE_REMOTE_CHIP(n) \
+ MAP_REGION_FLAT( \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + \
+ SOC_CSS_DEVICE_BASE, \
+ SOC_CSS_DEVICE_SIZE, \
+ MT_DEVICE | MT_RW | MT_SECURE)
+
+/*******************************************************************************
+ * TZ config
+ ******************************************************************************/
+
+/*
+ * Mapping definition of the TrustZone Controller for Arm Neoverse RD platforms
+ * where both the DRAM regions are marked for non-secure access. This applies
+ * to multi-chip platforms.
+ */
+#define NRD_PLAT_TZC_NS_REMOTE_REGIONS_DEF(n) \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM1_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}, \
+ {NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_BASE, \
+ NRD_REMOTE_CHIP_MEM_OFFSET(n) + ARM_DRAM2_END, \
+ ARM_TZC_NS_DRAM_S_ACCESS, PLAT_ARM_TZC_NS_DEV_ACCESS}
+
+#endif /* NRD_ROS_FW_DEF1_H */
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_soc_platform_def.h b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_soc_platform_def.h
index 0024e49..bacda87 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_soc_platform_def.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd1/nrd_soc_platform_def.h
@@ -10,7 +10,6 @@
#include <plat/arm/board/common/v2m_def.h>
#include <plat/arm/soc/common/soc_css_def.h>
-#include <nrd_base_platform_def.h>
#include <nrd_soc_css_def.h>
/* Map the System registers to access from S-EL0 */
diff --git a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
index 83590eb..4f80b22 100644
--- a/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdn1edge/include/platform_def.h
@@ -8,10 +8,16 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
#include <nrd_sdei.h>
#include <nrd_soc_platform_def.h>
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
+
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define NRD_MAX_CPUS_PER_CLUSTER U(4)
#define NRD_MAX_PE_PER_CPU U(1)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
index f889561..fb8574b 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1/include/platform_def.h
@@ -7,9 +7,15 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
+#include <nrd_soc_platform_def.h>
#include <lib/utils_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
-#include <nrd_soc_platform_def.h>
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(16)
#define NRD_MAX_CPUS_PER_CLUSTER U(1)
diff --git a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
index 3e7c9b5..fb498cb 100644
--- a/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdv1mc/include/platform_def.h
@@ -7,8 +7,15 @@
#ifndef PLATFORM_DEF_H
#define PLATFORM_DEF_H
-#include <lib/utils_def.h>
#include <nrd_soc_platform_def.h>
+#include <lib/utils_def.h>
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
+
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
#define PLAT_ARM_CLUSTER_COUNT U(4)
#define NRD_MAX_CPUS_PER_CLUSTER U(1)
diff --git a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
index 9658ee1..9a4d313 100644
--- a/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/sgi575/include/platform_def.h
@@ -8,10 +8,16 @@
#define PLATFORM_DEF_H
#include <lib/utils_def.h>
-
+#include <nrd_css_fw_def1.h>
+#include <nrd_plat_arm_def1.h>
+#include <nrd_ros_fw_def1.h>
#include <nrd_sdei.h>
#include <nrd_soc_platform_def.h>
+/* Remote chip address offset */
+#define NRD_REMOTE_CHIP_MEM_OFFSET(n) \
+ ((ULL(1) << NRD_ADDR_BITS_PER_CHIP) * (n))
+
#define PLAT_ARM_CLUSTER_COUNT U(2)
#define NRD_MAX_CPUS_PER_CLUSTER U(4)
#define NRD_MAX_PE_PER_CPU U(1)