feat(rdfremont): add support for RD-Fremont-Cfg2
Add board support for RD-Fremont-Cfg2 platform, which is a quad chip
variant of RD-Fremont. Each chip has reduced core count of four CPUs as
compared to single chip RD-Fremont platform.
Signed-off-by: Pranav Madhu <pranav.madhu@arm.com>
Signed-off-by: Rohit Mathew <rohit.mathew@arm.com>
Change-Id: I9b79f0eef210afecaa15e381414479027617e44a
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
index 4337fcc..3691961 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd3/nrd_plat_arm_def3.h
@@ -589,7 +589,11 @@
*/
/* Number of DRAM banks */
+#if (NRD_PLATFORM_VARIANT == 2)
+#define ARM_DRAM_NUM_BANKS U(8)
+#else
#define ARM_DRAM_NUM_BANKS U(2)
+#endif
/*******************************************************************************
* DRAM bank1 specific defines.
diff --git a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
index cd29b3b..391c68c 100644
--- a/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
+++ b/plat/arm/board/neoverse_rd/common/include/nrd_variant.h
@@ -34,6 +34,7 @@
/* SID Version values for RD-Fremont variants */
#define RD_FREMONT_CFG1_SID_VER_PART_NUM 0x07F9
+#define RD_FREMONT_CFG2_SID_VER_PART_NUM 0x07EE
/* Structure containing Neoverse RD platform variant information */
typedef struct nrd_platform_info {
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
index c319e17..061f081 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/include/platform_def.h
@@ -20,6 +20,8 @@
/* PE-Cluster count */
#if (NRD_PLATFORM_VARIANT == 1)
#define PLAT_ARM_CLUSTER_COUNT U(8)
+#elif (NRD_PLATFORM_VARIANT == 2)
+#define PLAT_ARM_CLUSTER_COUNT U(4)
#else
#define PLAT_ARM_CLUSTER_COUNT U(16)
#endif
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
index 87e1633..ef2fc29 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/platform.mk
@@ -3,13 +3,19 @@
# SPDX-License-Identifier: BSD-3-Clause
#
-RD_FREMONT_VARIANTS := 0 1
+RD_FREMONT_VARIANTS := 0 1 2
ifneq ($(NRD_PLATFORM_VARIANT), \
$(filter $(NRD_PLATFORM_VARIANT),$(RD_FREMONT_VARIANTS)))
- $(error "NRD_PLATFORM_VARIANT for RD-FREMONT should be 0 or 1,"
+ $(error "NRD_PLATFORM_VARIANT for RD-FREMONT should be 0, 1, or 2,"
"currently set to ${NRD_PLATFORM_VARIANT}.")
endif
+$(eval $(call CREATE_SEQ,SEQ,4))
+ifneq ($(NRD_CHIP_COUNT),$(filter $(NRD_CHIP_COUNT),$(SEQ)))
+ $(error "Chip count for RD-Fremont-MC should be either $(SEQ) \
+ currently it is set to ${NRD_CHIP_COUNT}.")
+endif
+
# Build options
# Major and Minor versions
override ARM_ARCH_MAJOR := 8
@@ -27,6 +33,11 @@
# RD-Fremont platform uses GIC-700 which is based on GICv4.1
GIC_ENABLE_V4_EXTN := 1
+# Enable GIC multichip extension only for multichip platforms
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+GICV3_IMPL_GIC600_MULTICHIP := 1
+endif
+
include plat/arm/board/neoverse_rd/common/nrd-common.mk
RDFREMONT_BASE = plat/arm/board/neoverse_rd/platform/rdfremont
@@ -63,6 +74,9 @@
drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/common/arm_nor_psci_mem_protect.c
+ifeq (${NRD_PLATFORM_VARIANT}, 2)
+BL31_SOURCES += drivers/arm/gic/v3/gic600_multichip.c
+endif
# XLAT options for RD-Fremont variants
BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
index c9d7cd1..a121061 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_bl31_setup.c
@@ -5,12 +5,107 @@
*/
#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <nrd_plat.h>
+#include <nrd_variant.h>
+#if (NRD_PLATFORM_VARIANT == 2)
+static const mmap_region_t rdfremontmc_dynamic_mmap[] = {
+#if NRD_CHIP_COUNT > 1
+ NRD_CSS_SHARED_RAM_MMAP(1),
+ NRD_CSS_PERIPH_MMAP(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ NRD_CSS_SHARED_RAM_MMAP(2),
+ NRD_CSS_PERIPH_MMAP(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ NRD_CSS_SHARED_RAM_MMAP(3),
+ NRD_CSS_PERIPH_MMAP(3),
+#endif
+};
+
+static struct gic600_multichip_data rdfremontmc_multichip_data __init = {
+ .rt_owner_base = PLAT_ARM_GICD_BASE,
+ .rt_owner = 0,
+ .chip_count = NRD_CHIP_COUNT,
+ .chip_addrs = {
+ PLAT_ARM_GICD_BASE >> 16,
+#if NRD_CHIP_COUNT > 1
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 2
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2)) >> 16,
+#endif
+#if NRD_CHIP_COUNT > 3
+ (PLAT_ARM_GICD_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3)) >> 16,
+#endif
+ },
+ .spi_ids = {
+ {PLAT_ARM_GICD_BASE, 32, 511},
+#if NRD_CHIP_COUNT > 1
+ {PLAT_ARM_GICD_BASE, 512, 991},
+#endif
+#if NRD_CHIP_COUNT > 2
+ {PLAT_ARM_GICD_BASE, 4096, 4575},
+#endif
+#if NRD_CHIP_COUNT > 3
+ {PLAT_ARM_GICD_BASE, 4576, 5055},
+#endif
+ }
+};
+
+static uintptr_t rdfremontmc_multichip_gicr_frames[] = {
+ /* Chip 0's GICR Base */
+ PLAT_ARM_GICR_BASE,
+#if NRD_CHIP_COUNT > 1
+ /* Chip 1's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(1),
+#endif
+#if NRD_CHIP_COUNT > 2
+ /* Chip 2's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(2),
+#endif
+#if NRD_CHIP_COUNT > 3
+ /* Chip 3's GICR BASE */
+ PLAT_ARM_GICR_BASE + NRD_REMOTE_CHIP_MEM_OFFSET(3),
+#endif
+ UL(0) /* Zero Termination */
+};
+#endif /* NRD_PLATFORM_VARIANT == 2 */
void bl31_platform_setup(void)
{
+#if (NRD_PLATFORM_VARIANT == 2)
+ int ret;
+ unsigned int i;
+
+ if (plat_arm_nrd_get_multi_chip_mode() == 0) {
+ ERROR("Chip Count is %u but multi-chip mode is not enabled\n",
+ NRD_CHIP_COUNT);
+ panic();
+ } else {
+ INFO("Enabling multi-chip support for RD-Fremont variant\n");
+
+ for (i = 0; i < ARRAY_SIZE(rdfremontmc_dynamic_mmap); i++) {
+ ret = mmap_add_dynamic_region(
+ rdfremontmc_dynamic_mmap[i].base_pa,
+ rdfremontmc_dynamic_mmap[i].base_va,
+ rdfremontmc_dynamic_mmap[i].size,
+ rdfremontmc_dynamic_mmap[i].attr);
+ if (ret != 0) {
+ ERROR("Failed to add entry i: %d (ret=%d)\n",
+ i, ret);
+ panic();
+ }
+ }
+
+ plat_arm_override_gicr_frames(
+ rdfremontmc_multichip_gicr_frames);
+ gic600_multichip_init(&rdfremontmc_multichip_data);
+ }
+#endif /* NRD_PLATFORM_VARIANT == 2 */
nrd_bl31_common_platform_setup();
}
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
index 8393060..5551d98 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_common.c
@@ -5,6 +5,7 @@
*/
#include <common/debug.h>
+#include <drivers/arm/gic600_multichip.h>
#include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h>
#include <platform_def.h>
diff --git a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
index f5ce075..e7931d4 100644
--- a/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
+++ b/plat/arm/board/neoverse_rd/platform/rdfremont/rdfremont_topology.c
@@ -11,20 +11,27 @@
* The power domain tree descriptor.
******************************************************************************/
const unsigned char rd_fremont_pd_tree_desc[] = {
- (PLAT_ARM_CLUSTER_COUNT),
+ (PLAT_ARM_CLUSTER_COUNT) * (NRD_CHIP_COUNT),
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
+#if (PLAT_ARM_CLUSTER_COUNT > 4 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 1))
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
-#if (NRD_PLATFORM_VARIANT == 0)
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 8 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 2))
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
+#endif
+#if (PLAT_ARM_CLUSTER_COUNT > 12 || \
+ (NRD_PLATFORM_VARIANT == 2 && NRD_CHIP_COUNT > 3))
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
NRD_MAX_CPUS_PER_CLUSTER,
@@ -44,11 +51,37 @@
* The array mapping platform core position (implemented by plat_my_core_pos())
* to the SCMI power domain ID implemented by SCP.
******************************************************************************/
+#if (NRD_PLATFORM_VARIANT == 2)
const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
+#if (NRD_CHIP_COUNT > 1)
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x1) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 2)
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x2) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+#if (NRD_CHIP_COUNT > 3)
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x3) | SET_SCMI_DOMAIN_ID(0x3)),
+#endif
+};
+#else
+const uint32_t plat_css_core_pos_to_scmi_dmn_id_map[] = {
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x0)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x1)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x2)),
+ (SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x3)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x4)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x5)),
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0x6)),
@@ -64,3 +97,4 @@
(SET_SCMI_CHANNEL_ID(0x0) | SET_SCMI_DOMAIN_ID(0xF)),
#endif
};
+#endif