feat(gicv5): add a barebones GICv5 driver
This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.
Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.
Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..e228495 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,8 @@
#define INTR_TYPE_S_EL1 U(0)
#define INTR_TYPE_EL3 U(1)
#define INTR_TYPE_NS U(2)
-#define MAX_INTR_TYPES U(3)
+#define INTR_TYPE_RL U(3)
+#define MAX_INTR_TYPES U(4)
#define INTR_TYPE_INVAL MAX_INTR_TYPES
/* Interrupt routing modes */