feat(gicv5): add a barebones GICv5 driver
This is the absolute minimum that's needed to compile an NS-only build
end exit out of EL3. The GIC is not used and/or configured in any way
but all the necessary hooks are populated.
Notably, SCR_EL3.FIQ becomes RES1 as GICv5 behaves in a similar manner
to a GICv3 with FIQ set.
Change-Id: Idae52b9df97f4ca2996b2dcd1e5efc45478a43f2
Co-developed-by: Achin Gupta <achin.gupta@arm.com>
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
diff --git a/include/arch/aarch64/arch.h b/include/arch/aarch64/arch.h
index 5475c7a..5f68b27 100644
--- a/include/arch/aarch64/arch.h
+++ b/include/arch/aarch64/arch.h
@@ -625,7 +625,11 @@
#define CPACR_EL1_SMEN_MASK ULL(0x3)
/* SCR definitions */
+#if ENABLE_FEAT_GCIE
+#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5) | SCR_FIQ_BIT)
+#else
#define SCR_RES1_BITS ((U(1) << 4) | (U(1) << 5))
+#endif
#define SCR_NSE_SHIFT U(62)
#define SCR_FGTEN2_BIT (UL(1) << 59)
#define SCR_NSE_BIT (ULL(1) << SCR_NSE_SHIFT)
diff --git a/include/bl31/interrupt_mgmt.h b/include/bl31/interrupt_mgmt.h
index 8b9dfb6..e228495 100644
--- a/include/bl31/interrupt_mgmt.h
+++ b/include/bl31/interrupt_mgmt.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2024, Arm Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@@ -16,7 +16,8 @@
#define INTR_TYPE_S_EL1 U(0)
#define INTR_TYPE_EL3 U(1)
#define INTR_TYPE_NS U(2)
-#define MAX_INTR_TYPES U(3)
+#define INTR_TYPE_RL U(3)
+#define MAX_INTR_TYPES U(4)
#define INTR_TYPE_INVAL MAX_INTR_TYPES
/* Interrupt routing modes */
diff --git a/include/drivers/arm/gicv5.h b/include/drivers/arm/gicv5.h
index e167845..ff3c61c 100644
--- a/include/drivers/arm/gicv5.h
+++ b/include/drivers/arm/gicv5.h
@@ -6,4 +6,33 @@
#ifndef GICV5_H
#define GICV5_H
+
+#ifndef __ASSEMBLER__
+#include <stdbool.h>
+#include <stdint.h>
+#endif
+
+#include <lib/utils_def.h>
+
+/* Interrupt Domain definitions */
+#define INTDMN_S 0
+#define INTDMN_NS 1
+#define INTDMN_EL3 2
+#define INTDMN_RL 3
+
+/* Trigger modes */
+#define TM_EDGE 0
+#define TM_LEVEL 1
+
+#ifndef __ASSEMBLER__
+
+struct gicv5_driver_data {
+};
+
+extern const struct gicv5_driver_data plat_gicv5_driver_data;
+
+void gicv5_driver_init();
+uint8_t gicv5_get_pending_interrupt_type(void);
+bool gicv5_has_interrupt_type(unsigned int type);
+#endif /* __ASSEMBLER__ */
#endif /* GICV5_H */