diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S
index 43d0ed4..fd53ed8 100644
--- a/bl31/bl31.ld.S
+++ b/bl31/bl31.ld.S
@@ -66,11 +66,11 @@
         __CPU_OPS_END__ = .;
 
         /*
-         * Keep the .got section in the RO section as the it is patched
+         * Keep the .got section in the RO section as it is patched
          * prior to enabling the MMU and having the .got in RO is better for
-         * security.
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
          */
-        . = ALIGN(16);
+        . = ALIGN(8);
         __GOT_START__ = .;
         *(.got)
         __GOT_END__ = .;
@@ -112,6 +112,16 @@
         KEEP(*(cpu_ops))
         __CPU_OPS_END__ = .;
 
+        /*
+         * Keep the .got section in the RO section as it is patched
+         * prior to enabling the MMU and having the .got in RO is better for
+         * security. GOT is a table of addresses so ensure 8-byte alignment.
+         */
+        . = ALIGN(8);
+        __GOT_START__ = .;
+        *(.got)
+        __GOT_END__ = .;
+
         /* Place pubsub sections for events */
         . = ALIGN(8);
 #include <pubsub_events.h>
@@ -165,11 +175,12 @@
         __DATA_END__ = .;
     } >RAM
 
-    . = ALIGN(16);
     /*
      * .rela.dyn needs to come after .data for the read-elf utility to parse
-     * this section correctly.
+     * this section correctly. Ensure 8-byte alignment so that the fields of
+     * RELA data structure are aligned.
      */
+    . = ALIGN(8);
     __RELA_START__ = .;
     .rela.dyn . : {
     } >RAM
diff --git a/docs/marvell/build.txt b/docs/marvell/build.txt
index 0682b77..a00dbb5 100644
--- a/docs/marvell/build.txt
+++ b/docs/marvell/build.txt
@@ -167,7 +167,7 @@
 
 (1) ARM cross compiler capable of building images for the service CPU (CM3).
     This component is usually included in the Linux host packages.
-    On Debian/Uboot hosts the default GNU ARM tool chain can be installed
+    On Debian/Ubuntu hosts the default GNU ARM tool chain can be installed
     using the following command::
 
 		> sudo apt-get install gcc-arm-linux-gnueabi
diff --git a/docs/user-guide.rst b/docs/user-guide.rst
index a8bd40c..103f1c7 100644
--- a/docs/user-guide.rst
+++ b/docs/user-guide.rst
@@ -1875,16 +1875,16 @@
     -C cluster0.NUM_CORES=4                                      \
     -C cluster1.NUM_CORES=4                                      \
     -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBAR=0x04020000                            \
-    -C cluster0.cpu1.RVBAR=0x04020000                            \
-    -C cluster0.cpu2.RVBAR=0x04020000                            \
-    -C cluster0.cpu3.RVBAR=0x04020000                            \
-    -C cluster1.cpu0.RVBAR=0x04020000                            \
-    -C cluster1.cpu1.RVBAR=0x04020000                            \
-    -C cluster1.cpu2.RVBAR=0x04020000                            \
-    -C cluster1.cpu3.RVBAR=0x04020000                            \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000    \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000    \
+    -C cluster0.cpu0.RVBAR=0x04010000                            \
+    -C cluster0.cpu1.RVBAR=0x04010000                            \
+    -C cluster0.cpu2.RVBAR=0x04010000                            \
+    -C cluster0.cpu3.RVBAR=0x04010000                            \
+    -C cluster1.cpu0.RVBAR=0x04010000                            \
+    -C cluster1.cpu1.RVBAR=0x04010000                            \
+    -C cluster1.cpu2.RVBAR=0x04010000                            \
+    -C cluster1.cpu3.RVBAR=0x04010000                            \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
     --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
@@ -1892,6 +1892,9 @@
 
 Notes:
 
+-  Since Position Independent Executable (PIE) support is enabled for BL31
+   in this config, it can be loaded at any valid address for execution.
+
 -  Since a FIP is not loaded when using BL31 as reset entrypoint, the
    ``--data="<path-to><bl31|bl32|bl33-binary>"@<base-address-of-binary>``
    parameter is needed to load the individual bootloader images in memory.
@@ -1932,14 +1935,14 @@
     -C cluster1.cpu1.CONFIG64=0                                  \
     -C cluster1.cpu2.CONFIG64=0                                  \
     -C cluster1.cpu3.CONFIG64=0                                  \
-    -C cluster0.cpu0.RVBAR=0x04001000                            \
-    -C cluster0.cpu1.RVBAR=0x04001000                            \
-    -C cluster0.cpu2.RVBAR=0x04001000                            \
-    -C cluster0.cpu3.RVBAR=0x04001000                            \
-    -C cluster1.cpu0.RVBAR=0x04001000                            \
-    -C cluster1.cpu1.RVBAR=0x04001000                            \
-    -C cluster1.cpu2.RVBAR=0x04001000                            \
-    -C cluster1.cpu3.RVBAR=0x04001000                            \
+    -C cluster0.cpu0.RVBAR=0x04002000                            \
+    -C cluster0.cpu1.RVBAR=0x04002000                            \
+    -C cluster0.cpu2.RVBAR=0x04002000                            \
+    -C cluster0.cpu3.RVBAR=0x04002000                            \
+    -C cluster1.cpu0.RVBAR=0x04002000                            \
+    -C cluster1.cpu1.RVBAR=0x04002000                            \
+    -C cluster1.cpu2.RVBAR=0x04002000                            \
+    -C cluster1.cpu3.RVBAR=0x04002000                            \
     --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000    \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
@@ -1962,16 +1965,16 @@
     -C bp.secure_memory=1                                        \
     -C bp.tzc_400.diagnostics=1                                  \
     -C cache_state_modelled=1                                    \
-    -C cluster0.cpu0.RVBARADDR=0x04020000                        \
-    -C cluster0.cpu1.RVBARADDR=0x04020000                        \
-    -C cluster0.cpu2.RVBARADDR=0x04020000                        \
-    -C cluster0.cpu3.RVBARADDR=0x04020000                        \
-    -C cluster1.cpu0.RVBARADDR=0x04020000                        \
-    -C cluster1.cpu1.RVBARADDR=0x04020000                        \
-    -C cluster1.cpu2.RVBARADDR=0x04020000                        \
-    -C cluster1.cpu3.RVBARADDR=0x04020000                        \
-    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000    \
-    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000    \
+    -C cluster0.cpu0.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu1.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu2.RVBARADDR=0x04010000                        \
+    -C cluster0.cpu3.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu0.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu1.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu2.RVBARADDR=0x04010000                        \
+    -C cluster1.cpu3.RVBARADDR=0x04010000                        \
+    --data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04010000    \
+    --data cluster0.cpu0="<path-to>/<bl32-binary>"@0xff000000    \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000    \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000            \
     --data cluster0.cpu0="<path-to>/<kernel-binary>"@0x80080000  \
@@ -1990,10 +1993,10 @@
     -C bp.secure_memory=1                                       \
     -C bp.tzc_400.diagnostics=1                                 \
     -C cache_state_modelled=1                                   \
-    -C cluster0.cpu0.RVBARADDR=0x04001000                       \
-    -C cluster0.cpu1.RVBARADDR=0x04001000                       \
-    -C cluster0.cpu2.RVBARADDR=0x04001000                       \
-    -C cluster0.cpu3.RVBARADDR=0x04001000                       \
+    -C cluster0.cpu0.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu1.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu2.RVBARADDR=0x04002000                       \
+    -C cluster0.cpu3.RVBARADDR=0x04002000                       \
     --data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04002000   \
     --data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000   \
     --data cluster0.cpu0="<path-to>/<fdt>"@0x82000000           \
diff --git a/include/drivers/arm/gic_common.h b/include/drivers/arm/gic_common.h
index 2f5334f..a9ec7b7 100644
--- a/include/drivers/arm/gic_common.h
+++ b/include/drivers/arm/gic_common.h
@@ -35,11 +35,9 @@
 #define GIC_INTR_CFG_LEVEL		(0 << 1)
 #define GIC_INTR_CFG_EDGE		(1 << 1)
 
-/* Constants to categorise priorities */
+/* Highest possible interrupt priorities */
 #define GIC_HIGHEST_SEC_PRIORITY	U(0x00)
-#define GIC_LOWEST_SEC_PRIORITY		U(0x7f)
 #define GIC_HIGHEST_NS_PRIORITY		U(0x80)
-#define GIC_LOWEST_NS_PRIORITY		U(0xfe) /* 0xff would disable all interrupts */
 
 /*******************************************************************************
  * GIC Distributor interface register offsets that are common to GICv3 & GICv2
diff --git a/include/plat/arm/common/arm_def.h b/include/plat/arm/common/arm_def.h
index cbac247..c5c10ab 100644
--- a/include/plat/arm/common/arm_def.h
+++ b/include/plat/arm/common/arm_def.h
@@ -407,12 +407,16 @@
 #define BL31_LIMIT			(ARM_AP_TZC_DRAM1_BASE +	\
 						PLAT_ARM_MAX_BL31_SIZE)
 #elif (RESET_TO_BL31)
+/* Ensure Position Independent support (PIE) is enabled for this config.*/
+# if !ENABLE_PIE
+#  error "BL31 must be a PIE if RESET_TO_BL31=1."
+# endif
 /*
- * Put BL31_BASE in the middle of the Trusted SRAM.
+ * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely
+ * used for building BL31 when RESET_TO_BL31=1.
  */
-#define BL31_BASE			(ARM_TRUSTED_SRAM_BASE + \
-						(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
-#define BL31_LIMIT			(ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
+#define BL31_BASE			0x0
+#define BL31_LIMIT			PLAT_ARM_MAX_BL31_SIZE
 #else
 /* Put BL31 below BL2 in the Trusted SRAM.*/
 #define BL31_BASE			((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\