Tegra194: memctrl: Disable PVARDC coalescer
Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.
Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
diff --git a/plat/nvidia/tegra/soc/t194/plat_memctrl.c b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
index 07c05c8..0f80922 100644
--- a/plat/nvidia/tegra/soc/t194/plat_memctrl.c
+++ b/plat/nvidia/tegra/soc/t194/plat_memctrl.c
@@ -618,6 +618,15 @@
reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
+
+ /*
+ * WAR to hardware bug 1953865: Coalescer must be disabled
+ * for PVA0RDC and PVA1RDC interfaces.
+ */
+ reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0);
+ reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED |
+ MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED);
+ tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val);
}
/*******************************************************************************