commit 917a00cf80ab3138625b7d3eaddd1314c43f2576
author Yann Gautier <yann.gautier@st.com> Tue Apr 16 16:20:58 2019 +0200
committer Yann Gautier <yann.gautier@st.com> Mon Sep 02 17:52:29 2019 +0200
tree f1bbdef802e6cf52e25265cd19fd6aa30aa35ed2
parent f540a599bcc84b6863351d6e8a7030aa1eb281b1

stm32mp1: add support for LpDDR3

This change enables LpDDR3 initialization with PMIC.

Change-Id: I2409a808335dfacd69a8517cb8510cee98bb8161
Signed-off-by: Yann Gautier <yann.gautier@st.com>

drivers/st/ddr/stm32mp1_ddr.c

diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c
index caf8eef..7d89d02 100644
--- a/drivers/st/ddr/stm32mp1_ddr.c
+++ b/drivers/st/ddr/stm32mp1_ddr.c
@@ -717,6 +717,8 @@
 		ret = board_ddr_power_init(STM32MP_DDR3);
 	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR2) != 0U) {
 		ret = board_ddr_power_init(STM32MP_LPDDR2);
+	} else if ((config->c_reg.mstr & DDRCTRL_MSTR_LPDDR3) != 0U) {
+		ret = board_ddr_power_init(STM32MP_LPDDR3);
 	} else {
 		ERROR("DDR type not supported\n");
 	}

drivers/st/pmic/stm32mp_pmic.c

diff --git a/drivers/st/pmic/stm32mp_pmic.c b/drivers/st/pmic/stm32mp_pmic.c
index 6fe51f4..9e9dddc 100644
--- a/drivers/st/pmic/stm32mp_pmic.c
+++ b/drivers/st/pmic/stm32mp_pmic.c
@@ -299,6 +299,7 @@
 		break;
 
 	case STM32MP_LPDDR2:
+	case STM32MP_LPDDR3:
 		/*
 		 * Set LDO3 to 1.8V
 		 * Set LDO3 to bypass mode if BUCK3 = 1.8V

plat/st/stm32mp1/stm32mp1_def.h

diff --git a/plat/st/stm32mp1/stm32mp1_def.h b/plat/st/stm32mp1/stm32mp1_def.h
index 77a95e6..0eba8a6 100644
--- a/plat/st/stm32mp1/stm32mp1_def.h
+++ b/plat/st/stm32mp1/stm32mp1_def.h
@@ -66,6 +66,7 @@
 enum ddr_type {
 	STM32MP_DDR3,
 	STM32MP_LPDDR2,
+	STM32MP_LPDDR3
 };
 #endif