tree 3564d74ce7775b5cc6e0b14ef7e788747d82be67
parent b9ae59fdc112e6def9536e0510ed8d476173dbb7
author Michal Simek <michal.simek@amd.com> 1661957114 +0200
committer Michal Simek <michal.simek@amd.com> 1663658383 +0200

feat(versal-net): add support for Xilinx Versal NET platform

New SoC is a78 based with gicv3 and uart over pl011. Communication
interfaces are similar to Versal platform. System starts with Xilinx PLM
firmware which loads TF-A(bl31) to DDR, which is already configured, and
jumps to it. PLM also prepare handoff structure for TF-A with information
what components were load and flags which indicate which EL level SW should
be started.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: Akshay Belsare <Akshay.Belsare@amd.com>
Change-Id: I2a16c242a77be6c91be3d198727dc3b9bbb97410