mediatek: mt8195: Add gpio driver
Add gpio driver.
Change-Id: I6ff6875c35294f56f2d8298d75cd18c230aad211
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.c b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
new file mode 100644
index 0000000..89977a5
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.c
@@ -0,0 +1,298 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <drivers/gpio.h>
+#include <lib/mmio.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+/******************************************************************************
+ *Macro Definition
+ ******************************************************************************/
+#define GPIO_MODE_BITS 4
+#define MAX_GPIO_MODE_PER_REG 8
+#define MAX_GPIO_REG_BITS 32
+#define DIR_BASE (GPIO_BASE + 0x000)
+#define DOUT_BASE (GPIO_BASE + 0x100)
+#define DIN_BASE (GPIO_BASE + 0x200)
+#define MODE_BASE (GPIO_BASE + 0x300)
+#define SET 0x4
+#define CLR 0x8
+
+static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(dir < MT_GPIO_DIR_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (dir == MT_GPIO_DIR_IN) {
+ mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_dir_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIR_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
+}
+
+static void mt_set_gpio_out_chip(uint32_t pin, int output)
+{
+ uint32_t pos, bit;
+
+ assert(pin < MAX_GPIO_PIN);
+ assert(output < MT_GPIO_OUT_MAX);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ if (output == MT_GPIO_OUT_ZERO) {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
+ } else {
+ mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
+ }
+}
+
+static int mt_get_gpio_in_chip(uint32_t pin)
+{
+ uint32_t pos, bit;
+ uint32_t reg;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ pos = pin / MAX_GPIO_REG_BITS;
+ bit = pin % MAX_GPIO_REG_BITS;
+
+ reg = mmio_read_32(DIN_BASE + 0x10U * pos);
+ return (((reg & (1U << bit)) != 0U) ? 1 : 0);
+}
+
+static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ mmio_write_32(reg2 + SET, (1U << bit));
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
+ int select)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+
+ if (enable == MT_GPIO_PULL_ENABLE) {
+ if (select == MT_GPIO_PULL_DOWN) {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + SET, (1U << bit));
+ } else {
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ mmio_write_32(reg1 + SET, (1U << bit));
+ }
+ } else {
+ mmio_write_32(reg1 + CLR, (1U << bit));
+ mmio_write_32(reg2 + CLR, (1U << bit));
+ }
+}
+
+static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
+ int select)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ if (gpio_info.flag) {
+ mt_gpio_set_spec_pull_pupd(pin, enable, select);
+ } else {
+ mt_gpio_set_pull_pu_pd(pin, enable, select);
+ }
+}
+
+static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t r0;
+ uint32_t r1;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 + (gpio_info.base & 0xf0);
+
+ r0 = (mmio_read_32(reg2) >> bit) & 1U;
+ r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
+ if (r0 == 0U && r1 == 0U) {
+ return MT_GPIO_PULL_NONE;
+ } else {
+ if (mmio_read_32(reg1) & (1U << bit)) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_UP;
+ }
+ }
+}
+
+static int mt_gpio_get_pull_pu_pd(uint32_t pin)
+{
+ uintptr_t reg1;
+ uintptr_t reg2;
+ uint32_t pu;
+ uint32_t pd;
+
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ uint32_t bit = gpio_info.bit;
+
+ reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
+ reg2 = reg1 - (gpio_info.base & 0xf0);
+ pu = (mmio_read_32(reg1) >> bit) & 1U;
+ pd = (mmio_read_32(reg2) >> bit) & 1U;
+ if (pu == 1U) {
+ return MT_GPIO_PULL_UP;
+ } else if (pd == 1U) {
+ return MT_GPIO_PULL_DOWN;
+ } else {
+ return MT_GPIO_PULL_NONE;
+ }
+}
+
+static int mt_gpio_get_pull_chip(uint32_t pin)
+{
+ struct mt_pin_info gpio_info;
+
+ gpio_info = mt_pin_infos[pin];
+ if (gpio_info.flag) {
+ return mt_gpio_get_spec_pull_pupd(pin);
+ } else {
+ return mt_gpio_get_pull_pu_pd(pin);
+ }
+}
+
+static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ if (sel == MT_GPIO_PULL_NONE) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
+ } else if (sel == MT_GPIO_PULL_UP) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
+ } else if (sel == MT_GPIO_PULL_DOWN) {
+ mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
+ }
+}
+
+/* get pull-up or pull-down, regardless of resistor value */
+static int mt_get_gpio_pull_select_chip(uint32_t pin)
+{
+ assert(pin < MAX_GPIO_PIN);
+
+ return mt_gpio_get_pull_chip(pin);
+}
+
+static void mt_set_gpio_dir(int gpio, int direction)
+{
+ mt_set_gpio_dir_chip((uint32_t)gpio, direction);
+}
+
+static int mt_get_gpio_dir(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_dir_chip(pin);
+}
+
+static void mt_set_gpio_pull(int gpio, int pull)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_pull_select_chip(pin, pull);
+}
+
+static int mt_get_gpio_pull(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_pull_select_chip(pin);
+}
+
+static void mt_set_gpio_out(int gpio, int value)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ mt_set_gpio_out_chip(pin, value);
+}
+
+static int mt_get_gpio_in(int gpio)
+{
+ uint32_t pin;
+
+ pin = (uint32_t)gpio;
+ return mt_get_gpio_in_chip(pin);
+}
+
+const gpio_ops_t mtgpio_ops = {
+ .get_direction = mt_get_gpio_dir,
+ .set_direction = mt_set_gpio_dir,
+ .get_value = mt_get_gpio_in,
+ .set_value = mt_set_gpio_out,
+ .set_pull = mt_set_gpio_pull,
+ .get_pull = mt_get_gpio_pull,
+};
+
+void mt_gpio_init(void)
+{
+ gpio_init(&mtgpio_ops);
+}
diff --git a/plat/mediatek/common/drivers/gpio/mtgpio_common.h b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
new file mode 100644
index 0000000..bf51055
--- /dev/null
+++ b/plat/mediatek/common/drivers/gpio/mtgpio_common.h
@@ -0,0 +1,109 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_COMMON_H
+#define MT_GPIO_COMMON_H
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include <plat/common/common_def.h>
+
+/* Error Code No. */
+#define RSUCCESS 0
+#define ERACCESS 1
+#define ERINVAL 2
+#define ERWRAPPER 3
+#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+
+/* GPIO MODE CONTROL VALUE*/
+typedef enum {
+ GPIO_MODE_UNSUPPORTED = -1,
+ GPIO_MODE_GPIO = 0,
+ GPIO_MODE_00 = 0,
+ GPIO_MODE_01,
+ GPIO_MODE_02,
+ GPIO_MODE_03,
+ GPIO_MODE_04,
+ GPIO_MODE_05,
+ GPIO_MODE_06,
+ GPIO_MODE_07,
+
+ GPIO_MODE_MAX,
+ GPIO_MODE_DEFAULT = GPIO_MODE_00,
+} GPIO_MODE;
+
+/* GPIO DIRECTION */
+typedef enum {
+ MT_GPIO_DIR_UNSUPPORTED = -1,
+ MT_GPIO_DIR_OUT = 0,
+ MT_GPIO_DIR_IN = 1,
+ MT_GPIO_DIR_MAX,
+ MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
+} GPIO_DIR;
+
+/* GPIO PULL ENABLE*/
+typedef enum {
+ MT_GPIO_PULL_EN_UNSUPPORTED = -1,
+ MT_GPIO_PULL_DISABLE = 0,
+ MT_GPIO_PULL_ENABLE = 1,
+ MT_GPIO_PULL_ENABLE_R0 = 2,
+ MT_GPIO_PULL_ENABLE_R1 = 3,
+ MT_GPIO_PULL_ENABLE_R0R1 = 4,
+
+ MT_GPIO_PULL_EN_MAX,
+ MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
+} GPIO_PULL_EN;
+
+/* GPIO PULL-UP/PULL-DOWN*/
+typedef enum {
+ MT_GPIO_PULL_UNSUPPORTED = -1,
+ MT_GPIO_PULL_NONE = 0,
+ MT_GPIO_PULL_UP = 1,
+ MT_GPIO_PULL_DOWN = 2,
+ MT_GPIO_PULL_MAX,
+ MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
+} GPIO_PULL;
+
+/* GPIO OUTPUT */
+typedef enum {
+ MT_GPIO_OUT_UNSUPPORTED = -1,
+ MT_GPIO_OUT_ZERO = 0,
+ MT_GPIO_OUT_ONE = 1,
+
+ MT_GPIO_OUT_MAX,
+ MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
+ MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO, /*compatible with DCT*/
+} GPIO_OUT;
+
+/* GPIO INPUT */
+typedef enum {
+ MT_GPIO_IN_UNSUPPORTED = -1,
+ MT_GPIO_IN_ZERO = 0,
+ MT_GPIO_IN_ONE = 1,
+
+ MT_GPIO_IN_MAX,
+} GPIO_IN;
+
+#define PIN(_id, _flag, _bit, _base, _offset) { \
+ .id = _id, \
+ .flag = _flag, \
+ .bit = _bit, \
+ .base = _base, \
+ .offset = _offset, \
+ }
+
+struct mt_pin_info {
+ uint8_t id;
+ uint8_t flag;
+ uint8_t bit;
+ uint16_t base;
+ uint16_t offset;
+};
+
+void mt_gpio_init(void);
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin);
+#endif /* MT_GPIO_COMMON_H */
diff --git a/plat/mediatek/mt8192/bl31_plat_setup.c b/plat/mediatek/mt8192/bl31_plat_setup.c
index 0040747..94ec1b5 100644
--- a/plat/mediatek/mt8192/bl31_plat_setup.c
+++ b/plat/mediatek/mt8192/bl31_plat_setup.c
@@ -98,7 +98,7 @@
mt_gic_driver_init();
mt_gic_init();
- plat_mt8192_gpio_init();
+ mt_gpio_init();
mt_systimer_init();
generic_delay_timer_init();
spm_boot_init();
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
index e07b75a..c78332d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.c
@@ -5,94 +5,17 @@
*/
#include <assert.h>
-#include <common/debug.h>
-#include <drivers/delay_timer.h>
-#include <drivers/gpio.h>
-#include <lib/mmio.h>
#include <mtgpio.h>
#include <platform_def.h>
-/******************************************************************************
- *Macro Definition
- ******************************************************************************/
-#define GPIO_MODE_BITS 4
-#define MAX_GPIO_MODE_PER_REG 8
-#define MAX_GPIO_REG_BITS 32
-#define DIR_BASE (GPIO_BASE + 0x000)
-#define DOUT_BASE (GPIO_BASE + 0x100)
-#define DIN_BASE (GPIO_BASE + 0x200)
-#define MODE_BASE (GPIO_BASE + 0x300)
-#define SET 0x4
-#define CLR 0x8
-
-static void mt_set_gpio_dir_chip(uint32_t pin, int dir)
-{
- uint32_t pos, bit;
-
- assert(pin < MAX_GPIO_PIN);
- assert(dir < MT_GPIO_DIR_MAX);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- if (dir == MT_GPIO_DIR_IN) {
- mmio_write_32(DIR_BASE + 0x10U * pos + CLR, 1U << bit);
- } else {
- mmio_write_32(DIR_BASE + 0x10U * pos + SET, 1U << bit);
- }
-}
-
-static int mt_get_gpio_dir_chip(uint32_t pin)
-{
- uint32_t pos, bit;
- uint32_t reg;
-
- assert(pin < MAX_GPIO_PIN);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- reg = mmio_read_32(DIR_BASE + 0x10U * pos);
- return (((reg & (1U << bit)) != 0U) ? MT_GPIO_DIR_OUT : MT_GPIO_DIR_IN);
-}
-
-static void mt_set_gpio_out_chip(uint32_t pin, int output)
-{
- uint32_t pos, bit;
-
- assert(pin < MAX_GPIO_PIN);
- assert(output < MT_GPIO_OUT_MAX);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- if (output == MT_GPIO_OUT_ZERO) {
- mmio_write_32(DOUT_BASE + 0x10U * pos + CLR, 1U << bit);
- } else {
- mmio_write_32(DOUT_BASE + 0x10U * pos + SET, 1U << bit);
- }
-}
-
-static int mt_get_gpio_in_chip(uint32_t pin)
-{
- uint32_t pos, bit;
- uint32_t reg;
-
- assert(pin < MAX_GPIO_PIN);
-
- pos = pin / MAX_GPIO_REG_BITS;
- bit = pin % MAX_GPIO_REG_BITS;
-
- reg = mmio_read_32(DIN_BASE + 0x10U * pos);
- return (((reg & (1U << bit)) != 0U) ? 1 : 0);
-}
-
-static uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
{
uintptr_t reg_addr = 0U;
struct mt_pin_info gpio_info;
- gpio_info = mt8192_pin_infos[pin];
+ assert(pin < MAX_GPIO_PIN);
+
+ gpio_info = mt_pin_infos[pin];
switch (gpio_info.base & 0x0f) {
case 0:
@@ -128,213 +51,3 @@
return reg_addr;
}
-
-static void mt_gpio_set_spec_pull_pupd(uint32_t pin, int enable,
- int select)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 + (gpio_info.base & 0xf0);
- if (enable == MT_GPIO_PULL_ENABLE) {
- mmio_write_32(reg2 + SET, (1U << bit));
- if (select == MT_GPIO_PULL_DOWN) {
- mmio_write_32(reg1 + SET, (1U << bit));
- } else {
- mmio_write_32(reg1 + CLR, (1U << bit));
- }
- } else {
- mmio_write_32(reg2 + CLR, (1U << bit));
- mmio_write_32((reg2 + 0x010U) + CLR, (1U << bit));
- }
-}
-
-static void mt_gpio_set_pull_pu_pd(uint32_t pin, int enable,
- int select)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 - (gpio_info.base & 0xf0);
-
- if (enable == MT_GPIO_PULL_ENABLE) {
- if (select == MT_GPIO_PULL_DOWN) {
- mmio_write_32(reg1 + CLR, (1U << bit));
- mmio_write_32(reg2 + SET, (1U << bit));
- } else {
- mmio_write_32(reg2 + CLR, (1U << bit));
- mmio_write_32(reg1 + SET, (1U << bit));
- }
- } else {
- mmio_write_32(reg1 + CLR, (1U << bit));
- mmio_write_32(reg2 + CLR, (1U << bit));
- }
-}
-
-static void mt_gpio_set_pull_chip(uint32_t pin, int enable,
- int select)
-{
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- if (gpio_info.flag) {
- mt_gpio_set_spec_pull_pupd(pin, enable, select);
- } else {
- mt_gpio_set_pull_pu_pd(pin, enable, select);
- }
-}
-
-static int mt_gpio_get_spec_pull_pupd(uint32_t pin)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- uint32_t r0;
- uint32_t r1;
-
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 + (gpio_info.base & 0xf0);
-
- r0 = (mmio_read_32(reg2) >> bit) & 1U;
- r1 = (mmio_read_32(reg2 + 0x010) >> bit) & 1U;
- if (r0 == 0U && r1 == 0U) {
- return MT_GPIO_PULL_NONE;
- } else {
- if (mmio_read_32(reg1) & (1U << bit)) {
- return MT_GPIO_PULL_DOWN;
- } else {
- return MT_GPIO_PULL_UP;
- }
- }
-}
-
-static int mt_gpio_get_pull_pu_pd(uint32_t pin)
-{
- uintptr_t reg1;
- uintptr_t reg2;
- uint32_t pu;
- uint32_t pd;
-
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- uint32_t bit = gpio_info.bit;
-
- reg1 = mt_gpio_find_reg_addr(pin) + gpio_info.offset;
- reg2 = reg1 - (gpio_info.base & 0xf0);
- pu = (mmio_read_32(reg1) >> bit) & 1U;
- pd = (mmio_read_32(reg2) >> bit) & 1U;
- if (pu == 1U) {
- return MT_GPIO_PULL_UP;
- } else if (pd == 1U) {
- return MT_GPIO_PULL_DOWN;
- } else {
- return MT_GPIO_PULL_NONE;
- }
-}
-
-static int mt_gpio_get_pull_chip(uint32_t pin)
-{
- struct mt_pin_info gpio_info;
-
- gpio_info = mt8192_pin_infos[pin];
- if (gpio_info.flag) {
- return mt_gpio_get_spec_pull_pupd(pin);
- } else {
- return mt_gpio_get_pull_pu_pd(pin);
- }
-}
-
-static void mt_set_gpio_pull_select_chip(uint32_t pin, int sel)
-{
- assert(pin < MAX_GPIO_PIN);
-
- if (sel == MT_GPIO_PULL_NONE) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_DISABLE, MT_GPIO_PULL_DOWN);
- } else if (sel == MT_GPIO_PULL_UP) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_UP);
- } else if (sel == MT_GPIO_PULL_DOWN) {
- mt_gpio_set_pull_chip(pin, MT_GPIO_PULL_ENABLE, MT_GPIO_PULL_DOWN);
- }
-}
-
-/* get pull-up or pull-down, regardless of resistor value */
-static int mt_get_gpio_pull_select_chip(uint32_t pin)
-{
- assert(pin < MAX_GPIO_PIN);
-
- return mt_gpio_get_pull_chip(pin);
-}
-
-static void mt_set_gpio_dir(int gpio, int direction)
-{
- mt_set_gpio_dir_chip((uint32_t)gpio, direction);
-}
-
-static int mt_get_gpio_dir(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_dir_chip(pin);
-}
-
-static void mt_set_gpio_pull(int gpio, int pull)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- mt_set_gpio_pull_select_chip(pin, pull);
-}
-
-static int mt_get_gpio_pull(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_pull_select_chip(pin);
-}
-
-static void mt_set_gpio_out(int gpio, int value)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- mt_set_gpio_out_chip(pin, value);
-}
-
-static int mt_get_gpio_in(int gpio)
-{
- uint32_t pin;
-
- pin = (uint32_t)gpio;
- return mt_get_gpio_in_chip(pin);
-}
-
-const gpio_ops_t mtgpio_ops = {
- .get_direction = mt_get_gpio_dir,
- .set_direction = mt_set_gpio_dir,
- .get_value = mt_get_gpio_in,
- .set_value = mt_set_gpio_out,
- .set_pull = mt_set_gpio_pull,
- .get_pull = mt_get_gpio_pull,
-};
-
-void plat_mt8192_gpio_init(void)
-{
- gpio_init(&mtgpio_ops);
-}
diff --git a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
index ca0c964..d3aa24d 100644
--- a/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
+++ b/plat/mediatek/mt8192/drivers/gpio/mtgpio.h
@@ -7,17 +7,7 @@
#ifndef MT_GPIO_H
#define MT_GPIO_H
-#include <stdbool.h>
-#include <stdint.h>
-
-#include <plat/common/common_def.h>
-
-/* Error Code No. */
-#define RSUCCESS 0
-#define ERACCESS 1
-#define ERINVAL 2
-#define ERWRAPPER 3
-#define MAX_GPIO_PIN MT_GPIO_BASE_MAX
+#include <mtgpio_common.h>
/* Enumeration for GPIO pin */
typedef enum GPIO_PIN {
@@ -54,110 +44,7 @@
MT_GPIO_BASE_MAX
} GPIO_PIN;
-/* GPIO MODE CONTROL VALUE*/
-typedef enum {
- GPIO_MODE_UNSUPPORTED = -1,
- GPIO_MODE_GPIO = 0,
- GPIO_MODE_00 = 0,
- GPIO_MODE_01,
- GPIO_MODE_02,
- GPIO_MODE_03,
- GPIO_MODE_04,
- GPIO_MODE_05,
- GPIO_MODE_06,
- GPIO_MODE_07,
-
- GPIO_MODE_MAX,
- GPIO_MODE_DEFAULT = GPIO_MODE_00,
-} GPIO_MODE;
-
-/* GPIO DIRECTION */
-typedef enum {
- MT_GPIO_DIR_UNSUPPORTED = -1,
- MT_GPIO_DIR_OUT = 0,
- MT_GPIO_DIR_IN = 1,
- MT_GPIO_DIR_MAX,
- MT_GPIO_DIR_DEFAULT = MT_GPIO_DIR_IN,
-} GPIO_DIR;
-
-/* GPIO PULL ENABLE*/
-typedef enum {
- MT_GPIO_PULL_EN_UNSUPPORTED = -1,
- MT_GPIO_PULL_DISABLE = 0,
- MT_GPIO_PULL_ENABLE = 1,
- MT_GPIO_PULL_ENABLE_R0 = 2,
- MT_GPIO_PULL_ENABLE_R1 = 3,
- MT_GPIO_PULL_ENABLE_R0R1 = 4,
-
- MT_GPIO_PULL_EN_MAX,
- MT_GPIO_PULL_EN_DEFAULT = MT_GPIO_PULL_ENABLE,
-} GPIO_PULL_EN;
-
-/* GPIO PULL-UP/PULL-DOWN*/
-typedef enum {
- MT_GPIO_PULL_UNSUPPORTED = -1,
- MT_GPIO_PULL_NONE = 0,
- MT_GPIO_PULL_UP = 1,
- MT_GPIO_PULL_DOWN = 2,
- MT_GPIO_PULL_MAX,
- MT_GPIO_PULL_DEFAULT = MT_GPIO_PULL_DOWN
-} GPIO_PULL;
-
-/* GPIO OUTPUT */
-typedef enum {
- MT_GPIO_OUT_UNSUPPORTED = -1,
- MT_GPIO_OUT_ZERO = 0,
- MT_GPIO_OUT_ONE = 1,
-
- MT_GPIO_OUT_MAX,
- MT_GPIO_OUT_DEFAULT = MT_GPIO_OUT_ZERO,
- MT_GPIO_DATA_OUT_DEFAULT = MT_GPIO_OUT_ZERO, /*compatible with DCT*/
-} GPIO_OUT;
-
-/* GPIO INPUT */
-typedef enum {
- MT_GPIO_IN_UNSUPPORTED = -1,
- MT_GPIO_IN_ZERO = 0,
- MT_GPIO_IN_ONE = 1,
-
- MT_GPIO_IN_MAX,
-} GPIO_IN;
-
-typedef struct {
- uint32_t val;
- uint32_t set;
- uint32_t rst;
- uint32_t _align1;
-} VAL_REGS;
-
-typedef struct {
- VAL_REGS dir[7];
- uint8_t rsv00[144];
- VAL_REGS dout[7];
- uint8_t rsv01[144];
- VAL_REGS din[7];
- uint8_t rsv02[144];
- VAL_REGS mode[28];
-} GPIO_REGS;
-
-
-#define PIN(_id, _flag, _bit, _base, _offset) { \
- .id = _id, \
- .flag = _flag, \
- .bit = _bit, \
- .base = _base, \
- .offset = _offset, \
- }
-
-struct mt_pin_info {
- uint8_t id;
- uint8_t flag;
- uint8_t bit;
- uint16_t base;
- uint16_t offset;
-};
-
-static const struct mt_pin_info mt8192_pin_infos[] = {
+static const struct mt_pin_info mt_pin_infos[] = {
PIN(0, 0, 9, 0x23, 0xb0),
PIN(1, 0, 10, 0x23, 0xb0),
PIN(2, 0, 11, 0x23, 0xb0),
@@ -379,6 +266,4 @@
PIN(218, 0, 1, 0x14, 0x50),
PIN(219, 0, 2, 0x14, 0x50),
};
-
-void plat_mt8192_gpio_init(void);
#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8192/platform.mk b/plat/mediatek/mt8192/platform.mk
index 11d9779..49d1059 100644
--- a/plat/mediatek/mt8192/platform.mk
+++ b/plat/mediatek/mt8192/platform.mk
@@ -9,6 +9,7 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gic600/ \
+ -I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/timer/ \
-I${MTK_PLAT}/common/drivers/uart/ \
-I${MTK_PLAT}/common/lpm/ \
@@ -42,6 +43,7 @@
lib/cpus/aarch64/cortex_a76.S \
plat/common/plat_gicv3.c \
${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
+ ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/common/drivers/pmic_wrap/pmic_wrap_init_v2.c \
${MTK_PLAT}/common/drivers/rtc/rtc_common.c \
${MTK_PLAT}/common/drivers/timer/mt_timer.c \
diff --git a/plat/mediatek/mt8195/bl31_plat_setup.c b/plat/mediatek/mt8195/bl31_plat_setup.c
index 61846a3..eaff349 100644
--- a/plat/mediatek/mt8195/bl31_plat_setup.c
+++ b/plat/mediatek/mt8195/bl31_plat_setup.c
@@ -18,6 +18,7 @@
/* Platform Includes */
#include <mt_gic_v3.h>
#include <mt_timer.h>
+#include <mtgpio.h>
#include <plat_params.h>
#include <plat_private.h>
@@ -86,6 +87,7 @@
mt_gic_driver_init();
mt_gic_init();
+ mt_gpio_init();
mt_systimer_init();
generic_delay_timer_init();
}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.c b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
new file mode 100644
index 0000000..daab84c
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.c
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <mtgpio.h>
+#include <platform_def.h>
+
+uintptr_t mt_gpio_find_reg_addr(uint32_t pin)
+{
+ uintptr_t reg_addr = 0U;
+ struct mt_pin_info gpio_info;
+
+ assert(pin < MAX_GPIO_PIN);
+
+ gpio_info = mt_pin_infos[pin];
+
+ switch (gpio_info.base & 0x0f) {
+ case 0:
+ reg_addr = IOCFG_BM_BASE;
+ break;
+ case 1:
+ reg_addr = IOCFG_BL_BASE;
+ break;
+ case 2:
+ reg_addr = IOCFG_BR_BASE;
+ break;
+ case 3:
+ reg_addr = IOCFG_LM_BASE;
+ break;
+ case 4:
+ reg_addr = IOCFG_RB_BASE;
+ break;
+ case 5:
+ reg_addr = IOCFG_TL_BASE;
+ break;
+ default:
+ break;
+ }
+
+ return reg_addr;
+}
diff --git a/plat/mediatek/mt8195/drivers/gpio/mtgpio.h b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
new file mode 100644
index 0000000..88b4706
--- /dev/null
+++ b/plat/mediatek/mt8195/drivers/gpio/mtgpio.h
@@ -0,0 +1,183 @@
+/*
+ * Copyright (c) 2020, MediaTek Inc. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef MT_GPIO_H
+#define MT_GPIO_H
+
+#include <mtgpio_common.h>
+
+/* Enumeration for GPIO pin */
+typedef enum GPIO_PIN {
+ GPIO_UNSUPPORTED = -1,
+
+ GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7,
+ GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, GPIO14, GPIO15,
+ GPIO16, GPIO17, GPIO18, GPIO19, GPIO20, GPIO21, GPIO22, GPIO23,
+ GPIO24, GPIO25, GPIO26, GPIO27, GPIO28, GPIO29, GPIO30, GPIO31,
+ GPIO32, GPIO33, GPIO34, GPIO35, GPIO36, GPIO37, GPIO38, GPIO39,
+ GPIO40, GPIO41, GPIO42, GPIO43, GPIO44, GPIO45, GPIO46, GPIO47,
+ GPIO48, GPIO49, GPIO50, GPIO51, GPIO52, GPIO53, GPIO54, GPIO55,
+ GPIO56, GPIO57, GPIO58, GPIO59, GPIO60, GPIO61, GPIO62, GPIO63,
+ GPIO64, GPIO65, GPIO66, GPIO67, GPIO68, GPIO69, GPIO70, GPIO71,
+ GPIO72, GPIO73, GPIO74, GPIO75, GPIO76, GPIO77, GPIO78, GPIO79,
+ GPIO80, GPIO81, GPIO82, GPIO83, GPIO84, GPIO85, GPIO86, GPIO87,
+ GPIO88, GPIO89, GPIO90, GPIO91, GPIO92, GPIO93, GPIO94, GPIO95,
+ GPIO96, GPIO97, GPIO98, GPIO99, GPIO100, GPIO101, GPIO102, GPIO103,
+ GPIO104, GPIO105, GPIO106, GPIO107, GPIO108, GPIO109, GPIO110, GPIO111,
+ GPIO112, GPIO113, GPIO114, GPIO115, GPIO116, GPIO117, GPIO118, GPIO119,
+ GPIO120, GPIO121, GPIO122, GPIO123, GPIO124, GPIO125, GPIO126, GPIO127,
+ GPIO128, GPIO129, GPIO130, GPIO131, GPIO132, GPIO133, GPIO134, GPIO135,
+ GPIO136, GPIO137, GPIO138, GPIO139, GPIO140, GPIO141, GPIO142, GPIO143,
+ MT_GPIO_BASE_MAX
+} GPIO_PIN;
+
+static const struct mt_pin_info mt_pin_infos[] = {
+ PIN(0, 1, 0, 0x23, 0x60),
+ PIN(1, 1, 1, 0x23, 0x60),
+ PIN(2, 1, 2, 0x23, 0x60),
+ PIN(3, 1, 3, 0x23, 0x60),
+ PIN(4, 1, 4, 0x23, 0x60),
+ PIN(5, 1, 5, 0x23, 0x60),
+ PIN(6, 0, 6, 0x23, 0x70),
+ PIN(7, 0, 7, 0x23, 0x70),
+ PIN(8, 0, 13, 0x23, 0x70),
+ PIN(9, 0, 8, 0x23, 0x70),
+ PIN(10, 0, 14, 0x23, 0x70),
+ PIN(11, 0, 9, 0x23, 0x70),
+ PIN(12, 0, 15, 0x23, 0x70),
+ PIN(13, 0, 10, 0x23, 0x70),
+ PIN(14, 0, 16, 0x23, 0x70),
+ PIN(15, 0, 11, 0x23, 0x70),
+ PIN(16, 0, 17, 0x23, 0x70),
+ PIN(17, 0, 12, 0x23, 0x70),
+ PIN(18, 0, 5, 0x10, 0x60),
+ PIN(19, 0, 12, 0x10, 0x60),
+ PIN(20, 0, 11, 0x10, 0x60),
+ PIN(21, 0, 10, 0x10, 0x60),
+ PIN(22, 0, 0, 0x10, 0x60),
+ PIN(23, 0, 1, 0x10, 0x60),
+ PIN(24, 0, 2, 0x10, 0x60),
+ PIN(25, 0, 4, 0x10, 0x60),
+ PIN(26, 0, 3, 0x10, 0x60),
+ PIN(27, 0, 6, 0x10, 0x60),
+ PIN(28, 0, 7, 0x10, 0x60),
+ PIN(29, 0, 8, 0x10, 0x60),
+ PIN(30, 0, 9, 0x10, 0x60),
+ PIN(31, 0, 13, 0x21, 0xa0),
+ PIN(32, 0, 12, 0x21, 0xa0),
+ PIN(33, 0, 11, 0x21, 0xa0),
+ PIN(34, 0, 14, 0x21, 0xa0),
+ PIN(35, 0, 15, 0x21, 0xa0),
+ PIN(36, 0, 3, 0x21, 0xb0),
+ PIN(37, 0, 6, 0x21, 0xb0),
+ PIN(38, 0, 4, 0x21, 0xb0),
+ PIN(39, 0, 5, 0x21, 0xb0),
+ PIN(40, 0, 8, 0x21, 0xb0),
+ PIN(41, 0, 7, 0x21, 0xb0),
+ PIN(42, 0, 10, 0x21, 0xb0),
+ PIN(43, 0, 9, 0x21, 0xb0),
+ PIN(44, 0, 20, 0x21, 0xb0),
+ PIN(45, 0, 21, 0x21, 0xb0),
+ PIN(46, 0, 18, 0x21, 0xa0),
+ PIN(47, 0, 16, 0x21, 0xa0),
+ PIN(48, 0, 19, 0x21, 0xa0),
+ PIN(49, 0, 17, 0x21, 0xa0),
+ PIN(50, 0, 25, 0x21, 0xa0),
+ PIN(51, 0, 20, 0x21, 0xa0),
+ PIN(52, 0, 26, 0x21, 0xa0),
+ PIN(53, 0, 21, 0x21, 0xa0),
+ PIN(54, 0, 22, 0x21, 0xa0),
+ PIN(55, 0, 23, 0x21, 0xa0),
+ PIN(56, 0, 24, 0x21, 0xa0),
+ PIN(57, 0, 29, 0x21, 0xa0),
+ PIN(58, 0, 27, 0x21, 0xa0),
+ PIN(59, 0, 30, 0x21, 0xa0),
+ PIN(60, 0, 28, 0x21, 0xa0),
+ PIN(61, 0, 8, 0x21, 0xa0),
+ PIN(62, 0, 7, 0x21, 0xa0),
+ PIN(63, 0, 10, 0x21, 0xa0),
+ PIN(64, 0, 9, 0x21, 0xa0),
+ PIN(65, 0, 1, 0x21, 0xb0),
+ PIN(66, 0, 31, 0x21, 0xa0),
+ PIN(67, 0, 0, 0x21, 0xb0),
+ PIN(68, 0, 2, 0x21, 0xb0),
+ PIN(69, 0, 0, 0x21, 0xa0),
+ PIN(70, 0, 6, 0x21, 0xa0),
+ PIN(71, 0, 4, 0x21, 0xa0),
+ PIN(72, 0, 5, 0x21, 0xa0),
+ PIN(73, 0, 1, 0x21, 0xa0),
+ PIN(74, 0, 2, 0x21, 0xa0),
+ PIN(75, 0, 3, 0x21, 0xa0),
+ PIN(76, 0, 11, 0x21, 0xb0),
+ PIN(77, 1, 1, 0x22, 0x60),
+ PIN(78, 1, 2, 0x22, 0x60),
+ PIN(79, 1, 9, 0x22, 0x60),
+ PIN(80, 1, 10, 0x22, 0x60),
+ PIN(81, 1, 11, 0x22, 0x60),
+ PIN(82, 1, 12, 0x22, 0x60),
+ PIN(83, 1, 13, 0x22, 0x60),
+ PIN(84, 1, 14, 0x22, 0x60),
+ PIN(85, 1, 15, 0x22, 0x60),
+ PIN(86, 1, 16, 0x22, 0x60),
+ PIN(87, 1, 3, 0x22, 0x60),
+ PIN(88, 1, 4, 0x22, 0x60),
+ PIN(89, 1, 5, 0x22, 0x60),
+ PIN(90, 1, 6, 0x22, 0x60),
+ PIN(91, 1, 7, 0x22, 0x60),
+ PIN(92, 1, 8, 0x22, 0x60),
+ PIN(93, 1, 18, 0x22, 0x60),
+ PIN(94, 1, 19, 0x22, 0x60),
+ PIN(95, 1, 17, 0x22, 0x60),
+ PIN(96, 1, 0, 0x22, 0x60),
+ PIN(97, 0, 20, 0x22, 0x70),
+ PIN(98, 0, 28, 0x22, 0x70),
+ PIN(99, 0, 27, 0x22, 0x70),
+ PIN(100, 0, 30, 0x22, 0x70),
+ PIN(101, 0, 29, 0x22, 0x70),
+ PIN(102, 0, 0, 0x22, 0x70),
+ PIN(103, 0, 31, 0x22, 0x70),
+ PIN(104, 1, 25, 0x22, 0x60),
+ PIN(105, 1, 26, 0x22, 0x60),
+ PIN(106, 1, 23, 0x22, 0x60),
+ PIN(107, 1, 24, 0x22, 0x60),
+ PIN(108, 0, 22, 0x22, 0x70),
+ PIN(109, 0, 21, 0x22, 0x70),
+ PIN(110, 1, 1, 0x14, 0x20),
+ PIN(111, 1, 0, 0x14, 0x20),
+ PIN(112, 1, 2, 0x14, 0x20),
+ PIN(113, 1, 3, 0x14, 0x20),
+ PIN(114, 1, 4, 0x14, 0x20),
+ PIN(115, 1, 5, 0x14, 0x20),
+ PIN(116, 1, 9, 0x25, 0x50),
+ PIN(117, 1, 8, 0x25, 0x50),
+ PIN(118, 1, 7, 0x25, 0x50),
+ PIN(119, 1, 6, 0x25, 0x50),
+ PIN(120, 1, 11, 0x25, 0x50),
+ PIN(121, 1, 1, 0x25, 0x50),
+ PIN(122, 1, 0, 0x25, 0x50),
+ PIN(123, 1, 5, 0x25, 0x50),
+ PIN(124, 1, 4, 0x25, 0x50),
+ PIN(125, 1, 3, 0x25, 0x50),
+ PIN(126, 1, 2, 0x25, 0x50),
+ PIN(127, 1, 10, 0x25, 0x50),
+ PIN(128, 0, 3, 0x22, 0x70),
+ PIN(129, 0, 1, 0x22, 0x70),
+ PIN(130, 0, 4, 0x22, 0x70),
+ PIN(131, 0, 2, 0x22, 0x70),
+ PIN(132, 0, 13, 0x25, 0x60),
+ PIN(133, 0, 12, 0x25, 0x60),
+ PIN(134, 0, 15, 0x25, 0x60),
+ PIN(135, 0, 14, 0x25, 0x60),
+ PIN(136, 0, 13, 0x21, 0xb0),
+ PIN(137, 0, 12, 0x21, 0xb0),
+ PIN(138, 0, 15, 0x21, 0xb0),
+ PIN(139, 0, 14, 0x21, 0xb0),
+ PIN(140, 0, 17, 0x21, 0xb0),
+ PIN(141, 0, 16, 0x21, 0xb0),
+ PIN(142, 0, 19, 0x21, 0xb0),
+ PIN(143, 0, 18, 0x21, 0xb0),
+};
+#endif /* MT_GPIO_H */
diff --git a/plat/mediatek/mt8195/include/platform_def.h b/plat/mediatek/mt8195/include/platform_def.h
index 307187e..a97d222 100644
--- a/plat/mediatek/mt8195/include/platform_def.h
+++ b/plat/mediatek/mt8195/include/platform_def.h
@@ -26,6 +26,17 @@
#define SPM_BASE (IO_PHYS + 0x00006000)
/*******************************************************************************
+ * GPIO related constants
+ ******************************************************************************/
+#define GPIO_BASE (IO_PHYS + 0x00005000)
+#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
+#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
+#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
+#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
+#define IOCFG_RB_BASE (IO_PHYS + 0x01EB0000)
+#define IOCFG_TL_BASE (IO_PHYS + 0x01F40000)
+
+/*******************************************************************************
* UART related constants
******************************************************************************/
#define UART0_BASE (IO_PHYS + 0x01001100)
diff --git a/plat/mediatek/mt8195/platform.mk b/plat/mediatek/mt8195/platform.mk
index 0f8263a..1a49b67 100644
--- a/plat/mediatek/mt8195/platform.mk
+++ b/plat/mediatek/mt8195/platform.mk
@@ -9,7 +9,9 @@
PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT}/common/drivers/gic600/ \
+ -I${MTK_PLAT}/common/drivers/gpio/ \
-I${MTK_PLAT}/common/drivers/timer/ \
+ -I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
-I${MTK_PLAT_SOC}/drivers/spmc/ \
-I${MTK_PLAT_SOC}/include/
@@ -26,6 +28,7 @@
BL31_SOURCES += common/desc_image_load.c \
drivers/delay_timer/delay_timer.c \
+ drivers/gpio/gpio.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
lib/bl_aux_params/bl_aux_params.c \
@@ -33,6 +36,7 @@
lib/cpus/aarch64/cortex_a78.S \
plat/common/plat_gicv3.c \
${MTK_PLAT}/common/drivers/gic600/mt_gic_v3.c \
+ ${MTK_PLAT}/common/drivers/gpio/mtgpio_common.c \
${MTK_PLAT}/common/drivers/timer/mt_timer.c \
${MTK_PLAT}/common/mtk_cirq.c \
${MTK_PLAT}/common/mtk_plat_common.c \
@@ -41,9 +45,11 @@
${MTK_PLAT_SOC}/aarch64/platform_common.c \
${MTK_PLAT_SOC}/aarch64/plat_helpers.S \
${MTK_PLAT_SOC}/bl31_plat_setup.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm_cpc.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_mcdi.c \
+ ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c \
${MTK_PLAT_SOC}/plat_pm.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \