diff --git a/plat/nvidia/tegra/common/tegra_gicv2.c b/plat/nvidia/tegra/common/tegra_gicv2.c
index 293df8d..012107e 100644
--- a/plat/nvidia/tegra/common/tegra_gicv2.c
+++ b/plat/nvidia/tegra/common/tegra_gicv2.c
@@ -1,20 +1,23 @@
 /*
  * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
 #include <assert.h>
-
 #include <platform_def.h>
 
 #include <common/bl_common.h>
 #include <drivers/arm/gicv2.h>
 #include <lib/utils.h>
+#include <plat/common/platform.h>
 
 #include <tegra_private.h>
 #include <tegra_def.h>
 
+static unsigned int tegra_target_masks[PLATFORM_CORE_COUNT];
+
 /******************************************************************************
  * Tegra common helper to setup the GICv2 driver data.
  *****************************************************************************/
@@ -33,6 +36,8 @@
 	tegra_gic_data.gicc_base = TEGRA_GICC_BASE;
 	tegra_gic_data.interrupt_props = interrupt_props;
 	tegra_gic_data.interrupt_props_num = interrupt_props_num;
+	tegra_gic_data.target_masks = tegra_target_masks;
+	tegra_gic_data.target_masks_num = ARRAY_SIZE(tegra_target_masks);
 	gicv2_driver_init(&tegra_gic_data);
 }
 
@@ -43,6 +48,7 @@
 {
 	gicv2_distif_init();
 	gicv2_pcpu_distif_init();
+	gicv2_set_pe_target_mask(plat_my_core_pos());
 	gicv2_cpuif_enable();
 }
 
@@ -61,5 +67,6 @@
 void tegra_gic_pcpu_init(void)
 {
 	gicv2_pcpu_distif_init();
+	gicv2_set_pe_target_mask(plat_my_core_pos());
 	gicv2_cpuif_enable();
 }