refactor(st): move FWU functions to common code
Move the platforms functions used for Firmware update in plat/st/common
directory. The function stm32mp1_fwu_set_boot_idx() is renamed
stm32_fwu_set_boot_idx() to align with other ones. A new function
stm32_get_bkpr_fwu_info_addr() is created to get the backup register
address where to store FWU info (counter and partition index).
Signed-off-by: Yann Gautier <yann.gautier@foss.st.com>
Change-Id: I64916c7992782ceeaaf990026756ca4134d93c88
diff --git a/plat/st/common/include/stm32mp_common.h b/plat/st/common/include/stm32mp_common.h
index 41b86ae..9af221c 100644
--- a/plat/st/common/include/stm32mp_common.h
+++ b/plat/st/common/include/stm32mp_common.h
@@ -131,7 +131,8 @@
void stm32_display_board_info(uint32_t board_id);
#if PSA_FWU_SUPPORT
-void stm32mp1_fwu_set_boot_idx(void);
+uintptr_t stm32_get_bkpr_fwu_info_addr(void);
+void stm32_fwu_set_boot_idx(void);
uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void);
void stm32_set_max_fwu_trial_boot_cnt(void);
void stm32_clear_fwu_trial_boot_cnt(void);
diff --git a/plat/st/common/stm32mp_common.c b/plat/st/common/stm32mp_common.c
index 6f36011..d2f8784 100644
--- a/plat/st/common/stm32mp_common.c
+++ b/plat/st/common/stm32mp_common.c
@@ -55,6 +55,12 @@
#define BOOT_INST_MASK GENMASK_32(11, 8)
#define BOOT_INST_SHIFT 8
+/* Layout for fwu update information. */
+#define FWU_INFO_IDX_MSK GENMASK(3, 0)
+#define FWU_INFO_IDX_OFF U(0)
+#define FWU_INFO_CNT_MSK GENMASK(7, 4)
+#define FWU_INFO_CNT_OFF U(4)
+
static console_t console;
uintptr_t plat_get_ns_image_entrypoint(void)
@@ -378,3 +384,53 @@
*interface = (itf & BOOT_ITF_MASK) >> BOOT_ITF_SHIFT;
*instance = (itf & BOOT_INST_MASK) >> BOOT_INST_SHIFT;
}
+
+#if PSA_FWU_SUPPORT
+void stm32_fwu_set_boot_idx(void)
+{
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrsetbits_32(stm32_get_bkpr_fwu_info_addr(),
+ FWU_INFO_IDX_MSK,
+ (plat_fwu_get_boot_idx() << FWU_INFO_IDX_OFF) &
+ FWU_INFO_IDX_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+ uint32_t try_cnt;
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ try_cnt = (mmio_read_32(bkpr_fwu_cnt) & FWU_INFO_CNT_MSK) >> FWU_INFO_CNT_OFF;
+
+ assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
+
+ if (try_cnt != 0U) {
+ mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
+ (try_cnt - 1U) << FWU_INFO_CNT_OFF);
+ }
+ clk_disable(TAMP_BKP_REG_CLK);
+
+ return try_cnt;
+}
+
+void stm32_set_max_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrsetbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK,
+ (FWU_MAX_TRIAL_REBOOT << FWU_INFO_CNT_OFF) & FWU_INFO_CNT_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+
+void stm32_clear_fwu_trial_boot_cnt(void)
+{
+ uintptr_t bkpr_fwu_cnt = stm32_get_bkpr_fwu_info_addr();
+
+ clk_enable(TAMP_BKP_REG_CLK);
+ mmio_clrbits_32(bkpr_fwu_cnt, FWU_INFO_CNT_MSK);
+ clk_disable(TAMP_BKP_REG_CLK);
+}
+#endif /* PSA_FWU_SUPPORT */
diff --git a/plat/st/stm32mp1/bl2_plat_setup.c b/plat/st/stm32mp1/bl2_plat_setup.c
index 24ecb32..2ade242 100644
--- a/plat/st/stm32mp1/bl2_plat_setup.c
+++ b/plat/st/stm32mp1/bl2_plat_setup.c
@@ -507,7 +507,7 @@
assert(bl32_mem_params != NULL);
bl32_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
#if PSA_FWU_SUPPORT
- stm32mp1_fwu_set_boot_idx();
+ stm32_fwu_set_boot_idx();
#endif /* PSA_FWU_SUPPORT */
break;
diff --git a/plat/st/stm32mp1/stm32mp1_private.c b/plat/st/stm32mp1/stm32mp1_private.c
index 509bb11..189f83d 100644
--- a/plat/st/stm32mp1/stm32mp1_private.c
+++ b/plat/st/stm32mp1/stm32mp1_private.c
@@ -29,10 +29,6 @@
* (so it should be in Zone 2).
*/
#define TAMP_BOOT_FWU_INFO_REG_ID U(10)
-#define TAMP_BOOT_FWU_INFO_IDX_MSK GENMASK(3, 0)
-#define TAMP_BOOT_FWU_INFO_IDX_OFF U(0)
-#define TAMP_BOOT_FWU_INFO_CNT_MSK GENMASK(7, 4)
-#define TAMP_BOOT_FWU_INFO_CNT_OFF U(4)
#if defined(IMAGE_BL2)
#define MAP_SEC_SYSRAM MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
@@ -674,53 +670,8 @@
}
#if PSA_FWU_SUPPORT
-void stm32mp1_fwu_set_boot_idx(void)
+uintptr_t stm32_get_bkpr_fwu_info_addr(void)
{
- clk_enable(RTCAPB);
- mmio_clrsetbits_32(tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID),
- TAMP_BOOT_FWU_INFO_IDX_MSK,
- (plat_fwu_get_boot_idx() << TAMP_BOOT_FWU_INFO_IDX_OFF) &
- TAMP_BOOT_FWU_INFO_IDX_MSK);
- clk_disable(RTCAPB);
-}
-
-uint32_t stm32_get_and_dec_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
- uint32_t try_cnt;
-
- clk_enable(RTCAPB);
- try_cnt = (mmio_read_32(bkpr_fwu_cnt) & TAMP_BOOT_FWU_INFO_CNT_MSK) >>
- TAMP_BOOT_FWU_INFO_CNT_OFF;
-
- assert(try_cnt <= FWU_MAX_TRIAL_REBOOT);
-
- if (try_cnt != 0U) {
- mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
- (try_cnt - 1U) << TAMP_BOOT_FWU_INFO_CNT_OFF);
- }
- clk_disable(RTCAPB);
-
- return try_cnt;
-}
-
-void stm32_set_max_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
-
- clk_enable(RTCAPB);
- mmio_clrsetbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK,
- (FWU_MAX_TRIAL_REBOOT << TAMP_BOOT_FWU_INFO_CNT_OFF) &
- TAMP_BOOT_FWU_INFO_CNT_MSK);
- clk_disable(RTCAPB);
-}
-
-void stm32_clear_fwu_trial_boot_cnt(void)
-{
- uintptr_t bkpr_fwu_cnt = tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
-
- clk_enable(RTCAPB);
- mmio_clrbits_32(bkpr_fwu_cnt, TAMP_BOOT_FWU_INFO_CNT_MSK);
- clk_disable(RTCAPB);
+ return tamp_bkpr(TAMP_BOOT_FWU_INFO_REG_ID);
}
#endif /* PSA_FWU_SUPPORT */