diff --git a/plat/intel/soc/stratix10/include/s10_system_manager.h b/plat/intel/soc/stratix10/include/s10_system_manager.h
deleted file mode 100644
index c34fcf7..0000000
--- a/plat/intel/soc/stratix10/include/s10_system_manager.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define S10_FIREWALL_SOC2FPGA                   0xffd21200
-#define S10_FIREWALL_LWSOC2FPGA                 0xffd21300
-
-/* L3 Interconnect Register Map */
-#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
-#define S10_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
-#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
-#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
-#define S10_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
-#define S10_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
-#define S10_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
-#define S10_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
-#define S10_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
-#define S10_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
-#define S10_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
-#define S10_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
-#define S10_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
-#define S10_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
-#define S10_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
-#define S10_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
-#define S10_NOC_FW_L4_PER_SCR_UART1		0xffd21070
-
-#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
-#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
-#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
-#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
-#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
-#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
-#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
-#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
-#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
-#define S10_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
-#define S10_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
-#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
-#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
-#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
-#define S10_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
-
-#define S10_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
-#define S10_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
-
-/* System Manager Register Map */
-#define S10_SYSMGR_CORE(x)			(0xffd12000 + (x))
-
-#define SYSMGR_MMC				0x28
-#define SYSMGR_MMC_DRVSEL(x)			(((x) & 0x7) << 0)
-
-#define SYSMGR_NOC_TIMEOUT			0xc0
-#define SYSMGR_NOC_IDLEREQ_SET			0xc4
-#define SYSMGR_NOC_IDLEREQ_CLR			0xc8
-#define SYSMGR_NOC_IDLEREQ_VAL			0xcc
-#define SYSMGR_NOC_IDLEACK			0xd0
-#define SYSMGR_NOC_IDLESTATUS			0xd4
-
-#define IDLE_DATA_LWSOC2FPGA			BIT(0)
-#define IDLE_DATA_SOC2FPGA			BIT(4)
-#define IDLE_DATA_MASK	(IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
-
-#define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
-
-#define DISABLE_BRIDGE_FIREWALL                 0x0ffe0101
-#define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
-
-void enable_nonsecure_access(void);
-void enable_ns_peripheral_access(void);
-void enable_ns_bridge_access(void);
diff --git a/plat/intel/soc/stratix10/include/socfpga_plat_def.h b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
index 066585e..9dc5151 100644
--- a/plat/intel/soc/stratix10/include/socfpga_plat_def.h
+++ b/plat/intel/soc/stratix10/include/socfpga_plat_def.h
@@ -14,7 +14,15 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE                    0xff808000
+
 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
+
 
 #endif /* PLATSOCFPGA_DEF_H */