Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
diff --git a/plat/common/aarch64/platform_helpers.S b/plat/common/aarch64/platform_helpers.S
index 1229ead..c236fd7 100644
--- a/plat/common/aarch64/platform_helpers.S
+++ b/plat/common/aarch64/platform_helpers.S
@@ -39,6 +39,7 @@
.weak plat_crash_console_init
.weak plat_crash_console_putc
.weak plat_reset_handler
+ .weak plat_disable_acp
/* -----------------------------------------------------
* int platform_get_core_pos(int mpidr);
@@ -93,3 +94,12 @@
*/
func plat_reset_handler
ret
+
+ /* -----------------------------------------------------
+ * Placeholder function which should be redefined by
+ * each platform. This function is allowed to use
+ * registers x0 - x17.
+ * -----------------------------------------------------
+ */
+func plat_disable_acp
+ ret
diff --git a/plat/fvp/aarch64/fvp_common.c b/plat/fvp/aarch64/fvp_common.c
index 89fd8b3..a25c4f0 100644
--- a/plat/fvp/aarch64/fvp_common.c
+++ b/plat/fvp/aarch64/fvp_common.c
@@ -134,7 +134,7 @@
******************************************************************************/
int fvp_config_setup(void)
{
- unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
+ unsigned int rev, hbi, bld, arch, sys_id;
sys_id = mmio_read_32(VE_SYSREGS_BASE + V2M_SYS_ID);
rev = (sys_id >> SYS_ID_REV_SHIFT) & SYS_ID_REV_MASK;
@@ -193,11 +193,6 @@
}
break;
case HBI_FVP_BASE:
- midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
- plat_config.flags =
- ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
- ? CONFIG_CPUECTLR_SMP_BIT : 0;
-
plat_config.max_aff0 = 4;
plat_config.max_aff1 = 2;
plat_config.flags |= CONFIG_BASE_MMAP | CONFIG_HAS_CCI |
diff --git a/plat/fvp/fvp_pm.c b/plat/fvp/fvp_pm.c
index 568b51d..2038e87 100644
--- a/plat/fvp/fvp_pm.c
+++ b/plat/fvp/fvp_pm.c
@@ -66,18 +66,6 @@
******************************************************************************/
static void fvp_cpu_pwrdwn_common()
{
- uint32_t ectlr;
-
- /*
- * Take this cpu out of intra-cluster coherency if the FVP flavour
- * supports the SMP bit.
- */
- if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
- ectlr = read_cpuectlr();
- ectlr &= ~CPUECTLR_SMP_BIT;
- write_cpuectlr(ectlr);
- }
-
/* Prevent interrupts from spuriously waking up this cpu */
arm_gic_cpuif_deactivate();
@@ -273,7 +261,6 @@
unsigned int state)
{
int rc = PSCI_E_SUCCESS;
- unsigned int ectlr;
/* Determine if any platform actions need to be executed. */
if (fvp_do_plat_actions(afflvl, state) == -EAGAIN)
@@ -297,16 +284,6 @@
}
/*
- * Turn on intra-cluster coherency if the FVP flavour supports
- * it.
- */
- if (get_plat_config()->flags & CONFIG_CPUECTLR_SMP_BIT) {
- ectlr = read_cpuectlr();
- ectlr |= CPUECTLR_SMP_BIT;
- write_cpuectlr(ectlr);
- }
-
- /*
* Clear PWKUPR.WEN bit to ensure interrupts do not interfere
* with a cpu power down unless the bit is set again
*/