diff --git a/include/lib/aarch64/arch.h b/include/lib/aarch64/arch.h
index bb33acb..333dcf1 100644
--- a/include/lib/aarch64/arch.h
+++ b/include/lib/aarch64/arch.h
@@ -39,9 +39,9 @@
 #define MIDR_IMPL_SHIFT		0x18
 #define MIDR_PN_MASK		0xfff
 #define MIDR_PN_SHIFT		0x4
-#define MIDR_PN_AEM		0xd0f
-#define MIDR_PN_A57		0xd07
-#define MIDR_PN_A53		0xd03
+#define MIDR_PN_AEM			0xd0f
+#define MIDR_PN_A57			0xd07
+#define MIDR_PN_A53			0xd03
 
 /*******************************************************************************
  * MPIDR macros
@@ -135,9 +135,6 @@
 #define SCTLR_WXN_BIT		(1 << 19)
 #define SCTLR_EE_BIT		(1 << 25)
 
-/* CPUECTLR definitions */
-#define CPUECTLR_SMP_BIT	(1 << 6)
-
 /* CPACR_El1 definitions */
 #define CPACR_EL1_FPEN(x)	(x << 20)
 #define CPACR_EL1_FP_TRAP_EL0	0x1
diff --git a/include/lib/aarch64/arch_helpers.h b/include/lib/aarch64/arch_helpers.h
index 6ba37c2..09365fb 100644
--- a/include/lib/aarch64/arch_helpers.h
+++ b/include/lib/aarch64/arch_helpers.h
@@ -265,10 +265,6 @@
 DEFINE_SYSREG_RW_FUNCS(vpidr_el2)
 DEFINE_SYSREG_RW_FUNCS(vmpidr_el2)
 
-/* Implementation specific registers */
-
-DEFINE_RENAME_SYSREG_RW_FUNCS(cpuectlr_el1, CPUECTLR_EL1)
-
 /* GICv3 System Registers */
 
 DEFINE_RENAME_SYSREG_RW_FUNCS(icc_sre_el1, ICC_SRE_EL1)
@@ -299,9 +295,6 @@
 #define read_hcr()		read_hcr_el2()
 #define write_hcr(_v)		write_hcr_el2(_v)
 
-#define read_cpuectlr()		read_cpuectlr_el1()
-#define write_cpuectlr(_v)	write_cpuectlr_el1(_v)
-
 #define read_cpacr()		read_cpacr_el1()
 #define write_cpacr(_v)		write_cpacr_el1(_v)
 
diff --git a/include/lib/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/aem_generic.h
similarity index 65%
copy from include/lib/aarch64/cpu_macros.S
copy to include/lib/cpus/aarch64/aem_generic.h
index 51c56e8..2f701d1 100644
--- a/include/lib/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/aem_generic.h
@@ -28,38 +28,14 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch.h>
+#ifndef __AEM_GENERIC_H__
+#define __AEM_GENERIC_H__
 
-#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
-				(MIDR_PN_MASK << MIDR_PN_SHIFT)
+/* BASE AEM midr for revision 0 */
+#define BASE_AEM_MIDR 0x410FD0F0
 
-	/*
-	 * Define the offsets to the fields in cpu_ops structure.
-	 */
-	.struct 0
-CPU_MIDR: /* cpu_ops midr */
-	.space  8
-/* Reset fn is needed in BL at reset vector */
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-CPU_RESET_FUNC: /* cpu_ops reset_func */
-	.space  8
-#endif
-CPU_OPS_SIZE = .
+/* Foundation AEM midr for revision 0 */
+#define FOUNDATION_AEM_MIDR  0x410FD000
+
 
-	/*
-	 * Convenience macro to declare cpu_ops structure.
-	 * Make sure the structure fields are as per the offsets
-	 * defined above.
-	 */
-	.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
-	.section cpu_ops, "a"; .align 3
-	.type cpu_ops_\_name, %object
-	.quad \_midr
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-	.if \_noresetfunc
-	.quad 0
-	.else
-	.quad \_name\()_reset_func
-	.endif
-#endif
-	.endm
+#endif /* __AEM_GENERIC_H__ */
diff --git a/include/lib/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cortex_a53.h
similarity index 65%
copy from include/lib/aarch64/cpu_macros.S
copy to include/lib/cpus/aarch64/cortex_a53.h
index 51c56e8..dcae411 100644
--- a/include/lib/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cortex_a53.h
@@ -28,38 +28,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch.h>
+#ifndef __CORTEX_A53_H__
+#define __CORTEX_A53_H__
 
-#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
-				(MIDR_PN_MASK << MIDR_PN_SHIFT)
+/* Cortex-A53 midr for revision 0 */
+#define CORTEX_A53_MIDR 0x410FD030
 
-	/*
-	 * Define the offsets to the fields in cpu_ops structure.
-	 */
-	.struct 0
-CPU_MIDR: /* cpu_ops midr */
-	.space  8
-/* Reset fn is needed in BL at reset vector */
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-CPU_RESET_FUNC: /* cpu_ops reset_func */
-	.space  8
-#endif
-CPU_OPS_SIZE = .
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CPUECTLR_SMP_BIT		(1 << 6)
 
-	/*
-	 * Convenience macro to declare cpu_ops structure.
-	 * Make sure the structure fields are as per the offsets
-	 * defined above.
-	 */
-	.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
-	.section cpu_ops, "a"; .align 3
-	.type cpu_ops_\_name, %object
-	.quad \_midr
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-	.if \_noresetfunc
-	.quad 0
-	.else
-	.quad \_name\()_reset_func
-	.endif
-#endif
-	.endm
+#endif /* __CORTEX_A53_H__ */
diff --git a/include/lib/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cortex_a57.h
similarity index 65%
copy from include/lib/aarch64/cpu_macros.S
copy to include/lib/cpus/aarch64/cortex_a57.h
index 51c56e8..cf887d0 100644
--- a/include/lib/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cortex_a57.h
@@ -28,38 +28,18 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch.h>
+#ifndef __CORTEX_A57_H__
+#define __CORTEX_A57_H__
 
-#define CPU_IMPL_PN_MASK	(MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \
-				(MIDR_PN_MASK << MIDR_PN_SHIFT)
+/* Cortex-A57 midr for revision 0 */
+#define CORTEX_A57_MIDR 0x410FD070
 
-	/*
-	 * Define the offsets to the fields in cpu_ops structure.
-	 */
-	.struct 0
-CPU_MIDR: /* cpu_ops midr */
-	.space  8
-/* Reset fn is needed in BL at reset vector */
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-CPU_RESET_FUNC: /* cpu_ops reset_func */
-	.space  8
-#endif
-CPU_OPS_SIZE = .
+/*******************************************************************************
+ * CPU Extended Control register specific definitions.
+ ******************************************************************************/
+#define CPUECTLR_SMP_BIT		(1 << 6)
+#define CPUECTLR_DIS_TWD_ACC_PFTCH_BIT	(1 << 38)
+#define CPUECTLR_L2_IPFTCH_DIST_MASK	(0x3 << 35)
+#define CPUECTLR_L2_DPFTCH_DIST_MASK	(0x3 << 32)
 
-	/*
-	 * Convenience macro to declare cpu_ops structure.
-	 * Make sure the structure fields are as per the offsets
-	 * defined above.
-	 */
-	.macro declare_cpu_ops _name:req, _midr:req, _noresetfunc = 0
-	.section cpu_ops, "a"; .align 3
-	.type cpu_ops_\_name, %object
-	.quad \_midr
-#if IMAGE_BL1 || (IMAGE_BL31 && RESET_TO_BL31)
-	.if \_noresetfunc
-	.quad 0
-	.else
-	.quad \_name\()_reset_func
-	.endif
-#endif
-	.endm
+#endif /* __CORTEX_A57_H__ */
diff --git a/include/lib/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S
similarity index 89%
rename from include/lib/aarch64/cpu_macros.S
rename to include/lib/cpus/aarch64/cpu_macros.S
index 51c56e8..abe8973 100644
--- a/include/lib/aarch64/cpu_macros.S
+++ b/include/lib/cpus/aarch64/cpu_macros.S
@@ -44,6 +44,12 @@
 CPU_RESET_FUNC: /* cpu_ops reset_func */
 	.space  8
 #endif
+#if IMAGE_BL31 /* The power down core and cluster is needed only in BL3-1 */
+CPU_PWR_DWN_CORE: /* cpu_ops core_pwr_dwn */
+	.space  8
+CPU_PWR_DWN_CLUSTER: /* cpu_ops cluster_pwr_dwn */
+	.space  8
+#endif
 CPU_OPS_SIZE = .
 
 	/*
@@ -62,4 +68,8 @@
 	.quad \_name\()_reset_func
 	.endif
 #endif
+#if IMAGE_BL31
+	.quad \_name\()_core_pwr_dwn
+	.quad \_name\()_cluster_pwr_dwn
+#endif
 	.endm
diff --git a/include/plat/common/plat_config.h b/include/plat/common/plat_config.h
index 826d01b..20d3c03 100644
--- a/include/plat/common/plat_config.h
+++ b/include/plat/common/plat_config.h
@@ -39,14 +39,12 @@
 
 
 enum plat_config_flags {
-	/* Whether CPUECTLR SMP bit should be enabled */
-	CONFIG_CPUECTLR_SMP_BIT		= 0x1,
 	/* Whether Base FVP memory map is in use */
-	CONFIG_BASE_MMAP		= 0x2,
+	CONFIG_BASE_MMAP		= 0x1,
 	/* Whether CCI should be enabled */
-	CONFIG_HAS_CCI			= 0x4,
+	CONFIG_HAS_CCI			= 0x2,
 	/* Whether TZC should be configured */
-	CONFIG_HAS_TZC			= 0x8
+	CONFIG_HAS_TZC			= 0x4
 };
 
 typedef struct plat_config {