Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
diff --git a/include/plat/common/plat_config.h b/include/plat/common/plat_config.h
index 826d01b..20d3c03 100644
--- a/include/plat/common/plat_config.h
+++ b/include/plat/common/plat_config.h
@@ -39,14 +39,12 @@
enum plat_config_flags {
- /* Whether CPUECTLR SMP bit should be enabled */
- CONFIG_CPUECTLR_SMP_BIT = 0x1,
/* Whether Base FVP memory map is in use */
- CONFIG_BASE_MMAP = 0x2,
+ CONFIG_BASE_MMAP = 0x1,
/* Whether CCI should be enabled */
- CONFIG_HAS_CCI = 0x4,
+ CONFIG_HAS_CCI = 0x2,
/* Whether TZC should be configured */
- CONFIG_HAS_TZC = 0x8
+ CONFIG_HAS_TZC = 0x4
};
typedef struct plat_config {