Add CPU specific power management operations
This patch adds CPU core and cluster power down sequences to the CPU specific
operations framework introduced in a earlier patch. Cortex-A53, Cortex-A57 and
generic AEM sequences have been added. The latter is suitable for the
Foundation and Base AEM FVPs. A pointer to each CPU's operations structure is
saved in the per-cpu data so that it can be easily accessed during power down
seqeunces.
An optional platform API has been introduced to allow a platform to disable the
Accelerator Coherency Port (ACP) during a cluster power down sequence. The weak
definition of this function (plat_disable_acp()) does not take any action. It
should be overriden with a strong definition if the ACP is present on a
platform.
Change-Id: I8d09bd40d2f528a28d2d3f19b77101178778685d
diff --git a/Makefile b/Makefile
index 520a0d7..6f6d703 100644
--- a/Makefile
+++ b/Makefile
@@ -180,6 +180,7 @@
-Iinclude/drivers/io \
-Iinclude/lib \
-Iinclude/lib/aarch64 \
+ -Iinclude/lib/cpus/aarch64 \
-Iinclude/plat/common \
-Iinclude/stdlib \
-Iinclude/stdlib/sys \