feat(imx93): add the basic support
Add the basic boot support for i.MX93.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Change-Id: I48bac2fd8bf2145133edf101a315908266c3f50a
diff --git a/plat/imx/imx93/include/platform_def.h b/plat/imx/imx93/include/platform_def.h
new file mode 100644
index 0000000..5d3c2c8
--- /dev/null
+++ b/plat/imx/imx93/include/platform_def.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright 2022-2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PLATFORM_DEF_H
+#define PLATFORM_DEF_H
+
+#include <lib/utils_def.h>
+#include <lib/xlat_tables/xlat_tables_v2.h>
+
+#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
+#define PLATFORM_LINKER_ARCH aarch64
+
+#define PLATFORM_STACK_SIZE 0xB00
+#define CACHE_WRITEBACK_GRANULE 64
+
+#define PLAT_PRIMARY_CPU U(0x0)
+#define PLATFORM_MAX_CPU_PER_CLUSTER U(2)
+#define PLATFORM_CLUSTER_COUNT U(1)
+#define PLATFORM_CLUSTER0_CORE_COUNT U(2)
+#define PLATFORM_CORE_COUNT U(2)
+
+#define IMX_PWR_LVL0 MPIDR_AFFLVL0
+
+#define PWR_DOMAIN_AT_MAX_LVL U(1)
+#define PLAT_MAX_PWR_LVL U(2)
+#define PLAT_MAX_OFF_STATE U(4)
+#define PLAT_MAX_RET_STATE U(2)
+
+#define BL31_BASE U(0x204E0000)
+#define BL31_LIMIT U(0x20520000)
+
+/* non-secure uboot base */
+/* TODO */
+#define PLAT_NS_IMAGE_OFFSET U(0x80200000)
+
+/* GICv4 base address */
+#define PLAT_GICD_BASE U(0x48000000)
+#define PLAT_GICR_BASE U(0x48040000)
+
+#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
+#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
+
+#define MAX_XLAT_TABLES 8
+#define MAX_MMAP_REGIONS 16
+
+#define IMX_LPUART_BASE U(0x44380000)
+#define IMX_BOOT_UART_CLK_IN_HZ U(24000000) /* Select 24MHz oscillator */
+#define IMX_CONSOLE_BAUDRATE 115200
+
+#define AIPSx_SIZE U(0x800000)
+#define AIPS1_BASE U(0x44000000)
+#define AIPS2_BASE U(0x42000000)
+#define AIPS3_BASE U(0x42800000)
+#define AIPS4_BASE U(0x49000000)
+#define GPIO1_BASE U(0x47400000)
+#define GPIO2_BASE U(0x43810000)
+#define GPIO3_BASE U(0x43820000)
+#define GPIO4_BASE U(0x43830000)
+
+#define TRDC_A_BASE U(0x44270000)
+#define TRDC_W_BASE U(0x42460000)
+#define TRDC_M_BASE U(0x42810000)
+#define TRDC_N_BASE U(0x49010000)
+#define TRDC_x_SISE U(0x20000)
+
+#define SRC_BASE U(0x44460000)
+#define GPC_BASE U(0x44470000)
+#define BLK_CTRL_S_BASE U(0x444F0000)
+#define S400_MU_BASE U(0x47520000)
+
+/* system memory map define */
+#define AIPS2_MAP MAP_REGION_FLAT(AIPS2_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS)
+#define AIPS1_MAP MAP_REGION_FLAT(AIPS1_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW)
+#define AIPS4_MAP MAP_REGION_FLAT(AIPS4_BASE, AIPSx_SIZE, MT_DEVICE | MT_RW | MT_NS)
+#define GIC_MAP MAP_REGION_FLAT(PLAT_GICD_BASE, 0x200000, MT_DEVICE | MT_RW)
+#define TRDC_A_MAP MAP_REGION_FLAT(TRDC_A_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW)
+#define TRDC_W_MAP MAP_REGION_FLAT(TRDC_W_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW)
+#define TRDC_M_MAP MAP_REGION_FLAT(TRDC_M_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW)
+#define TRDC_N_MAP MAP_REGION_FLAT(TRDC_N_BASE, TRDC_x_SISE, MT_DEVICE | MT_RW)
+
+#define COUNTER_FREQUENCY 24000000
+
+#endif /* platform_def.h */
diff --git a/plat/imx/imx93/include/pwr_ctrl.h b/plat/imx/imx93/include/pwr_ctrl.h
new file mode 100644
index 0000000..9bcf486
--- /dev/null
+++ b/plat/imx/imx93/include/pwr_ctrl.h
@@ -0,0 +1,216 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef PWR_CTRL_H
+#define PWR_CTRL_H
+
+#include <stdbool.h>
+
+#include <lib/mmio.h>
+
+#include <platform_def.h>
+
+/*******************************************************************************
+ * GPC definitions & declarations
+ ******************************************************************************/
+/* GPC GLOBAL */
+#define GPC_GLOBAL_BASE U(GPC_BASE + 0x4000)
+#define GPC_AUTHEN_CTRL U(0x4)
+#define GPC_DOMAIN U(0x10)
+#define GPC_MASTER U(0x1c)
+#define GPC_SYS_SLEEP U(0x40)
+#define PMIC_CTRL U(0x100)
+#define PMIC_PRE_DLY_CTRL U(0x104)
+#define PMIC_STBY_ACK_CTRL U(0x108)
+#define GPC_ROSC_CTRL U(0x200)
+#define GPC_AON_MEM_CTRL U(0x204)
+#define GPC_EFUSE_CTRL U(0x208)
+
+#define FORCE_CPUx_DISABLE(x) (1 << (16 + (x)))
+#define PMIC_STBY_EN BIT(0)
+#define ROSC_OFF_EN BIT(0)
+
+/* GPC CPU_CTRL */
+#define CM_SLICE(x) (GPC_BASE + 0x800 * (x))
+#define CM_AUTHEN_CTRL U(0x4)
+#define CM_MISC U(0xc)
+#define CM_MODE_CTRL U(0x10)
+#define CM_IRQ_WAKEUP_MASK0 U(0x100)
+#define CM_SYS_SLEEP_CTRL U(0x380)
+#define IMR_NUM U(8)
+
+/* CM_MISC */
+#define SLEEP_HOLD_EN BIT(1)
+#define IRQ_MUX BIT(5)
+#define SW_WAKEUP BIT(6)
+
+/* CM_SYS_SLEEP_CTRL */
+#define SS_WAIT BIT(0)
+#define SS_STOP BIT(1)
+#define SS_SUSPEND BIT(2)
+
+#define CM_MODE_RUN U(0x0)
+#define CM_MODE_WAIT U(0x1)
+#define CM_MODE_STOP U(0x2)
+#define CM_MODE_SUSPEND U(0x3)
+
+#define LPM_SETTING(d, m) ((m) << (((d) % 8) * 4))
+
+enum gpc_cmc_slice {
+ CPU_M33,
+ CPU_A55C0,
+ CPU_A55C1,
+ CPU_A55_PLAT,
+};
+
+/* set gpc domain assignment */
+static inline void gpc_assign_domains(unsigned int domains)
+{
+ mmio_write_32(GPC_GLOBAL_BASE + GPC_DOMAIN, domains);
+}
+
+/* force a cpu into sleep status */
+static inline void gpc_force_cpu_suspend(unsigned int cpu)
+{
+ mmio_setbits_32(GPC_GLOBAL_BASE + GPC_SYS_SLEEP, FORCE_CPUx_DISABLE(cpu));
+}
+
+static inline void gpc_pmic_stby_en(bool en)
+{
+ mmio_write_32(GPC_GLOBAL_BASE + PMIC_CTRL, en ? 1 : 0);
+}
+
+static inline void gpc_rosc_off(bool off)
+{
+ mmio_write_32(GPC_GLOBAL_BASE + GPC_ROSC_CTRL, off ? 1 : 0);
+}
+
+static inline void gpc_set_cpu_mode(unsigned int cpu, unsigned int mode)
+{
+ mmio_write_32(CM_SLICE(cpu) + CM_MODE_CTRL, mode);
+}
+
+static inline void gpc_select_wakeup_gic(unsigned int cpu)
+{
+ mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
+}
+
+static inline void gpc_select_wakeup_raw_irq(unsigned int cpu)
+{
+ mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, IRQ_MUX);
+}
+
+static inline void gpc_assert_sw_wakeup(unsigned int cpu)
+{
+ mmio_setbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
+}
+
+static inline void gpc_deassert_sw_wakeup(unsigned int cpu)
+{
+ mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SW_WAKEUP);
+}
+
+static inline void gpc_clear_cpu_sleep_hold(unsigned int cpu)
+{
+ mmio_clrbits_32(CM_SLICE(cpu) + CM_MISC, SLEEP_HOLD_EN);
+}
+
+static inline void gpc_set_irq_mask(unsigned int cpu, unsigned int idx, uint32_t mask)
+{
+ mmio_write_32(CM_SLICE(cpu) + idx * 0x4 + CM_IRQ_WAKEUP_MASK0, mask);
+}
+
+/*******************************************************************************
+ * SRC definitions & declarations
+ ******************************************************************************/
+#define SRC_SLICE(x) (SRC_BASE + 0x400 * (x))
+#define SRC_AUTHEN_CTRL U(0x4)
+#define SRC_LPM_SETTING0 U(0x10)
+#define SRC_LPM_SETTING1 U(0x14)
+#define SRC_LPM_SETTING2 U(0x18)
+#define SRC_SLICE_SW_CTRL U(0x20)
+
+#define SRC_MEM_CTRL U(0x4)
+#define MEM_LP_EN BIT(2)
+#define MEM_LP_RETN BIT(1)
+
+enum mix_mem_mode {
+ MEM_OFF,
+ MEM_RETN,
+};
+
+enum src_mix_mem_slice {
+ SRC_GLOBAL,
+
+ /* MIX slice */
+ SRC_SENTINEL,
+ SRC_AON,
+ SRC_WKUP,
+ SRC_DDR,
+ SRC_DPHY,
+ SRC_ML,
+ SRC_NIC,
+ SRC_HSIO,
+ SRC_MEDIA,
+ SRC_M33P,
+ SRC_A55C0,
+ SRC_A55C1,
+ SRC_A55P,
+
+ /* MEM slice */
+ SRC_AON_MEM,
+ SRC_WKUP_MEM,
+ SRC_DDR_MEM,
+ SRC_DPHY_MEM,
+ SRC_ML_MEM,
+ SRC_NIC_MEM,
+ SRC_NIC_OCRAM,
+ SRC_HSIO_MEM,
+ SRC_MEDIA_MEM,
+ SRC_A55P0_MEM,
+ SRC_A55P1_MEM,
+ SRC_A55_SCU_MEM,
+ SRC_A55_L3_MEM,
+};
+
+static inline void src_authen_config(unsigned int mix, unsigned int wlist,
+ unsigned int lpm_en)
+{
+ mmio_write_32(SRC_SLICE(mix) + SRC_AUTHEN_CTRL, (wlist << 16) | (lpm_en << 2));
+}
+
+static inline void src_mix_set_lpm(unsigned int mix, unsigned int did, unsigned int lpm_mode)
+{
+ mmio_clrsetbits_32(SRC_SLICE(mix) + SRC_LPM_SETTING1 + (did / 8) * 0x4,
+ LPM_SETTING(did, 0x7), LPM_SETTING(did, lpm_mode));
+}
+
+static inline void src_mem_lpm_en(unsigned int mix, bool retn)
+{
+ mmio_setbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | (retn ? MEM_LP_RETN : 0));
+}
+
+static inline void src_mem_lpm_dis(unsigned int mix)
+{
+ mmio_clrbits_32(SRC_SLICE(mix) + SRC_MEM_CTRL, MEM_LP_EN | MEM_LP_RETN);
+}
+
+/*******************************************************************************
+ * BLK_CTRL_S definitions & declarations
+ ******************************************************************************/
+#define HW_LP_HANDHSK U(0x110)
+#define HW_LP_HANDHSK2 U(0x114)
+#define CA55_CPUWAIT U(0x118)
+#define CA55_RVBADDR0_L U(0x11c)
+#define CA55_RVBADDR0_H U(0x120)
+
+/*******************************************************************************
+ * Other definitions & declarations
+ ******************************************************************************/
+void pwr_sys_init(void);
+
+#endif /* PWR_CTRL_H */
+