diff --git a/plat/arm/board/fvp/fvp_common.c b/plat/arm/board/fvp/fvp_common.c
index b885b47..36cd500 100644
--- a/plat/arm/board/fvp/fvp_common.c
+++ b/plat/arm/board/fvp/fvp_common.c
@@ -81,7 +81,7 @@
 	MAP_DEVICE0,
 	MAP_DEVICE1,
 	ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
 	ARM_MAP_DRAM2,
 #endif
 #ifdef SPD_tspd
@@ -150,7 +150,7 @@
 #endif
 #ifdef IMAGE_BL32
 const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
 	ARM_MAP_SHARED_RAM,
 	ARM_V2M_MAP_MEM_PROTECT,
 #endif
diff --git a/plat/arm/board/fvp/include/platform_def.h b/plat/arm/board/fvp/include/platform_def.h
index 207cd31..4f26277 100644
--- a/plat/arm/board/fvp/include/platform_def.h
+++ b/plat/arm/board/fvp/include/platform_def.h
@@ -120,7 +120,7 @@
 #define PLAT_ARM_MAX_BL31_SIZE		UL(0x3B000)
 #endif
 
-#ifdef AARCH32
+#ifndef __aarch64__
 /*
  * Since BL32 NOBITS overlays BL2 and BL1-RW, PLAT_ARM_MAX_BL32_SIZE is
  * calculated using the current SP_MIN PROGBITS debug size plus the sizes of
@@ -259,7 +259,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifdef AARCH64
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/fvp_ve/include/platform_def.h b/plat/arm/board/fvp_ve/include/platform_def.h
index b3b3672..4e575e1 100644
--- a/plat/arm/board/fvp_ve/include/platform_def.h
+++ b/plat/arm/board/fvp_ve/include/platform_def.h
@@ -331,7 +331,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifdef AARCH64
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/juno/include/platform_def.h b/plat/arm/board/juno/include/platform_def.h
index d693c26..83aeeb4 100644
--- a/plat/arm/board/juno/include/platform_def.h
+++ b/plat/arm/board/juno/include/platform_def.h
@@ -291,7 +291,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifdef AARCH64
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/juno/juno_common.c b/plat/arm/board/juno/juno_common.c
index 118c19a..98c5d3c 100644
--- a/plat/arm/board/juno/juno_common.c
+++ b/plat/arm/board/juno/juno_common.c
@@ -37,7 +37,7 @@
 	CSS_MAP_DEVICE,
 	SOC_CSS_MAP_DEVICE,
 	ARM_MAP_NS_DRAM1,
-#ifdef AARCH64
+#ifdef __aarch64__
 	ARM_MAP_DRAM2,
 #endif
 #ifdef SPD_tspd
@@ -74,7 +74,7 @@
 #endif
 #ifdef IMAGE_BL32
 const mmap_region_t plat_arm_mmap[] = {
-#ifdef AARCH32
+#ifndef __aarch64__
 	ARM_MAP_SHARED_RAM,
 #ifdef PLAT_ARM_MEM_PROT_ADDR
 	ARM_V2M_MAP_MEM_PROTECT,
diff --git a/plat/arm/board/n1sdp/include/platform_def.h b/plat/arm/board/n1sdp/include/platform_def.h
index ff583a9..7348bf5 100644
--- a/plat/arm/board/n1sdp/include/platform_def.h
+++ b/plat/arm/board/n1sdp/include/platform_def.h
@@ -34,7 +34,7 @@
  * space the physical & virtual address space limits are extended to
  * 40-bits.
  */
-#ifndef AARCH32
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE		(1ULL << 40)
 #define PLAT_VIRT_ADDR_SPACE_SIZE		(1ULL << 40)
 #else
diff --git a/plat/arm/board/rde1edge/include/platform_def.h b/plat/arm/board/rde1edge/include/platform_def.h
index c62cda8..50b04f0 100644
--- a/plat/arm/board/rde1edge/include/platform_def.h
+++ b/plat/arm/board/rde1edge/include/platform_def.h
@@ -29,7 +29,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifndef AARCH32
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/rdn1edge/include/platform_def.h b/plat/arm/board/rdn1edge/include/platform_def.h
index 2c7b8bd..580ab8e 100644
--- a/plat/arm/board/rdn1edge/include/platform_def.h
+++ b/plat/arm/board/rdn1edge/include/platform_def.h
@@ -30,7 +30,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifndef AARCH32
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/sgi575/include/platform_def.h b/plat/arm/board/sgi575/include/platform_def.h
index 883403b..f00146f 100644
--- a/plat/arm/board/sgi575/include/platform_def.h
+++ b/plat/arm/board/sgi575/include/platform_def.h
@@ -30,7 +30,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifndef AARCH32
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/board/sgm775/include/platform_def.h b/plat/arm/board/sgm775/include/platform_def.h
index 3e1fdd1..27d1b33 100644
--- a/plat/arm/board/sgm775/include/platform_def.h
+++ b/plat/arm/board/sgm775/include/platform_def.h
@@ -15,7 +15,7 @@
 /*
  * Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
  */
-#ifndef AARCH32
+#ifdef __aarch64__
 #define PLAT_PHY_ADDR_SPACE_SIZE	(1ULL << 36)
 #define PLAT_VIRT_ADDR_SPACE_SIZE	(1ULL << 36)
 #else
diff --git a/plat/arm/common/arm_bl1_setup.c b/plat/arm/common/arm_bl1_setup.c
index 8905bb0..b19a7c3 100644
--- a/plat/arm/common/arm_bl1_setup.c
+++ b/plat/arm/common/arm_bl1_setup.c
@@ -121,11 +121,11 @@
 	};
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+	enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
 
 	arm_setup_romlib();
 }
diff --git a/plat/arm/common/arm_bl2_el3_setup.c b/plat/arm/common/arm_bl2_el3_setup.c
index 0c01c87..97b5a88 100644
--- a/plat/arm/common/arm_bl2_el3_setup.c
+++ b/plat/arm/common/arm_bl2_el3_setup.c
@@ -83,10 +83,10 @@
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el3(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 }
 
diff --git a/plat/arm/common/arm_bl2_setup.c b/plat/arm/common/arm_bl2_setup.c
index 32617f6..cdf87ca 100644
--- a/plat/arm/common/arm_bl2_setup.c
+++ b/plat/arm/common/arm_bl2_setup.c
@@ -128,10 +128,10 @@
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 
 	arm_setup_romlib();
@@ -153,7 +153,7 @@
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/arm/common/arm_bl2u_setup.c b/plat/arm/common/arm_bl2u_setup.c
index 9f44b9e..3614c7d 100644
--- a/plat/arm/common/arm_bl2u_setup.c
+++ b/plat/arm/common/arm_bl2u_setup.c
@@ -83,10 +83,10 @@
 
 	setup_page_tables(bl_regions, plat_arm_get_mmap());
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 	arm_setup_romlib();
 }
diff --git a/plat/arm/common/arm_common.c b/plat/arm/common/arm_common.c
index f5ce4d2..bc0cf9a 100644
--- a/plat/arm/common/arm_common.c
+++ b/plat/arm/common/arm_common.c
@@ -59,7 +59,7 @@
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t arm_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -97,7 +97,7 @@
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 /*******************************************************************************
  * Configures access to the system counter timer module.
diff --git a/plat/arm/common/arm_gicv3.c b/plat/arm/common/arm_gicv3.c
index 93bebf3..7f4957f 100644
--- a/plat/arm/common/arm_gicv3.c
+++ b/plat/arm/common/arm_gicv3.c
@@ -83,8 +83,8 @@
 	 * can use GIC system registers to manage interrupts and does
 	 * not need GIC interface base addresses to be configured.
 	 */
-#if (defined(AARCH32) && defined(IMAGE_BL32)) || \
-	(defined(IMAGE_BL31) && !defined(AARCH32))
+#if (!defined(__aarch64__) && defined(IMAGE_BL32)) || \
+	(defined(__aarch64__) && defined(IMAGE_BL31))
 	gicv3_driver_init(&arm_gic_data);
 #endif
 }
diff --git a/plat/arm/common/arm_nor_psci_mem_protect.c b/plat/arm/common/arm_nor_psci_mem_protect.c
index 3a70059..b9181eb 100644
--- a/plat/arm/common/arm_nor_psci_mem_protect.c
+++ b/plat/arm/common/arm_nor_psci_mem_protect.c
@@ -26,7 +26,7 @@
 
 static mem_region_t arm_ram_ranges[] = {
 	{DRAM1_NS_IMAGE_LIMIT, DRAM1_PROTECTED_SIZE},
-#ifdef AARCH64
+#ifdef __aarch64__
 	{ARM_DRAM2_BASE, 1u << ONE_GB_SHIFT},
 #endif
 };
diff --git a/plat/arm/common/arm_pm.c b/plat/arm/common/arm_pm.c
index cb87baf..c95f452 100644
--- a/plat/arm/common/arm_pm.c
+++ b/plat/arm/common/arm_pm.c
@@ -116,7 +116,7 @@
 			(ARM_NS_DRAM1_BASE + ARM_NS_DRAM1_SIZE))) {
 		return 0;
 	}
-#ifndef AARCH32
+#ifdef __aarch64__
 	if ((entrypoint >= ARM_DRAM2_BASE) && (entrypoint <
 			(ARM_DRAM2_BASE + ARM_DRAM2_SIZE))) {
 		return 0;
diff --git a/plat/arm/common/execution_state_switch.c b/plat/arm/common/execution_state_switch.c
index d471130..00ac16e 100644
--- a/plat/arm/common/execution_state_switch.c
+++ b/plat/arm/common/execution_state_switch.c
@@ -40,7 +40,7 @@
 		void *handle)
 {
 	/* Execution state can be switched only if EL3 is AArch64 */
-#ifdef AARCH64
+#ifdef __aarch64__
 	bool caller_64, thumb = false, from_el2;
 	unsigned int el, endianness;
 	u_register_t spsr, pc, scr, sctlr;
@@ -173,7 +173,7 @@
 	SMC_RET1(handle, STATE_SW_E_PARAM);
 
 exec_denied:
-#endif
+#endif /* __aarch64__ */
 	/* State switch denied */
 	SMC_RET1(handle, STATE_SW_E_DENIED);
 }
diff --git a/plat/common/plat_gicv3.c b/plat/common/plat_gicv3.c
index f5ed6fc..4a8a7ee 100644
--- a/plat/common/plat_gicv3.c
+++ b/plat/common/plat_gicv3.c
@@ -300,7 +300,7 @@
 #pragma weak plat_ic_end_of_interrupt
 
 /* In AArch32, the secure group1 interrupts are targeted to Secure PL1 */
-#ifdef AARCH32
+#ifndef __aarch64__
 #define IS_IN_EL1()	IS_IN_SECURE()
 #endif
 
diff --git a/plat/common/plat_psci_common.c b/plat/common/plat_psci_common.c
index 1a29d9c..16bec79 100644
--- a/plat/common/plat_psci_common.c
+++ b/plat/common/plat_psci_common.c
@@ -20,10 +20,10 @@
 #define MHZ_TICKS_PER_SEC 1000000U
 
 /* Maximum time-stamp value read from architectural counters */
-#ifdef AARCH32
-#define MAX_TS	UINT32_MAX
-#else
+#ifdef __aarch64__
 #define MAX_TS	UINT64_MAX
+#else
+#define MAX_TS	UINT32_MAX
 #endif
 
 /* Following are used as ID's to capture time-stamp */
diff --git a/plat/hisilicon/hikey/hikey_bl2_setup.c b/plat/hisilicon/hikey/hikey_bl2_setup.c
index c57fea9..2f96efc 100644
--- a/plat/hisilicon/hikey/hikey_bl2_setup.c
+++ b/plat/hisilicon/hikey/hikey_bl2_setup.c
@@ -77,7 +77,7 @@
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t hikey_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -112,7 +112,7 @@
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int hikey_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -125,7 +125,7 @@
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/hikey/include/hikey_layout.h b/plat/hisilicon/hikey/include/hikey_layout.h
index a87648e..4b8dc53 100644
--- a/plat/hisilicon/hikey/include/hikey_layout.h
+++ b/plat/hisilicon/hikey/include/hikey_layout.h
@@ -113,7 +113,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */
diff --git a/plat/hisilicon/hikey960/hikey960_bl2_setup.c b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
index 7102de8..fc9ddab 100644
--- a/plat/hisilicon/hikey960/hikey960_bl2_setup.c
+++ b/plat/hisilicon/hikey960/hikey960_bl2_setup.c
@@ -168,7 +168,7 @@
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t hikey960_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -203,7 +203,7 @@
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int hikey960_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -216,7 +216,7 @@
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/hikey960/include/platform_def.h b/plat/hisilicon/hikey960/include/platform_def.h
index 7c3c102..f6edad6 100644
--- a/plat/hisilicon/hikey960/include/platform_def.h
+++ b/plat/hisilicon/hikey960/include/platform_def.h
@@ -95,7 +95,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */
diff --git a/plat/hisilicon/poplar/bl2_plat_setup.c b/plat/hisilicon/poplar/bl2_plat_setup.c
index 11403b0..cc9d975 100644
--- a/plat/hisilicon/poplar/bl2_plat_setup.c
+++ b/plat/hisilicon/poplar/bl2_plat_setup.c
@@ -54,7 +54,7 @@
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t poplar_get_spsr_for_bl33_entry(void)
 {
 	unsigned long el_status;
@@ -93,7 +93,7 @@
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 int poplar_bl2_handle_post_image_load(unsigned int image_id)
 {
@@ -107,7 +107,7 @@
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 #ifdef SPD_opteed
 		pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
diff --git a/plat/hisilicon/poplar/include/platform_def.h b/plat/hisilicon/poplar/include/platform_def.h
index 8f7a155..9783f8d 100644
--- a/plat/hisilicon/poplar/include/platform_def.h
+++ b/plat/hisilicon/poplar/include/platform_def.h
@@ -107,7 +107,7 @@
 #endif
 
 /* BL32 is mandatory in AArch32 */
-#ifndef AARCH32
+#ifdef __aarch64__
 #ifdef SPD_none
 #undef BL32_BASE
 #endif /* SPD_none */
diff --git a/plat/layerscape/common/ls_bl1_setup.c b/plat/layerscape/common/ls_bl1_setup.c
index 163b35c..fff065e 100644
--- a/plat/layerscape/common/ls_bl1_setup.c
+++ b/plat/layerscape/common/ls_bl1_setup.c
@@ -59,11 +59,11 @@
 #endif
 			     );
 	VERBOSE("After setup the page tables\n");
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el3(0);
-#endif /* AARCH32 */
+#else
+	enable_mmu_svc_mon(0);
+#endif /* __aarch64__ */
 	VERBOSE("After MMU enabled\n");
 }
 
diff --git a/plat/layerscape/common/ls_bl2_setup.c b/plat/layerscape/common/ls_bl2_setup.c
index 192eaec..35f42e1 100644
--- a/plat/layerscape/common/ls_bl2_setup.c
+++ b/plat/layerscape/common/ls_bl2_setup.c
@@ -54,10 +54,10 @@
 #endif
 			      );
 
-#ifdef AARCH32
-	enable_mmu_svc_mon(0);
-#else
+#ifdef __aarch64__
 	enable_mmu_el1(0);
+#else
+	enable_mmu_svc_mon(0);
 #endif
 }
 
@@ -74,7 +74,7 @@
 	assert(bl_mem_params);
 
 	switch (image_id) {
-#ifdef AARCH64
+#ifdef __aarch64__
 	case BL32_IMAGE_ID:
 		bl_mem_params->ep_info.spsr = ls_get_spsr_for_bl32_entry();
 		break;
diff --git a/plat/layerscape/common/ls_common.c b/plat/layerscape/common/ls_common.c
index 3b42909..23c0d00 100644
--- a/plat/layerscape/common/ls_common.c
+++ b/plat/layerscape/common/ls_common.c
@@ -143,7 +143,7 @@
 /*******************************************************************************
  * Gets SPSR for BL33 entry
  ******************************************************************************/
-#ifndef AARCH32
+#ifdef __aarch64__
 uint32_t ls_get_spsr_for_bl33_entry(void)
 {
 	unsigned int mode;
@@ -181,7 +181,7 @@
 			SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
 	return spsr;
 }
-#endif /* AARCH32 */
+#endif /* __aarch64__ */
 
 /*******************************************************************************
  * Returns Layerscape platform specific memory map regions.
diff --git a/plat/qemu/qemu_bl1_setup.c b/plat/qemu/qemu_bl1_setup.c
index b582151..67f3327 100644
--- a/plat/qemu/qemu_bl1_setup.c
+++ b/plat/qemu/qemu_bl1_setup.c
@@ -41,10 +41,10 @@
  * does basic initialization. Later architectural setup (bl1_arch_setup())
  * does not do anything platform specific.
  *****************************************************************************/
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
 #define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_el3(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL1_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #endif
 
 void bl1_plat_arch_setup(void)
diff --git a/plat/qemu/qemu_bl2_mem_params_desc.c b/plat/qemu/qemu_bl2_mem_params_desc.c
index ba6a4db..a01f2dc 100644
--- a/plat/qemu/qemu_bl2_mem_params_desc.c
+++ b/plat/qemu/qemu_bl2_mem_params_desc.c
@@ -35,7 +35,7 @@
 	  .next_handoff_image_id = INVALID_IMAGE_ID,
 	},
 #else /* EL3_PAYLOAD_BASE */
-#ifdef AARCH64
+#ifdef __aarch64__
 	/* Fill BL31 related information */
 	{ .image_id = BL31_IMAGE_ID,
 
@@ -59,10 +59,10 @@
 	  .next_handoff_image_id = BL33_IMAGE_ID,
 # endif
 	},
-#endif /* AARCH64 */
+#endif /* __aarch64__ */
 # ifdef QEMU_LOAD_BL32
 
-#ifdef AARCH64
+#ifdef __aarch64__
 #define BL32_EP_ATTRIBS		(SECURE | EXECUTABLE)
 #define BL32_IMG_ATTRIBS	0
 #else
diff --git a/plat/qemu/qemu_bl2_setup.c b/plat/qemu/qemu_bl2_setup.c
index b8ca895..4c97c8d 100644
--- a/plat/qemu/qemu_bl2_setup.c
+++ b/plat/qemu/qemu_bl2_setup.c
@@ -81,10 +81,10 @@
 	/* TODO Initialize timer */
 }
 
-#ifdef AARCH32
-#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
-#else
+#ifdef __aarch64__
 #define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_el1(__VA_ARGS__)
+#else
+#define QEMU_CONFIGURE_BL2_MMU(...)	qemu_configure_mmu_svc_mon(__VA_ARGS__)
 #endif
 
 void bl2_plat_arch_setup(void)
@@ -101,7 +101,7 @@
  ******************************************************************************/
 static uint32_t qemu_get_spsr_for_bl32_entry(void)
 {
-#ifdef AARCH64
+#ifdef __aarch64__
 	/*
 	 * The Secure Payload Dispatcher service is responsible for
 	 * setting the SPSR prior to entry into the BL3-2 image.
@@ -119,7 +119,7 @@
 static uint32_t qemu_get_spsr_for_bl33_entry(void)
 {
 	uint32_t spsr;
-#ifdef AARCH64
+#ifdef __aarch64__
 	unsigned int mode;
 
 	/* Figure out what mode we enter the non-secure world in */
diff --git a/plat/qemu/qemu_common.c b/plat/qemu/qemu_common.c
index aee8321..56bf953 100644
--- a/plat/qemu/qemu_common.c
+++ b/plat/qemu/qemu_common.c
@@ -132,11 +132,11 @@
 	}
 
 /* Define EL1 and EL3 variants of the function initialising the MMU */
-#ifdef AARCH32
-DEFINE_CONFIGURE_MMU_EL(svc_mon)
-#else
+#ifdef __aarch64__
 DEFINE_CONFIGURE_MMU_EL(el1)
 DEFINE_CONFIGURE_MMU_EL(el3)
+#else
+DEFINE_CONFIGURE_MMU_EL(svc_mon)
 #endif
 
 
diff --git a/plat/rockchip/common/include/plat_private.h b/plat/rockchip/common/include/plat_private.h
index 9041bdb..714a8bf 100644
--- a/plat/rockchip/common/include/plat_private.h
+++ b/plat/rockchip/common/include/plat_private.h
@@ -60,16 +60,7 @@
 /******************************************************************************
  * Function and variable prototypes
  *****************************************************************************/
-#ifdef AARCH32
-void plat_configure_mmu_svc_mon(unsigned long total_base,
-				unsigned long total_size,
-				unsigned long,
-				unsigned long,
-				unsigned long,
-				unsigned long);
-
-void rockchip_plat_mmu_svc_mon(void);
-#else
+#ifdef __aarch64__
 void plat_configure_mmu_el3(unsigned long total_base,
 			    unsigned long total_size,
 			    unsigned long,
@@ -78,6 +69,15 @@
 			    unsigned long);
 
 void rockchip_plat_mmu_el3(void);
+#else
+void plat_configure_mmu_svc_mon(unsigned long total_base,
+				unsigned long total_size,
+				unsigned long,
+				unsigned long,
+				unsigned long,
+				unsigned long);
+
+void rockchip_plat_mmu_svc_mon(void);
 #endif
 
 void plat_cci_init(void);